Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 70231)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 70232)
@@ -3304,6 +3304,6 @@
                 /*
                  * AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
-                 * We just avoid delivering the TPR-masked interrupt here. TPR will be updated
-                 * always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
+                 * We just avoid delivering the TPR-masked interrupt here. TPR and the force-flag
+                 * will be updated eventually when the TPR is written by the guest.
                  */
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
@@ -3314,7 +3314,7 @@
 
         /*
-         * Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
-         * We can safely call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
-         * nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
+         * Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
+         * interrupt injection. The virtual interrupt injection itself, if any, will be done
+         * by the physical CPU.
          */
         if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
@@ -3419,6 +3419,6 @@
                     /*
                      * AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
-                     * We just avoid delivering the TPR-masked interrupt here. TPR will be updated
-                     * always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
+                     * We just avoid delivering the TPR-masked interrupt here. TPR and the force-flag
+                     * will be updated eventually when the TPR is written by the guest.
                      */
                     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);