VirtualBox

Changeset 67264 in vbox for trunk


Ignore:
Timestamp:
Jun 6, 2017 9:30:19 AM (7 years ago)
Author:
vboxsync
Message:

HDA: More macros executed in a purge.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Audio/DevHDA.cpp

    r67248 r67264  
    203203
    204204#define HDA_REG_WALCLK              13 /* 0x30 */
    205 #define HDA_RMX_WALCLK              /* Not defined! */
     205/* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
    206206
    207207/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
     
    209209 * the datasheet.
    210210 */
    211 #define HDA_REG_SSYNC               14 /* 0x38 */
     211#define HDA_REG_SSYNC               14 /* 0x34 */
    212212#define HDA_RMX_SSYNC               12
    213213
     
    224224#define HDA_RMX_CORBRP              16
    225225#define HDA_CORBRP_RST              RT_BIT(15)  /* CORB Read Pointer Reset */
    226 #define HDA_CORBRP_WP_SHIFT         0
    227 #define HDA_CORBRP_WP_MASK          0xFF
    228226
    229227#define HDA_REG_CORBCTL             19 /* 0x4C */
     
    234232#define HDA_REG_CORBSTS             20 /* 0x4D */
    235233#define HDA_RMX_CORBSTS             18
    236 #define HDA_CORBSTS_CMEI_SHIFT      0
    237234
    238235#define HDA_REG_CORBSIZE            21 /* 0x4E */
    239236#define HDA_RMX_CORBSIZE            19
    240 #define HDA_CORBSIZE_SZ_CAP         0xF0
    241 #define HDA_CORBSIZE_SZ             0x3
    242 /* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
     237/* NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */
    243238
    244239#define HDA_REG_RIRBLBASE           22 /* 0x50 */
     
    251246#define HDA_RMX_RIRBWP              22
    252247#define HDA_RIRBWP_RST              RT_BIT(15)  /* RIRB Write Pointer Reset */
    253 #define HDA_RIRBWP_WP_MASK          0xFF
    254248
    255249#define HDA_REG_RINTCNT             25 /* 0x5A */
     
    270264#define HDA_REG_RIRBSIZE            28 /* 0x5E */
    271265#define HDA_RMX_RIRBSIZE            26
    272 #define HDA_RIRBSIZE_SZ_CAP         0xF0
    273 #define HDA_RIRBSIZE_SZ             0x3
    274 
    275 #define RIRBSIZE_SZ(pThis)          (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
    276 #define RIRBSIZE_SZ_CAP(pThis)      (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
    277 
    278266
    279267#define HDA_REG_IC                  29 /* 0x60 */
     
    290278#define HDA_REG_DPLBASE             32 /* 0x70 */
    291279#define HDA_RMX_DPLBASE             30
    292 #define DPLBASE(pThis)              (HDA_REG((pThis), DPLBASE))
    293280
    294281#define HDA_REG_DPUBASE             33 /* 0x74 */
    295282#define HDA_RMX_DPUBASE             31
    296 #define DPUBASE(pThis)              (HDA_REG((pThis), DPUBASE))
    297283
    298284#define DPBASE_ADDR_MASK            (~(uint64_t)0x7f)
     
    316302#define HDA_RMX_SD6CTL              (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
    317303#define HDA_RMX_SD7CTL              (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
    318 
    319 #define SD(func, num)               SD##num##func
    320304
    321305#define HDA_SDCTL_NUM_MASK          0xF
     
    341325#define HDA_RMX_SD7STS              (HDA_STREAM_RMX_DEF(STS, 0) + 70)
    342326
    343 #define SDSTS(pThis, num)           HDA_REG((pThis), SD(STS, num))
    344327#define HDA_SDSTS_FIFORDY           RT_BIT(5)   /* FIFO Ready */
    345328#define HDA_SDSTS_DESE              RT_BIT(4)   /* Descriptor Error */
     
    428411#define HDA_SDOFIFO_192B            0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
    429412#define HDA_SDOFIFO_256B            0xFF /* 20-, 24-bit Output Streams */
    430 #define SDFIFOS(pThis, num)         HDA_REG((pThis), SD(FIFOS, num))
    431413
    432414#define HDA_REG_SD0FMT              41 /* 0x92; other streams offset by 0x20 */
     
    439421#define HDA_RMX_SD6FMT              (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
    440422#define HDA_RMX_SD7FMT              (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
    441 
    442 #define SDFMT(pThis, num)               (HDA_REG((pThis), SD(FMT, num)))
    443423
    444424#define HDA_REG_SD0BDPL             42 /* 0x98; other streams offset by 0x20 */
     
    994974
    995975/** Same as above for a register *not* stored in memory. */
    996 #define HDA_REG_IDX_LOCAL(abbrev)   0, #abbrev
     976#define HDA_REG_IDX_NOMEM(abbrev)   0, #abbrev
    997977
    998978/** No register description (RD) flags defined. */
    999 #define HDA_RD_FLAG_NONE           UINT32_C(0)
     979#define HDA_RD_FLAG_NONE           0
    1000980/** Writes to SD are allowed while RUN bit is set. */
    1001981#define HDA_RD_FLAG_SD_WRITE_RUN   RT_BIT(0)
     
    10741054    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteINTCTL  , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
    10751055    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
    1076     { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
     1056    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
    10771057    { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
    10781058    { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
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