- Timestamp:
- Jun 6, 2017 9:30:19 AM (7 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Audio/DevHDA.cpp (modified) (13 diffs)
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- Unmodified
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trunk/src/VBox/Devices/Audio/DevHDA.cpp
r67248 r67264 203 203 204 204 #define HDA_REG_WALCLK 13 /* 0x30 */ 205 #define HDA_RMX_WALCLK /* Not defined!*/205 /* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */ 206 206 207 207 /* Note: The HDA specification defines a SSYNC register at offset 0x38. The … … 209 209 * the datasheet. 210 210 */ 211 #define HDA_REG_SSYNC 14 /* 0x3 8*/211 #define HDA_REG_SSYNC 14 /* 0x34 */ 212 212 #define HDA_RMX_SSYNC 12 213 213 … … 224 224 #define HDA_RMX_CORBRP 16 225 225 #define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */ 226 #define HDA_CORBRP_WP_SHIFT 0227 #define HDA_CORBRP_WP_MASK 0xFF228 226 229 227 #define HDA_REG_CORBCTL 19 /* 0x4C */ … … 234 232 #define HDA_REG_CORBSTS 20 /* 0x4D */ 235 233 #define HDA_RMX_CORBSTS 18 236 #define HDA_CORBSTS_CMEI_SHIFT 0237 234 238 235 #define HDA_REG_CORBSIZE 21 /* 0x4E */ 239 236 #define HDA_RMX_CORBSIZE 19 240 #define HDA_CORBSIZE_SZ_CAP 0xF0 241 #define HDA_CORBSIZE_SZ 0x3 242 /* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */ 237 /* NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */ 243 238 244 239 #define HDA_REG_RIRBLBASE 22 /* 0x50 */ … … 251 246 #define HDA_RMX_RIRBWP 22 252 247 #define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */ 253 #define HDA_RIRBWP_WP_MASK 0xFF254 248 255 249 #define HDA_REG_RINTCNT 25 /* 0x5A */ … … 270 264 #define HDA_REG_RIRBSIZE 28 /* 0x5E */ 271 265 #define HDA_RMX_RIRBSIZE 26 272 #define HDA_RIRBSIZE_SZ_CAP 0xF0273 #define HDA_RIRBSIZE_SZ 0x3274 275 #define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)276 #define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)277 278 266 279 267 #define HDA_REG_IC 29 /* 0x60 */ … … 290 278 #define HDA_REG_DPLBASE 32 /* 0x70 */ 291 279 #define HDA_RMX_DPLBASE 30 292 #define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))293 280 294 281 #define HDA_REG_DPUBASE 33 /* 0x74 */ 295 282 #define HDA_RMX_DPUBASE 31 296 #define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))297 283 298 284 #define DPBASE_ADDR_MASK (~(uint64_t)0x7f) … … 316 302 #define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60) 317 303 #define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70) 318 319 #define SD(func, num) SD##num##func320 304 321 305 #define HDA_SDCTL_NUM_MASK 0xF … … 341 325 #define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70) 342 326 343 #define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))344 327 #define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */ 345 328 #define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */ … … 428 411 #define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 429 412 #define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */ 430 #define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))431 413 432 414 #define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */ … … 439 421 #define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60) 440 422 #define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70) 441 442 #define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))443 423 444 424 #define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */ … … 994 974 995 975 /** Same as above for a register *not* stored in memory. */ 996 #define HDA_REG_IDX_ LOCAL(abbrev) 0, #abbrev976 #define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev 997 977 998 978 /** No register description (RD) flags defined. */ 999 #define HDA_RD_FLAG_NONE UINT32_C(0)979 #define HDA_RD_FLAG_NONE 0 1000 980 /** Writes to SD are allowed while RUN bit is set. */ 1001 981 #define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0) … … 1074 1054 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteINTCTL , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */ 1075 1055 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */ 1076 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_ LOCAL(WALCLK) }, /* Wall Clock Counter */1056 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */ 1077 1057 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */ 1078 1058 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
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