- Timestamp:
- May 23, 2017 10:08:01 AM (7 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 4 edited
-
VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (3 diffs)
-
VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h (modified) (1 diff)
-
ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (2 diffs)
-
ValidationKit/bootsectors/bs3-cpu-generated-1.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r67030 r67033 8938 8938 8939 8939 8940 /** Opcode 0x0f 0xe7 - movntq Mq, Pq */ 8940 /** 8941 * @opcode 0xe7 8942 * @opcodesub !11 mr/reg 8943 * @oppfx none 8944 * @opcpuid sse 8945 * @opgroup og_sse1_cachect 8946 * @opxcpttype none 8947 * @optest op1=-1 op2=2 -> op1=2 ftw=0xff 8948 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff 8949 */ 8941 8950 FNIEMOP_DEF(iemOp_movntq_Mq_Pq) 8942 8951 { 8943 IEMOP_MNEMONIC (movntq_Mq_Pq, "movntq Mq,Pq");8952 IEMOP_MNEMONIC2(MR_MEM, MOVNTQ, movntq, Mq_WO, Pq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 8944 8953 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 8945 8954 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)) … … 8953 8962 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8954 8963 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 8955 IEM_MC_ACTUALIZE_FPU_STATE_FOR_ READ();8964 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 8956 8965 8957 8966 IEM_MC_FETCH_MREG_U64(uSrc, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 8958 8967 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 8968 IEM_MC_FPU_TO_MMX_MODE(); 8959 8969 8960 8970 IEM_MC_ADVANCE_RIP(); … … 8962 8972 return VINF_SUCCESS; 8963 8973 } 8964 /* The register, register encoding is invalid. */ 8974 /** 8975 * @opdone 8976 * @opmnemonic ud0fe7reg 8977 * @opcode 0xe7 8978 * @opcodesub 11 mr/reg 8979 * @oppfx f2 8980 * @opunused immediate 8981 * @opcpuid sse 8982 * @optest -> 8983 */ 8965 8984 return IEMOP_RAISE_INVALID_OPCODE(); 8966 8985 } -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r67030 r67033 3364 3364 * @optest op1=-1 op2=2 -> op1=2 3365 3365 * @optest op1=0 op2=-42 -> op1=-42 3366 * @oponly3367 3366 */ 3368 3367 FNIEMOP_DEF(iemOp_vmovq_Wq_Vq) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r67030 r67033 2335 2335 2336 2336 2337 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_Pq(PBS3CG1STATE pThis, unsigned iEncoding) 2338 { 2339 unsigned off; 2340 switch (iEncoding) 2341 { 2342 case 0: 2343 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)); 2344 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/); 2345 break; 2346 case 1: 2347 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)); 2348 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/); 2349 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0; 2350 break; 2351 #if ARCH_BITS == 64 2352 case 2: 2353 off = Bs3Cg1InsertReqPrefix(pThis, 0); 2354 pThis->abCurInstr[off++] = REX__RBX; 2355 off = Bs3Cg1InsertOpcodes(pThis, off); 2356 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg - no +8*/, 0 /*cbMisalign*/); 2357 break; 2358 #endif 2359 2360 default: 2361 return 0; 2362 } 2363 2364 pThis->cbCurInstr = off; 2365 return iEncoding + 1; 2366 } 2367 2368 2337 2369 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding) 2338 2370 { … … 4531 4563 pThis->aOperands[0].cbOp = 4; 4532 4564 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO; 4565 break; 4566 4567 case BS3CG1ENC_MODRM_Mq_WO_Pq: 4568 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Mq_WO_Pq; 4569 pThis->iRmOp = 0; 4570 pThis->iRegOp = 1; 4571 pThis->aOperands[0].cbOp = 8; 4572 pThis->aOperands[1].cbOp = 8; 4573 pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0; 4574 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO; 4575 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; 4533 4576 break; 4534 4577 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r67030 r67033 173 173 BS3CG1ENC_MODRM_Md_RO, 174 174 BS3CG1ENC_MODRM_Md_WO, 175 BS3CG1ENC_MODRM_Mq_WO_Pq, 175 176 BS3CG1ENC_MODRM_Mq_WO_Vq, 176 177 BS3CG1ENC_MODRM_Mq_WO_VqHi,
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