- Timestamp:
- May 22, 2017 12:11:21 PM (7 years ago)
- Location:
- trunk
- Files:
-
- 2 edited
-
include/VBox/disopcode.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/disopcode.h
r67009 r67010 792 792 OP_VMOVQ, 793 793 OP_VMOVDQA, 794 OP_VMOVDQU, 794 795 /** @} */ 795 796 OP_END_OF_OPCODES -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r67009 r67010 2160 2160 * @optest op1=1 op2=2 -> op1=2 2161 2161 * @optest op1=0 op2=-42 -> op1=-42 2162 * @oponly2163 2162 */ 2164 2163 FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx) … … 2229 2228 } 2230 2229 2231 /** Opcode VEX.F3.0F 0x6f - vmovdqu Vx, Wx */ 2232 FNIEMOP_STUB(iemOp_vmovdqu_Vx_Wx); 2233 //FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx) 2234 //{ 2235 // uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2236 // IEMOP_MNEMONIC(vmovdqu_Vdq_Wdq, "movdqu Vdq,Wdq"); 2237 // if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2238 // { 2239 // /* 2240 // * Register, register. 2241 // */ 2242 // IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2243 // IEM_MC_BEGIN(0, 0); 2244 // IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2245 // IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2246 // IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 2247 // (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); 2248 // IEM_MC_ADVANCE_RIP(); 2249 // IEM_MC_END(); 2250 // } 2251 // else 2252 // { 2253 // /* 2254 // * Register, memory. 2255 // */ 2256 // IEM_MC_BEGIN(0, 2); 2257 // IEM_MC_LOCAL(RTUINT128U, u128Tmp); 2258 // IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2259 // 2260 // IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2261 // IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2262 // IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2263 // IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2264 // IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2265 // IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp); 2266 // 2267 // IEM_MC_ADVANCE_RIP(); 2268 // IEM_MC_END(); 2269 // } 2270 // return VINF_SUCCESS; 2271 //} 2230 /** 2231 * @opcode 0x6f 2232 * @oppfx 0xf3 2233 * @opcpuid avx 2234 * @opgroup og_avx_simdint_datamove 2235 * @opxcpttype 4UA 2236 * @optest op1=1 op2=2 -> op1=2 2237 * @optest op1=0 op2=-42 -> op1=-42 2238 */ 2239 FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx) 2240 { 2241 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 2242 Assert(pVCpu->iem.s.uVexLength <= 1); 2243 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2244 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2245 { 2246 /* 2247 * Register, register. 2248 */ 2249 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV(); 2250 IEM_MC_BEGIN(0, 0); 2251 2252 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2253 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 2254 if (pVCpu->iem.s.uVexLength == 0) 2255 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 2256 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); 2257 else 2258 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 2259 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); 2260 IEM_MC_ADVANCE_RIP(); 2261 IEM_MC_END(); 2262 } 2263 else if (pVCpu->iem.s.uVexLength == 0) 2264 { 2265 /* 2266 * Register, memory128. 2267 */ 2268 IEM_MC_BEGIN(0, 2); 2269 IEM_MC_LOCAL(RTUINT128U, u128Tmp); 2270 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2271 2272 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2273 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV(); 2274 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2275 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 2276 2277 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2278 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp); 2279 2280 IEM_MC_ADVANCE_RIP(); 2281 IEM_MC_END(); 2282 } 2283 else 2284 { 2285 /* 2286 * Register, memory256. 2287 */ 2288 IEM_MC_BEGIN(0, 2); 2289 IEM_MC_LOCAL(RTUINT256U, u256Tmp); 2290 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2291 2292 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2293 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV(); 2294 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2295 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 2296 2297 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2298 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u256Tmp); 2299 2300 IEM_MC_ADVANCE_RIP(); 2301 IEM_MC_END(); 2302 } 2303 return VINF_SUCCESS; 2304 } 2272 2305 2273 2306
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