- Timestamp:
- May 5, 2017 7:35:39 PM (7 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
-
include/VBox/disopcode.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (modified) (2 diffs)
-
src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (4 diffs)
-
src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (6 diffs)
-
src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/disopcode.h
r66814 r66815 1081 1081 #define OP_PARM_VqHi OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are accessed. */ 1082 1082 #define OP_PARM_VqHi_WO OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are written. */ 1083 #define OP_PARM_VqZxReg_WO OP_PARM_Vq /**< Annotates that register targets get their upper bits cleared */ 1084 #define OP_PARM_VsdZxReg_WO OP_PARM_Vsd /**< Annotates that register targets get their upper bits cleared. */ 1085 #define OP_PARM_VsdZxReg_WO OP_PARM_Vsd /**< Annotates that register targets get their upper bits cleared. */ 1086 #define OP_PARM_VssZxReg_WO OP_PARM_Vss /**< Annotates that register targets get their upper bits cleared. */ 1083 #define OP_PARM_VqZx_WO OP_PARM_Vq /**< Annotates that the registers get their upper bits cleared */ 1084 #define OP_PARM_VsdZx_WO OP_PARM_Vsd /**< Annotates that the registers get their upper bits cleared. */ 1085 #define OP_PARM_VssZx_WO OP_PARM_Vss /**< Annotates that the registers get their upper bits cleared. */ 1087 1086 #define OP_PARM_Wpd_WO OP_PARM_Wpd /**< Annotates write only operand. */ 1088 1087 #define OP_PARM_Wps_WO OP_PARM_Wps /**< Annotates write only operand. */ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r66814 r66815 251 251 'Pq_WO': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', ), 252 252 'Vss': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ), 253 'VssZx Reg_WO':( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ),253 'VssZx_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ), 254 254 'Vsd': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ), 255 'VsdZx Reg_WO':( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ),255 'VsdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ), 256 256 'Vps': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', ), 257 257 'Vps_WO': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', ), … … 263 263 'VqHi': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', ), 264 264 'VqHi_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', ), 265 'VqZx Reg_WO':( 'IDX_UseModRM', 'reg', '%Vq', 'VqZx', ),265 'VqZx_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'VqZx', ), 266 266 267 267 # Immediate values. -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r66812 r66815 1104 1104 FNIEMOP_DEF(iemOp_movss_Vss_Wss) 1105 1105 { 1106 IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZx Reg_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);1106 IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZx_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 1107 1107 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1108 1108 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) … … 1158 1158 FNIEMOP_DEF(iemOp_movsd_Vsd_Wsd) 1159 1159 { 1160 IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZx Reg_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);1160 IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZx_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 1161 1161 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1162 1162 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) … … 4325 4325 FNIEMOP_DEF(iemOp_movq_Vq_Wq) 4326 4326 { 4327 IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZx Reg_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);4327 IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZx_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 4328 4328 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 4329 4329 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) … … 8402 8402 * Register, register. 8403 8403 */ 8404 IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx Reg_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);8404 IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 8405 8405 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8406 8406 IEM_MC_BEGIN(0, 1); -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66814 r66815 1765 1765 1766 1766 1767 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx Reg_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding)1767 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding) 1768 1768 { 1769 1769 unsigned off; … … 1794 1794 1795 1795 1796 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx Reg_WO_Wsd__OR__MODRM_VqZxReg_WO_Wq(PBS3CG1STATE pThis,1796 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(PBS3CG1STATE pThis, 1797 1797 unsigned iEncoding) 1798 1798 { … … 1824 1824 1825 1825 1826 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx Reg_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)1826 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding) 1827 1827 { 1828 1828 unsigned off; … … 2282 2282 case BS3CG1ENC_MODRM_Vps_WO_Wps: 2283 2283 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_WO_Wps__OR__BS3CG1ENC_MODRM_Vpd_WO_Wpd(pThis, iEncoding); 2284 case BS3CG1ENC_MODRM_VssZx Reg_WO_Wss:2285 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx Reg_WO_Wss(pThis, iEncoding);2286 case BS3CG1ENC_MODRM_VsdZx Reg_WO_Wsd:2287 case BS3CG1ENC_MODRM_VqZx Reg_WO_Wq:2288 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx Reg_WO_Wsd__OR__MODRM_VqZxReg_WO_Wq(pThis, iEncoding);2289 case BS3CG1ENC_MODRM_VqZx Reg_WO_Nq:2290 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx Reg_WO_Nq(pThis, iEncoding);2284 case BS3CG1ENC_MODRM_VssZx_WO_Wss: 2285 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(pThis, iEncoding); 2286 case BS3CG1ENC_MODRM_VsdZx_WO_Wsd: 2287 case BS3CG1ENC_MODRM_VqZx_WO_Wq: 2288 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(pThis, iEncoding); 2289 case BS3CG1ENC_MODRM_VqZx_WO_Nq: 2290 return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(pThis, iEncoding); 2291 2291 2292 2292 case BS3CG1ENC_MODRM_Gv_RO_Ma: … … 2470 2470 break; 2471 2471 2472 case BS3CG1ENC_MODRM_VssZx Reg_WO_Wss:2472 case BS3CG1ENC_MODRM_VssZx_WO_Wss: 2473 2473 pThis->iRmOp = 1; 2474 2474 pThis->iRegOp = 0; … … 2479 2479 break; 2480 2480 2481 case BS3CG1ENC_MODRM_VsdZx Reg_WO_Wsd:2482 case BS3CG1ENC_MODRM_VqZx Reg_WO_Wq:2483 case BS3CG1ENC_MODRM_VqZx Reg_WO_Nq:2481 case BS3CG1ENC_MODRM_VsdZx_WO_Wsd: 2482 case BS3CG1ENC_MODRM_VqZx_WO_Wq: 2483 case BS3CG1ENC_MODRM_VqZx_WO_Nq: 2484 2484 pThis->iRmOp = 1; 2485 2485 pThis->iRegOp = 0; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r66814 r66815 67 67 BS3CG1OP_Vss, 68 68 BS3CG1OP_Vss_WO, 69 BS3CG1OP_VssZx Reg_WO,69 BS3CG1OP_VssZx_WO, 70 70 BS3CG1OP_Vsd, 71 71 BS3CG1OP_Vsd_WO, 72 BS3CG1OP_VsdZx Reg_WO,72 BS3CG1OP_VsdZx_WO, 73 73 BS3CG1OP_Vps, 74 74 BS3CG1OP_Vps_WO, … … 81 81 BS3CG1OP_VqHi, 82 82 BS3CG1OP_VqHi_WO, 83 BS3CG1OP_VqZx Reg_WO,83 BS3CG1OP_VqZx_WO, 84 84 85 85 BS3CG1OP_Ib, … … 131 131 BS3CG1ENC_MODRM_Vpd_WO_Wpd, 132 132 BS3CG1ENC_MODRM_Vps_WO_Wps, 133 BS3CG1ENC_MODRM_VssZx Reg_WO_Wss,134 BS3CG1ENC_MODRM_VsdZx Reg_WO_Wsd,135 BS3CG1ENC_MODRM_VqZx Reg_WO_Wq,136 BS3CG1ENC_MODRM_VqZx Reg_WO_Nq,133 BS3CG1ENC_MODRM_VssZx_WO_Wss, 134 BS3CG1ENC_MODRM_VsdZx_WO_Wsd, 135 BS3CG1ENC_MODRM_VqZx_WO_Wq, 136 BS3CG1ENC_MODRM_VqZx_WO_Nq, 137 137 BS3CG1ENC_MODRM_Mb_RO, 138 138 BS3CG1ENC_MODRM_Md_RO,
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