VirtualBox

Changeset 66815 in vbox for trunk


Ignore:
Timestamp:
May 5, 2017 7:35:39 PM (7 years ago)
Author:
vboxsync
Message:

IEM: s/V\([a-z]*\)ZxReg/V\1ZxReg/g because 'V' can only indicate a register so the 'Reg' part is superfluous.

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/VBox/disopcode.h

    r66814 r66815  
    10811081#define OP_PARM_VqHi            OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are accessed. */
    10821082#define OP_PARM_VqHi_WO         OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are written. */
    1083 #define OP_PARM_VqZxReg_WO      OP_PARM_Vq              /**< Annotates that register targets get their upper bits cleared */
    1084 #define OP_PARM_VsdZxReg_WO     OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
    1085 #define OP_PARM_VsdZxReg_WO     OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
    1086 #define OP_PARM_VssZxReg_WO     OP_PARM_Vss             /**< Annotates that register targets get their upper bits cleared. */
     1083#define OP_PARM_VqZx_WO         OP_PARM_Vq              /**< Annotates that the registers get their upper bits cleared */
     1084#define OP_PARM_VsdZx_WO        OP_PARM_Vsd             /**< Annotates that the registers get their upper bits cleared. */
     1085#define OP_PARM_VssZx_WO        OP_PARM_Vss             /**< Annotates that the registers get their upper bits cleared. */
    10871086#define OP_PARM_Wpd_WO          OP_PARM_Wpd             /**< Annotates write only operand. */
    10881087#define OP_PARM_Wps_WO          OP_PARM_Wps             /**< Annotates write only operand. */
  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

    r66814 r66815  
    251251    'Pq_WO':        ( 'IDX_UseModRM',       'reg',    '%Pq',  'Pq',      ),
    252252    'Vss':          ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
    253     'VssZxReg_WO':  ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
     253    'VssZx_WO':     ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
    254254    'Vsd':          ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
    255     'VsdZxReg_WO':  ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
     255    'VsdZx_WO':     ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
    256256    'Vps':          ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),
    257257    'Vps_WO':       ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),
     
    263263    'VqHi':         ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
    264264    'VqHi_WO':      ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
    265     'VqZxReg_WO':   ( 'IDX_UseModRM',       'reg',    '%Vq',  'VqZx',    ),
     265    'VqZx_WO':      ( 'IDX_UseModRM',       'reg',    '%Vq',  'VqZx',    ),
    266266
    267267    # Immediate values.
  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

    r66812 r66815  
    11041104FNIEMOP_DEF(iemOp_movss_Vss_Wss)
    11051105{
    1106     IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZxReg_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     1106    IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZx_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
    11071107    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
    11081108    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     
    11581158FNIEMOP_DEF(iemOp_movsd_Vsd_Wsd)
    11591159{
    1160     IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZxReg_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     1160    IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZx_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
    11611161    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
    11621162    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     
    43254325FNIEMOP_DEF(iemOp_movq_Vq_Wq)
    43264326{
    4327     IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZxReg_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     4327    IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZx_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
    43284328    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
    43294329    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     
    84028402         * Register, register.
    84038403         */
    8404         IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZxReg_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     8404        IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
    84058405        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
    84068406        IEM_MC_BEGIN(0, 1);
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66814 r66815  
    17651765
    17661766
    1767 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
     1767static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
    17681768{
    17691769    unsigned off;
     
    17941794
    17951795
    1796 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd__OR__MODRM_VqZxReg_WO_Wq(PBS3CG1STATE pThis,
     1796static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(PBS3CG1STATE pThis,
    17971797                                                                                                  unsigned iEncoding)
    17981798{
     
    18241824
    18251825
    1826 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
     1826static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
    18271827{
    18281828    unsigned off;
     
    22822282        case BS3CG1ENC_MODRM_Vps_WO_Wps:
    22832283            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_WO_Wps__OR__BS3CG1ENC_MODRM_Vpd_WO_Wpd(pThis, iEncoding);
    2284         case BS3CG1ENC_MODRM_VssZxReg_WO_Wss:
    2285             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_WO_Wss(pThis, iEncoding);
    2286         case BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd:
    2287         case BS3CG1ENC_MODRM_VqZxReg_WO_Wq:
    2288             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd__OR__MODRM_VqZxReg_WO_Wq(pThis, iEncoding);
    2289         case BS3CG1ENC_MODRM_VqZxReg_WO_Nq:
    2290             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_WO_Nq(pThis, iEncoding);
     2284        case BS3CG1ENC_MODRM_VssZx_WO_Wss:
     2285            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(pThis, iEncoding);
     2286        case BS3CG1ENC_MODRM_VsdZx_WO_Wsd:
     2287        case BS3CG1ENC_MODRM_VqZx_WO_Wq:
     2288            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(pThis, iEncoding);
     2289        case BS3CG1ENC_MODRM_VqZx_WO_Nq:
     2290            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(pThis, iEncoding);
    22912291
    22922292        case BS3CG1ENC_MODRM_Gv_RO_Ma:
     
    24702470            break;
    24712471
    2472         case BS3CG1ENC_MODRM_VssZxReg_WO_Wss:
     2472        case BS3CG1ENC_MODRM_VssZx_WO_Wss:
    24732473            pThis->iRmOp             = 1;
    24742474            pThis->iRegOp            = 0;
     
    24792479            break;
    24802480
    2481         case BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd:
    2482         case BS3CG1ENC_MODRM_VqZxReg_WO_Wq:
    2483         case BS3CG1ENC_MODRM_VqZxReg_WO_Nq:
     2481        case BS3CG1ENC_MODRM_VsdZx_WO_Wsd:
     2482        case BS3CG1ENC_MODRM_VqZx_WO_Wq:
     2483        case BS3CG1ENC_MODRM_VqZx_WO_Nq:
    24842484            pThis->iRmOp             = 1;
    24852485            pThis->iRegOp            = 0;
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

    r66814 r66815  
    6767    BS3CG1OP_Vss,
    6868    BS3CG1OP_Vss_WO,
    69     BS3CG1OP_VssZxReg_WO,
     69    BS3CG1OP_VssZx_WO,
    7070    BS3CG1OP_Vsd,
    7171    BS3CG1OP_Vsd_WO,
    72     BS3CG1OP_VsdZxReg_WO,
     72    BS3CG1OP_VsdZx_WO,
    7373    BS3CG1OP_Vps,
    7474    BS3CG1OP_Vps_WO,
     
    8181    BS3CG1OP_VqHi,
    8282    BS3CG1OP_VqHi_WO,
    83     BS3CG1OP_VqZxReg_WO,
     83    BS3CG1OP_VqZx_WO,
    8484
    8585    BS3CG1OP_Ib,
     
    131131    BS3CG1ENC_MODRM_Vpd_WO_Wpd,
    132132    BS3CG1ENC_MODRM_Vps_WO_Wps,
    133     BS3CG1ENC_MODRM_VssZxReg_WO_Wss,
    134     BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd,
    135     BS3CG1ENC_MODRM_VqZxReg_WO_Wq,
    136     BS3CG1ENC_MODRM_VqZxReg_WO_Nq,
     133    BS3CG1ENC_MODRM_VssZx_WO_Wss,
     134    BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
     135    BS3CG1ENC_MODRM_VqZx_WO_Wq,
     136    BS3CG1ENC_MODRM_VqZx_WO_Nq,
    137137    BS3CG1ENC_MODRM_Mb_RO,
    138138    BS3CG1ENC_MODRM_Md_RO,
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette