VirtualBox

Changeset 66392 in vbox for trunk


Ignore:
Timestamp:
Apr 2, 2017 7:44:26 PM (8 years ago)
Author:
vboxsync
Message:

x86.h,IEMAll.cpp,bs3-cpu-generated-1: s/X86_MXSCR_/X86_MXCSR_/

Location:
trunk
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/iprt/x86.h

    r66314 r66392  
    28282828 * @{ */
    28292829/** Exception Flag: Invalid operation.  */
    2830 #define X86_MXSCR_IE          RT_BIT_32(0)
     2830#define X86_MXCSR_IE          RT_BIT_32(0)
    28312831/** Exception Flag: Denormalized operand.  */
    2832 #define X86_MXSCR_DE          RT_BIT_32(1)
     2832#define X86_MXCSR_DE          RT_BIT_32(1)
    28332833/** Exception Flag: Zero divide.  */
    2834 #define X86_MXSCR_ZE          RT_BIT_32(2)
     2834#define X86_MXCSR_ZE          RT_BIT_32(2)
    28352835/** Exception Flag: Overflow.  */
    2836 #define X86_MXSCR_OE          RT_BIT_32(3)
     2836#define X86_MXCSR_OE          RT_BIT_32(3)
    28372837/** Exception Flag: Underflow.  */
    2838 #define X86_MXSCR_UE          RT_BIT_32(4)
     2838#define X86_MXCSR_UE          RT_BIT_32(4)
    28392839/** Exception Flag: Precision.  */
    2840 #define X86_MXSCR_PE          RT_BIT_32(5)
     2840#define X86_MXCSR_PE          RT_BIT_32(5)
    28412841
    28422842/** Denormals are zero. */
    2843 #define X86_MXSCR_DAZ         RT_BIT_32(6)
     2843#define X86_MXCSR_DAZ         RT_BIT_32(6)
    28442844
    28452845/** Exception Mask: Invalid operation. */
    2846 #define X86_MXSCR_IM          RT_BIT_32(7)
     2846#define X86_MXCSR_IM          RT_BIT_32(7)
    28472847/** Exception Mask: Denormalized operand. */
    2848 #define X86_MXSCR_DM          RT_BIT_32(8)
     2848#define X86_MXCSR_DM          RT_BIT_32(8)
    28492849/** Exception Mask: Zero divide.  */
    2850 #define X86_MXSCR_ZM          RT_BIT_32(9)
     2850#define X86_MXCSR_ZM          RT_BIT_32(9)
    28512851/** Exception Mask: Overflow.  */
    2852 #define X86_MXSCR_OM          RT_BIT_32(10)
     2852#define X86_MXCSR_OM          RT_BIT_32(10)
    28532853/** Exception Mask: Underflow.  */
    2854 #define X86_MXSCR_UM          RT_BIT_32(11)
     2854#define X86_MXCSR_UM          RT_BIT_32(11)
    28552855/** Exception Mask: Precision.  */
    2856 #define X86_MXSCR_PM          RT_BIT_32(12)
     2856#define X86_MXCSR_PM          RT_BIT_32(12)
    28572857
    28582858/** Rounding control mask. */
    2859 #define X86_MXSCR_RC_MASK     UINT16_C(0x6000)
     2859#define X86_MXCSR_RC_MASK     UINT16_C(0x6000)
    28602860/** Rounding control: To nearest. */
    2861 #define X86_MXSCR_RC_NEAREST  UINT16_C(0x0000)
     2861#define X86_MXCSR_RC_NEAREST  UINT16_C(0x0000)
    28622862/** Rounding control: Down. */
    2863 #define X86_MXSCR_RC_DOWN     UINT16_C(0x2000)
     2863#define X86_MXCSR_RC_DOWN     UINT16_C(0x2000)
    28642864/** Rounding control: Up. */
    2865 #define X86_MXSCR_RC_UP       UINT16_C(0x4000)
     2865#define X86_MXCSR_RC_UP       UINT16_C(0x4000)
    28662866/** Rounding control: Towards zero. */
    2867 #define X86_MXSCR_RC_ZERO     UINT16_C(0x6000)
     2867#define X86_MXCSR_RC_ZERO     UINT16_C(0x6000)
    28682868
    28692869/** Flush-to-zero for masked underflow.  */
    2870 #define X86_MXSCR_FZ          RT_BIT_32(15)
     2870#define X86_MXCSR_FZ          RT_BIT_32(15)
    28712871
    28722872/** Misaligned Exception Mask (AMD MISALIGNSSE).  */
    2873 #define X86_MXSCR_MM          RT_BIT_32(17)
     2873#define X86_MXCSR_MM          RT_BIT_32(17)
    28742874/** @} */
    28752875
  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r66391 r66392  
    92519251    /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
    92529252    if (   (GCPtrMem & 15)
    9253         && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
     9253        && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
    92549254        return iemRaiseGeneralProtectionFault0(pVCpu);
    92559255
     
    92849284    /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
    92859285    if (   (GCPtrMem & 15) == 0
    9286         || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
     9286        || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
    92879287    {
    92889288        PCRTUINT128U pu128Src = (PCRTUINT128U)iemMemMapJmp(pVCpu, sizeof(*pu128Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
     
    96099609    /* The lazy approach for now... */
    96109610    if (   (GCPtrMem & 15)
    9611         && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
     9611        && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
    96129612        return iemRaiseGeneralProtectionFault0(pVCpu);
    96139613
     
    96409640    /* The lazy approach for now... */
    96419641    if (   (GCPtrMem & 15) == 0
    9642         || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
     9642        || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
    96439643    {
    96449644        PRTUINT128U pu128Dst = (PRTUINT128U)iemMemMapJmp(pVCpu, sizeof(*pu128Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66391 r66392  
    30463046        pExtCtx->Ctx.x87.FCW   = X86_FCW_MASK_ALL | X86_FCW_PC_64 | X86_FCW_RC_NEAREST;
    30473047        pExtCtx->Ctx.x87.FSW   = 0;
    3048         pExtCtx->Ctx.x87.MXCSR      = X86_MXSCR_IM | X86_MXSCR_DM | X86_MXSCR_RC_NEAREST;
     3048        pExtCtx->Ctx.x87.MXCSR      = X86_MXCSR_IM | X86_MXCSR_DM | X86_MXCSR_RC_NEAREST;
    30493049        pExtCtx->Ctx.x87.MXCSR_MASK = 0;
    30503050        for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
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