- Timestamp:
- Apr 2, 2017 7:44:26 PM (8 years ago)
- Location:
- trunk
- Files:
-
- 3 edited
-
include/iprt/x86.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (4 diffs)
-
src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/iprt/x86.h
r66314 r66392 2828 2828 * @{ */ 2829 2829 /** Exception Flag: Invalid operation. */ 2830 #define X86_MX SCR_IE RT_BIT_32(0)2830 #define X86_MXCSR_IE RT_BIT_32(0) 2831 2831 /** Exception Flag: Denormalized operand. */ 2832 #define X86_MX SCR_DE RT_BIT_32(1)2832 #define X86_MXCSR_DE RT_BIT_32(1) 2833 2833 /** Exception Flag: Zero divide. */ 2834 #define X86_MX SCR_ZE RT_BIT_32(2)2834 #define X86_MXCSR_ZE RT_BIT_32(2) 2835 2835 /** Exception Flag: Overflow. */ 2836 #define X86_MX SCR_OE RT_BIT_32(3)2836 #define X86_MXCSR_OE RT_BIT_32(3) 2837 2837 /** Exception Flag: Underflow. */ 2838 #define X86_MX SCR_UE RT_BIT_32(4)2838 #define X86_MXCSR_UE RT_BIT_32(4) 2839 2839 /** Exception Flag: Precision. */ 2840 #define X86_MX SCR_PE RT_BIT_32(5)2840 #define X86_MXCSR_PE RT_BIT_32(5) 2841 2841 2842 2842 /** Denormals are zero. */ 2843 #define X86_MX SCR_DAZ RT_BIT_32(6)2843 #define X86_MXCSR_DAZ RT_BIT_32(6) 2844 2844 2845 2845 /** Exception Mask: Invalid operation. */ 2846 #define X86_MX SCR_IM RT_BIT_32(7)2846 #define X86_MXCSR_IM RT_BIT_32(7) 2847 2847 /** Exception Mask: Denormalized operand. */ 2848 #define X86_MX SCR_DM RT_BIT_32(8)2848 #define X86_MXCSR_DM RT_BIT_32(8) 2849 2849 /** Exception Mask: Zero divide. */ 2850 #define X86_MX SCR_ZM RT_BIT_32(9)2850 #define X86_MXCSR_ZM RT_BIT_32(9) 2851 2851 /** Exception Mask: Overflow. */ 2852 #define X86_MX SCR_OM RT_BIT_32(10)2852 #define X86_MXCSR_OM RT_BIT_32(10) 2853 2853 /** Exception Mask: Underflow. */ 2854 #define X86_MX SCR_UM RT_BIT_32(11)2854 #define X86_MXCSR_UM RT_BIT_32(11) 2855 2855 /** Exception Mask: Precision. */ 2856 #define X86_MX SCR_PM RT_BIT_32(12)2856 #define X86_MXCSR_PM RT_BIT_32(12) 2857 2857 2858 2858 /** Rounding control mask. */ 2859 #define X86_MX SCR_RC_MASK UINT16_C(0x6000)2859 #define X86_MXCSR_RC_MASK UINT16_C(0x6000) 2860 2860 /** Rounding control: To nearest. */ 2861 #define X86_MX SCR_RC_NEAREST UINT16_C(0x0000)2861 #define X86_MXCSR_RC_NEAREST UINT16_C(0x0000) 2862 2862 /** Rounding control: Down. */ 2863 #define X86_MX SCR_RC_DOWN UINT16_C(0x2000)2863 #define X86_MXCSR_RC_DOWN UINT16_C(0x2000) 2864 2864 /** Rounding control: Up. */ 2865 #define X86_MX SCR_RC_UP UINT16_C(0x4000)2865 #define X86_MXCSR_RC_UP UINT16_C(0x4000) 2866 2866 /** Rounding control: Towards zero. */ 2867 #define X86_MX SCR_RC_ZERO UINT16_C(0x6000)2867 #define X86_MXCSR_RC_ZERO UINT16_C(0x6000) 2868 2868 2869 2869 /** Flush-to-zero for masked underflow. */ 2870 #define X86_MX SCR_FZ RT_BIT_32(15)2870 #define X86_MXCSR_FZ RT_BIT_32(15) 2871 2871 2872 2872 /** Misaligned Exception Mask (AMD MISALIGNSSE). */ 2873 #define X86_MX SCR_MM RT_BIT_32(17)2873 #define X86_MXCSR_MM RT_BIT_32(17) 2874 2874 /** @} */ 2875 2875 -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r66391 r66392 9251 9251 /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */ 9252 9252 if ( (GCPtrMem & 15) 9253 && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MX SCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */9253 && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */ 9254 9254 return iemRaiseGeneralProtectionFault0(pVCpu); 9255 9255 … … 9284 9284 /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */ 9285 9285 if ( (GCPtrMem & 15) == 0 9286 || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MX SCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */9286 || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */ 9287 9287 { 9288 9288 PCRTUINT128U pu128Src = (PCRTUINT128U)iemMemMapJmp(pVCpu, sizeof(*pu128Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R); … … 9609 9609 /* The lazy approach for now... */ 9610 9610 if ( (GCPtrMem & 15) 9611 && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MX SCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */9611 && !(IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */ 9612 9612 return iemRaiseGeneralProtectionFault0(pVCpu); 9613 9613 … … 9640 9640 /* The lazy approach for now... */ 9641 9641 if ( (GCPtrMem & 15) == 0 9642 || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MX SCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */9642 || (IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.MXCSR & X86_MXCSR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */ 9643 9643 { 9644 9644 PRTUINT128U pu128Dst = (PRTUINT128U)iemMemMapJmp(pVCpu, sizeof(*pu128Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W); -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66391 r66392 3046 3046 pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL | X86_FCW_PC_64 | X86_FCW_RC_NEAREST; 3047 3047 pExtCtx->Ctx.x87.FSW = 0; 3048 pExtCtx->Ctx.x87.MXCSR = X86_MX SCR_IM | X86_MXSCR_DM | X86_MXSCR_RC_NEAREST;3048 pExtCtx->Ctx.x87.MXCSR = X86_MXCSR_IM | X86_MXCSR_DM | X86_MXCSR_RC_NEAREST; 3049 3049 pExtCtx->Ctx.x87.MXCSR_MASK = 0; 3050 3050 for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
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