- Timestamp:
- Mar 30, 2017 11:00:19 AM (8 years ago)
- Location:
- trunk
- Files:
-
- 8 edited
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include/VBox/err.h (modified) (2 diffs)
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include/VBox/vmm/hm.h (modified) (2 diffs)
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include/VBox/vmm/hm_svm.h (modified) (3 diffs)
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src/VBox/VMM/VMMAll/HMSVMAll.cpp (modified) (6 diffs)
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src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h (modified) (1 diff)
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src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (11 diffs)
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src/VBox/VMM/include/HMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/err.h
r66227 r66356 2128 2128 /** Internal SVM processing error no 5. */ 2129 2129 #define VERR_SVM_IPE_5 (-4065) 2130 /** \#VMEXIT processing failed, initiate shutdown. */2130 /** The nested-guest \#VMEXIT processing failed, initiate shutdown. */ 2131 2131 #define VERR_SVM_VMEXIT_FAILED (-4066) 2132 2132 /** An operation caused a nested-guest SVM \#VMEXIT. */ 2133 #define VINF_SVM_VMEXIT 40672133 #define VINF_SVM_VMEXIT 4067 2134 2134 /** @} */ 2135 2135 … … 2174 2174 /** Resume guest execution after injecting a double-fault. */ 2175 2175 #define VINF_HM_DOUBLE_FAULT 4117 2176 /** The requested nested-guest VM-exit intercept is not active or not in 2177 * nested-guest execution mode. */ 2178 #define VINF_HM_INTERCEPT_NOT_ACTIVE 4118 2176 2179 /** @} */ 2177 2180 -
trunk/include/VBox/vmm/hm.h
r66318 r66356 149 149 VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu); 150 150 151 /** @name Nested hardware virtualization. 152 * @{ 153 */ 151 154 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstVmExit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, 152 155 uint64_t uExitInfo2); … … 156 159 VMM_INT_DECL(int) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt); 157 160 VMM_INT_DECL(bool) HMSvmNstGstIsInterruptPending(PCCPUMCTX pCtx); 161 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, 162 uint64_t uExitInfo1,uint64_t uExitInfo2); 163 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite); 164 /** @} */ 158 165 159 166 #ifndef IN_RC -
trunk/include/VBox/vmm/hm_svm.h
r66301 r66356 177 177 # define SVM_EXIT_EXCEPTION_8 0x48 178 178 # define SVM_EXIT_EXCEPTION_9 0x49 179 # define SVM_EXIT_EXCEPTION_ A0x4A180 # define SVM_EXIT_EXCEPTION_ B0x4B181 # define SVM_EXIT_EXCEPTION_ C0x4C182 # define SVM_EXIT_EXCEPTION_ D0x4D183 # define SVM_EXIT_EXCEPTION_ E0x4E184 # define SVM_EXIT_EXCEPTION_ F0x4F185 # define SVM_EXIT_EXCEPTION_1 00x50186 # define SVM_EXIT_EXCEPTION_1 10x51187 # define SVM_EXIT_EXCEPTION_1 20x52188 # define SVM_EXIT_EXCEPTION_1 30x53189 # define SVM_EXIT_EXCEPTION_ 140x54190 # define SVM_EXIT_EXCEPTION_ 150x55191 # define SVM_EXIT_EXCEPTION_ 160x56192 # define SVM_EXIT_EXCEPTION_ 170x57193 # define SVM_EXIT_EXCEPTION_ 180x58194 # define SVM_EXIT_EXCEPTION_ 190x59195 # define SVM_EXIT_EXCEPTION_ 1A0x5A196 # define SVM_EXIT_EXCEPTION_ 1B0x5B197 # define SVM_EXIT_EXCEPTION_ 1C0x5C198 # define SVM_EXIT_EXCEPTION_ 1D0x5D199 # define SVM_EXIT_EXCEPTION_ 1E0x5E200 # define SVM_EXIT_EXCEPTION_ 1F0x5F179 # define SVM_EXIT_EXCEPTION_10 0x4A 180 # define SVM_EXIT_EXCEPTION_11 0x4B 181 # define SVM_EXIT_EXCEPTION_12 0x4C 182 # define SVM_EXIT_EXCEPTION_13 0x4D 183 # define SVM_EXIT_EXCEPTION_14 0x4E 184 # define SVM_EXIT_EXCEPTION_15 0x4F 185 # define SVM_EXIT_EXCEPTION_16 0x50 186 # define SVM_EXIT_EXCEPTION_17 0x51 187 # define SVM_EXIT_EXCEPTION_18 0x52 188 # define SVM_EXIT_EXCEPTION_19 0x53 189 # define SVM_EXIT_EXCEPTION_20 0x54 190 # define SVM_EXIT_EXCEPTION_21 0x55 191 # define SVM_EXIT_EXCEPTION_22 0x56 192 # define SVM_EXIT_EXCEPTION_23 0x57 193 # define SVM_EXIT_EXCEPTION_24 0x58 194 # define SVM_EXIT_EXCEPTION_25 0x59 195 # define SVM_EXIT_EXCEPTION_26 0x5A 196 # define SVM_EXIT_EXCEPTION_27 0x5B 197 # define SVM_EXIT_EXCEPTION_28 0x5C 198 # define SVM_EXIT_EXCEPTION_29 0x5D 199 # define SVM_EXIT_EXCEPTION_30 0x5E 200 # define SVM_EXIT_EXCEPTION_31 0x5F 201 201 /** Physical maskable interrupt. */ 202 202 # define SVM_EXIT_INTR 0x60 … … 341 341 #define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4) 342 342 /** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */ 343 #define SVM_CTRL_INTERCEPT_CR0 RT_BIT_64(5)343 #define SVM_CTRL_INTERCEPT_CR0_SEL_WRITES RT_BIT_64(5) 344 344 /** Intercept reads of IDTR. */ 345 345 #define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6) … … 385 385 #define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26) 386 386 /** IOIO_PROT Intercept IN/OUT accesses to selected ports. */ 387 #define SVM_CTRL_INTERCEPT_I NOUT_BITMAPRT_BIT_64(27)387 #define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27) 388 388 /** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */ 389 #define SVM_CTRL_INTERCEPT_MSR_ SHADOWRT_BIT_64(28)389 #define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28) 390 390 /** Intercept task switches. */ 391 391 #define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29) -
trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp
r66320 r66356 176 176 177 177 178 #ifndef IN_RC 178 179 /** 179 180 * Performs the operations necessary that are part of the vmrun instruction … … 497 498 * below. */ 498 499 VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */); 499 if (rcStrict == VINF_SVM_VMEXIT) 500 if ( rcStrict == VINF_SVM_VMEXIT 501 || rcStrict == VERR_SVM_VMEXIT_FAILED) 500 502 return rcStrict; 501 503 } … … 605 607 */ 606 608 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, &pCtx->hwvirt.svm.VmcbCtrl, 607 sizeof(pCtx->hwvirt.svm.VmcbCtrl));609 sizeof(pCtx->hwvirt.svm.VmcbCtrl)); 608 610 if (RT_SUCCESS(rc)) 609 611 { … … 666 668 { 667 669 Log(("HMNstGstSvmVmExit: Writing VMCB at %#RGp failed\n", pCtx->hwvirt.svm.GCPhysVmcb)); 670 Assert(!CPUMIsGuestInNestedHwVirtMode(pCtx)); 668 671 rc = VERR_SVM_VMEXIT_FAILED; 669 672 } … … 677 680 return VERR_SVM_IPE_5; 678 681 } 682 683 684 /** 685 * Checks whether an interrupt is pending for the nested-guest. 686 * 687 * @returns VBox status code. 688 * @retval true if there's a pending interrupt, false otherwise. 689 * 690 * @param pCtx The guest-CPU context. 691 */ 692 VMM_INT_DECL(bool) HMSvmNstGstIsInterruptPending(PCCPUMCTX pCtx) 693 { 694 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl; 695 if (!CPUMIsGuestInNestedHwVirtMode(pCtx)) 696 return false; 697 698 X86RFLAGS RFlags; 699 if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking) 700 RFlags.u = pCtx->rflags.u; 701 else 702 RFlags.u = pCtx->hwvirt.svm.HostState.rflags.u; 703 704 if (!RFlags.Bits.u1IF) 705 return false; 706 707 return RT_BOOL(pVmcbCtrl->IntCtrl.n.u1VIrqPending); 708 } 709 710 711 /** 712 * Gets the pending nested-guest interrupt. 713 * 714 * @returns VBox status code. 715 * @retval VINF_SUCCESS on success. 716 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but 717 * can't be delivered due to TPR priority. 718 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC 719 * has been software-disabled since it flagged something was pending, 720 * or other reasons). 721 * 722 * @param pCtx The guest-CPU context. 723 * @param pu8Interrupt Where to store the interrupt. 724 */ 725 VMM_INT_DECL(int) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt) 726 { 727 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl; 728 /** @todo remove later, paranoia for now. */ 729 #ifdef DEBUG_ramshankar 730 Assert(HMSvmNstGstIsInterruptPending(pCtx)); 731 #endif 732 733 *pu8Interrupt = pVmcbCtrl->IntCtrl.n.u8VIntrVector; 734 if ( pVmcbCtrl->IntCtrl.n.u1IgnoreTPR 735 || pVmcbCtrl->IntCtrl.n.u4VIntrPrio > pVmcbCtrl->IntCtrl.n.u8VTPR) 736 return VINF_SUCCESS; 737 738 return VERR_APIC_INTR_MASKED_BY_TPR; 739 } 740 741 742 /** 743 * Handles nested-guest SVM intercepts and performs the \#VMEXIT if the 744 * intercept is active. 745 * 746 * @returns Strict VBox status code. 747 * @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or 748 * we're not executing a nested-guest. 749 * @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred 750 * successfully. 751 * @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT 752 * failed and a shutdown needs to be initiated for the geust. 753 */ 754 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, 755 uint64_t uExitInfo2) 756 { 757 #define HMSVM_VMEXIT_RET() do { return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); } while (0) 758 #define HMSVM_CTRL_INTERCEPT_VMEXIT_RET(a_Intercept) \ 759 do { \ 760 if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \ 761 return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \ 762 break; \ 763 } while (0) 764 765 if (!CPUMIsGuestInNestedHwVirtMode(pCtx)) 766 return VINF_HM_INTERCEPT_NOT_ACTIVE; 767 768 switch (uExitCode) 769 { 770 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3: 771 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7: 772 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: 773 case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: 774 case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: 775 case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23: 776 case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: 777 case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31: 778 if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0))) 779 HMSVM_VMEXIT_RET(); 780 break; 781 782 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3: 783 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7: 784 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11: 785 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15: 786 if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0)) 787 HMSVM_VMEXIT_RET(); 788 break; 789 790 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3: 791 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7: 792 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11: 793 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15: 794 if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0)) 795 HMSVM_VMEXIT_RET(); 796 break; 797 798 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3: 799 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: 800 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: 801 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15: 802 if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0)) 803 HMSVM_VMEXIT_RET(); 804 break; 805 806 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3: 807 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: 808 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: 809 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15: 810 if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0)) 811 HMSVM_VMEXIT_RET(); 812 break; 813 814 case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INTR); 815 case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_NMI); 816 case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_SMI); 817 case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INIT); 818 case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_VINTR); 819 case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES); 820 case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_IDTR_READS); 821 case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_GDTR_READS); 822 case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_LDTR_READS); 823 case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_TR_READS); 824 case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_IDTR_WRITES); 825 case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_GDTR_WRITES); 826 case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_LDTR_WRITES); 827 case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_TR_WRITES); 828 case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_RDTSC); 829 case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_RDPMC); 830 case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_PUSHF); 831 case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_POPF); 832 case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_CPUID); 833 case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_RSM); 834 case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_IRET); 835 case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INTN); 836 case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INVD); 837 case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_PAUSE); 838 case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_HLT); 839 case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INVLPG); 840 case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_INVLPGA); 841 case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_TASK_SWITCH); 842 case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_FERR_FREEZE); 843 case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_SHUTDOWN); 844 case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_VMRUN); 845 case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_VMMCALL); 846 case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_VMLOAD); 847 case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_VMSAVE); 848 case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_STGI); 849 case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_CLGI); 850 case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_SKINIT); 851 case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_RDTSCP); 852 case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_ICEBP); 853 case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_WBINVD); 854 case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_MONITOR); 855 case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_MWAIT); 856 case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_MWAIT_ARMED); 857 case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT_RET(SVM_CTRL_INTERCEPT_XSETBV); 858 859 #if 0 860 case SVM_EXIT_IOIO: 861 { 862 if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT)) 863 { 864 SVMIOIOEXIT IOExitInfo; 865 IOExitInfo.u = uExitInfo1; 866 const volatile void *pvIOPM = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap); 867 uint16_t const offIoBitmap = pVIOPM + (IOExitInfo.n.u16Port / 8); 868 uint16_t const u16Port = IOExitInfo.n.u16Port; 869 uint8_t const cbIoSize = IOExitInfo.n.u1OP32 ? 4 : IOExitInfo.n.u1OP16; 870 } 871 break; 872 } 873 #endif 874 875 case SVM_EXIT_MSR: 876 AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n")); 877 return VERR_SVM_IPE_1; 878 879 case SVM_EXIT_NPF: 880 case SVM_EXIT_AVIC_INCOMPLETE_IPI: 881 case SVM_EXIT_AVIC_NOACCEL: 882 AssertMsgFailed(("Todo Implement.\n")); 883 return VERR_SVM_IPE_1; 884 885 default: 886 AssertMsgFailed(("Unsupported.\n")); 887 return VERR_SVM_IPE_1; 888 } 889 890 return VINF_HM_INTERCEPT_NOT_ACTIVE; 891 892 #undef HMSVM_VMEXIT_RET 893 #undef HMSVM_CTRL_INTERCEPT_VMEXIT_RET 894 } 895 896 897 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite) 898 { 899 /* 900 * Check if any MSRs are being intercepted. 901 */ 902 if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_MSR_PROT)) 903 { 904 Assert(CPUMIsGuestInNestedHwVirtMode(pCtx)); 905 uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ; 906 907 /* 908 * Get the byte and bit offset of the permission bits corresponding to the MSR. 909 */ 910 uint16_t offMsrpm; 911 uint32_t uMsrpmBit; 912 int rc = hmSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); 913 if (RT_SUCCESS(rc)) 914 { 915 Assert(uMsrpmBit < 0x3fff); 916 Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT); 917 if (fWrite) 918 ++uMsrpmBit; 919 920 /* 921 * Check if the bit is set, if so, trigger a #VMEXIT. 922 */ 923 uint8_t *pbMsrpm = (uint8_t *)pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap); 924 pbMsrpm += offMsrpm; 925 if (ASMBitTest(pbMsrpm, uMsrpmBit)) 926 return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */); 927 } 928 else 929 { 930 /* 931 * This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it. 932 */ 933 Log(("HMSvmNstGstHandleIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool\n", idMsr, fWrite)); 934 return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */); 935 } 936 } 937 return VINF_HM_INTERCEPT_NOT_ACTIVE; 938 } 939 940 VMM_INT_DECL(int) hmSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint32_t *puMsrpmBit) 941 { 942 Assert(pbOffMsrpm); 943 Assert(puMsrpmBit); 944 945 /* 946 * MSRPM Layout: 947 * Byte offset MSR range 948 * 0x000 - 0x7ff 0x00000000 - 0x00001fff 949 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff 950 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff 951 * 0x1800 - 0x1fff Reserved 952 * 953 * Each MSR is represented by 2 permission bits (read and write). 954 */ 955 if (idMsr <= 0x00001fff) 956 { 957 /* Pentium-compatible MSRs. */ 958 *pbOffMsrpm = 0; 959 *puMsrpmBit = idMsr << 1; 960 return VINF_SUCCESS; 961 } 962 963 if ( idMsr >= 0xc0000000 964 && idMsr <= 0xc0001fff) 965 { 966 /* AMD Sixth Generation x86 Processor MSRs. */ 967 *pbOffMsrpm = 0x800; 968 *puMsrpmBit = (idMsr - 0xc0000000) << 1; 969 return VINF_SUCCESS; 970 } 971 972 if ( idMsr >= 0xc0010000 973 && idMsr <= 0xc0011fff) 974 { 975 /* AMD Seventh and Eighth Generation Processor MSRs. */ 976 *pbOffMsrpm += 0x1000; 977 *puMsrpmBit = (idMsr - 0xc0001000) << 1; 978 return VINF_SUCCESS; 979 } 980 981 *pbOffMsrpm = 0; 982 *puMsrpmBit = 0; 983 return VERR_OUT_OF_RANGE; 984 } 985 #endif /* !IN_RC */ 679 986 680 987 … … 704 1011 } 705 1012 706 707 /**708 * Checks whether an interrupt is pending for the nested-guest.709 *710 * @returns VBox status code.711 * @retval true if there's a pending interrupt, false otherwise.712 *713 * @param pCtx The guest-CPU context.714 */715 VMM_INT_DECL(bool) HMSvmNstGstIsInterruptPending(PCCPUMCTX pCtx)716 {717 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl;718 if (!CPUMIsGuestInNestedHwVirtMode(pCtx))719 return false;720 721 X86RFLAGS RFlags;722 if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)723 RFlags.u = pCtx->rflags.u;724 else725 RFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;726 727 if (!RFlags.Bits.u1IF)728 return false;729 730 return RT_BOOL(pVmcbCtrl->IntCtrl.n.u1VIrqPending);731 }732 733 734 /**735 * Gets the pending nested-guest interrupt.736 *737 * @returns VBox status code.738 * @retval VINF_SUCCESS on success.739 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but740 * can't be delivered due to TPR priority.741 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC742 * has been software-disabled since it flagged something was pending,743 * or other reasons).744 *745 * @param pCtx The guest-CPU context.746 * @param pu8Interrupt Where to store the interrupt.747 */748 VMM_INT_DECL(int) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt)749 {750 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl;751 /** @todo remove later, paranoia for now. */752 #ifdef DEBUG_ramshankar753 Assert(HMSvmNstGstIsInterruptPending(pCtx));754 #endif755 756 *pu8Interrupt = pVmcbCtrl->IntCtrl.n.u8VIntrVector;757 if ( pVmcbCtrl->IntCtrl.n.u1IgnoreTPR758 || pVmcbCtrl->IntCtrl.n.u4VIntrPrio > pVmcbCtrl->IntCtrl.n.u8VTPR)759 return VINF_SUCCESS;760 761 return VERR_APIC_INTR_MASKED_BY_TPR;762 }763 -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r66326 r66356 3114 3114 * @{ 3115 3115 */ 3116 3117 /** 3118 * Initiates a CPU shutdown sequence. 3119 * 3120 * @returns Strict VBox status code. 3121 * @param pVCpu The cross context virtual CPU structure of the 3122 * calling thread. 3123 */ 3124 IEM_STATIC VBOXSTRICTRC iemInitiateCpuShutdown(PVMCPU pVCpu) 3125 { 3126 RT_NOREF_PV(pVCpu); 3127 /** @todo Probably need a separate error code and handling for this to 3128 * distinguish it from the regular triple fault. */ 3129 return VINF_EM_TRIPLE_FAULT; 3130 } 3116 3131 3117 3132 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
r66327 r66356 5908 5908 } 5909 5909 else if (rcStrict == VERR_SVM_VMEXIT_FAILED) 5910 { 5911 /** @todo We're supposed to do a "shutdown" but I don't think we have anything 5912 * for that, so a VM reset is probably the closest. */ 5913 rcStrict = VINF_EM_RESET; 5914 } 5910 rcStrict = iemInitiateCpuShutdown(pVCpu); 5915 5911 return rcStrict; 5916 5912 } -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r66301 r66356 586 586 static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite) 587 587 { 588 unsigned uBit; 588 uint16_t offMsrpm; 589 uint32_t uMsrpmBit; 590 int rc = hmSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit); 591 AssertRC(rc); 592 593 Assert(uMsrpmBit < 0x3fff); 594 Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT); 595 589 596 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap; 590 591 /* 592 * Layout: 593 * Byte offset MSR range 594 * 0x000 - 0x7ff 0x00000000 - 0x00001fff 595 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff 596 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff 597 * 0x1800 - 0x1fff Reserved 598 */ 599 if (uMsr <= 0x00001FFF) 600 { 601 /* Pentium-compatible MSRs. */ 602 uBit = uMsr * 2; 603 } 604 else if ( uMsr >= 0xC0000000 605 && uMsr <= 0xC0001FFF) 606 { 607 /* AMD Sixth Generation x86 Processor MSRs. */ 608 uBit = (uMsr - 0xC0000000) * 2; 609 pbMsrBitmap += 0x800; 610 } 611 else if ( uMsr >= 0xC0010000 612 && uMsr <= 0xC0011FFF) 613 { 614 /* AMD Seventh and Eighth Generation Processor MSRs. */ 615 uBit = (uMsr - 0xC0001000) * 2; 616 pbMsrBitmap += 0x1000; 617 } 597 pbMsrBitmap += offMsrpm; 598 599 if (enmRead == SVMMSREXIT_INTERCEPT_READ) 600 ASMBitSet(pbMsrBitmap, uMsrpmBit); 618 601 else 619 { 620 AssertFailed(); 621 return; 622 } 623 624 Assert(uBit < 0x3fff /* 16 * 1024 - 1 */); 625 if (enmRead == SVMMSREXIT_INTERCEPT_READ) 626 ASMBitSet(pbMsrBitmap, uBit); 602 ASMBitClear(pbMsrBitmap, uMsrpmBit); 603 604 if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE) 605 ASMBitSet(pbMsrBitmap, uMsrpmBit + 1); 627 606 else 628 ASMBitClear(pbMsrBitmap, uBit); 629 630 if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE) 631 ASMBitSet(pbMsrBitmap, uBit + 1); 632 else 633 ASMBitClear(pbMsrBitmap, uBit + 1); 607 ASMBitClear(pbMsrBitmap, uMsrpmBit + 1); 634 608 635 609 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; … … 699 673 | SVM_CTRL_INTERCEPT_RSM /* RSM causes a #VMEXIT. */ 700 674 | SVM_CTRL_INTERCEPT_HLT /* HLT causes a #VMEXIT. */ 701 | SVM_CTRL_INTERCEPT_I NOUT_BITMAP/* Use the IOPM to cause IOIO #VMEXITs. */702 | SVM_CTRL_INTERCEPT_MSR_ SHADOW/* MSR access not covered by MSRPM causes a #VMEXIT.*/675 | SVM_CTRL_INTERCEPT_IOIO_PROT /* Use the IOPM to cause IOIO #VMEXITs. */ 676 | SVM_CTRL_INTERCEPT_MSR_PROT /* MSR access not covered by MSRPM causes a #VMEXIT.*/ 703 677 | SVM_CTRL_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */ 704 678 | SVM_CTRL_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */ … … 3525 3499 return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient); 3526 3500 3527 case SVM_EXIT_EXCEPTION_ E:/* X86_XCPT_PF */3501 case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */ 3528 3502 return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient); 3529 3503 … … 3531 3505 return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient); 3532 3506 3533 case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */3507 case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */ 3534 3508 return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient); 3535 3509 3536 case SVM_EXIT_EXCEPTION_1 0: /* X86_XCPT_MF */3510 case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */ 3537 3511 return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient); 3538 3512 … … 3540 3514 return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient); 3541 3515 3542 case SVM_EXIT_EXCEPTION_1 1: /* X86_XCPT_AC */3516 case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */ 3543 3517 return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient); 3544 3518 3545 case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */3519 case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */ 3546 3520 return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient); 3547 3521 … … 3657 3631 /* SVM_EXIT_EXCEPTION_1: */ /* X86_XCPT_DB - Handled above. */ 3658 3632 case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */ 3659 /* case SVM_EXIT_EXCEPTION_3: *//* X86_XCPT_BP - Handled above. */3633 /* SVM_EXIT_EXCEPTION_3: */ /* X86_XCPT_BP - Handled above. */ 3660 3634 case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */ 3661 3635 case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */ 3662 /* case SVM_EXIT_EXCEPTION_6: *//* X86_XCPT_UD - Handled above. */3636 /* SVM_EXIT_EXCEPTION_6: */ /* X86_XCPT_UD - Handled above. */ 3663 3637 /* SVM_EXIT_EXCEPTION_7: */ /* X86_XCPT_NM - Handled above. */ 3664 3638 case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */ 3665 3639 case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */ 3666 case SVM_EXIT_EXCEPTION_ A:/* X86_XCPT_TS */3667 case SVM_EXIT_EXCEPTION_ B:/* X86_XCPT_NP */3668 case SVM_EXIT_EXCEPTION_ C:/* X86_XCPT_SS */3669 case SVM_EXIT_EXCEPTION_ D:/* X86_XCPT_GP */3670 /* SVM_EXIT_EXCEPTION_ E: *//* X86_XCPT_PF - Handled above. */3671 /* SVM_EXIT_EXCEPTION_10: */ /* X86_XCPT_MF - Handled above. */3672 /* SVM_EXIT_EXCEPTION_1 1: */ /* X86_XCPT_AC- Handled above. */3673 case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC*/3674 case SVM_EXIT_EXCEPTION_1 3: /* X86_XCPT_XF*/3675 case SVM_EXIT_EXCEPTION_ F: /* Reserved*/3676 case SVM_EXIT_EXCEPTION_ 14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:3677 case SVM_EXIT_EXCEPTION_ 17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:3678 case SVM_EXIT_EXCEPTION_ 1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:3679 case SVM_EXIT_EXCEPTION_ 1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:3640 case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */ 3641 case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */ 3642 case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */ 3643 case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */ 3644 /* SVM_EXIT_EXCEPTION_14: */ /* X86_XCPT_PF - Handled above. */ 3645 case SVM_EXIT_EXCEPTION_15: /* Reserved. */ 3646 /* SVM_EXIT_EXCEPTION_16: */ /* X86_XCPT_MF - Handled above. */ 3647 /* SVM_EXIT_EXCEPTION_17: */ /* X86_XCPT_AC - Handled above. */ 3648 case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */ 3649 case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */ 3650 case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: 3651 case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: 3652 case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: 3653 case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31: 3680 3654 { 3681 3655 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; … … 4024 3998 if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION) 4025 3999 { 4026 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_ 1F)4000 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31) 4027 4001 { 4028 4002 uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0); … … 4086 4060 fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI); 4087 4061 4088 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_ 1F)4062 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31) 4089 4063 { 4090 4064 uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0); … … 5208 5182 5209 5183 /** 5210 * \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_ E).5184 * \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14). 5211 5185 * Conditional \#VMEXIT. 5212 5186 */ … … 5426 5400 5427 5401 /** 5428 * \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_1 0).5402 * \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16). 5429 5403 * Conditional \#VMEXIT. 5430 5404 */ … … 5516 5490 5517 5491 /** 5518 * \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_1 1).5492 * \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17). 5519 5493 * Conditional \#VMEXIT. 5520 5494 */ -
trunk/src/VBox/VMM/include/HMInternal.h
r66281 r66356 1103 1103 1104 1104 VMM_INT_DECL(TRPMEVENT) hmSvmEventToTrpmEventType(PCSVMEVENT pSvmEvent); 1105 VMM_INT_DECL(int) hmSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint32_t *puMsrpmBit); 1106 1105 1107 1106 1108 #ifdef IN_RING0
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