- Timestamp:
- Mar 28, 2017 2:49:17 PM (8 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 6 edited
-
VMM/VMMAll/IEMAll.cpp (modified) (1 diff)
-
VMM/VMMAll/IEMAllInstructionsPython.py (modified) (2 diffs)
-
VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (4 diffs)
-
VMM/testcase/tstIEMCheckMc.cpp (modified) (1 diff)
-
ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (6 diffs)
-
ValidationKit/bootsectors/bs3-cpu-generated-1.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r66159 r66306 10767 10767 IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.aXMM[(a_iXReg)].au64[1] = 0; \ 10768 10768 } while (0) 10769 #define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \ 10770 do { IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0) 10769 10771 #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \ 10770 10772 do { IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState)->x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r66303 r66306 161 161 'Ew': ( 'IDX_UseModRM', 'rm', '%Ew', 'Ew', ), 162 162 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', 'Ev', ), 163 'Wss': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', ), 163 164 'Wsd': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', ), 164 165 'Wps': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', ), … … 172 173 'Gw': ( 'IDX_UseModRM', 'reg', '%Gw', 'Gw', ), 173 174 'Gv': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', ), 175 'Vss': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ), 174 176 'Vsd': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ), 175 177 'Vps': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', ), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r66303 r66306 1080 1080 * @oppfx none 1081 1081 * @opcpuid sse 1082 * @opgroup og_sse 2_pcksclr_datamov1082 * @opgroup og_sse_simdfp_datamove 1083 1083 * @opxcpttype 4UA 1084 1084 * @optest op1=1 op2=2 -> op1=2 … … 1132 1132 * @oppfx 0x66 1133 1133 * @opcpuid sse2 1134 * @opgroup og_sse2_pcksclr_datamov 1134 * @opgroup og_sse2_pcksclr_datamove 1135 1135 * @opxcpttype 4UA 1136 1136 * @optest op1=1 op2=2 -> op1=2 … … 1180 1180 1181 1181 1182 /** Opcode 0xf3 0x0f 0x11 - vmovss Wss, Hx, Vss */ 1183 FNIEMOP_STUB(iemOp_vmovss_Wss_Hx_Vss); 1182 /** 1183 * @opcode 0x11 1184 * @oppfx 0xf3 1185 * @opcpuid sse 1186 * @opgroup og_sse_simdfp_datamove 1187 * @opxcpttype 5 1188 * @optest op1=1 op2=2 -> op1=2 1189 * @optest op1=0 op2=-22 -> op1=-22 1190 * @oponlytest 1191 */ 1192 FNIEMOP_DEF(iemOp_vmovss_Wss_Hx_Vss) 1193 { 1194 IEMOP_MNEMONIC2(MR, MOVSS, movss, Wss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 1195 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1196 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 1197 { 1198 /* 1199 * Register, register. 1200 */ 1201 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1202 IEM_MC_BEGIN(0, 1); 1203 IEM_MC_LOCAL(uint32_t, uSrc); 1204 1205 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1206 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 1207 IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); 1208 IEM_MC_STORE_XREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc); 1209 1210 IEM_MC_ADVANCE_RIP(); 1211 IEM_MC_END(); 1212 } 1213 else 1214 { 1215 /* 1216 * Memory, register. 1217 */ 1218 IEM_MC_BEGIN(0, 2); 1219 IEM_MC_LOCAL(uint32_t, uSrc); 1220 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 1221 1222 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 1223 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1224 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1225 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 1226 1227 IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); 1228 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1229 1230 IEM_MC_ADVANCE_RIP(); 1231 IEM_MC_END(); 1232 } 1233 return VINF_SUCCESS; 1234 } 1235 1184 1236 1185 1237 /** … … 1187 1239 * @oppfx 0xf2 1188 1240 * @opcpuid sse2 1189 * @opgroup og_sse2_pcksclr_datamov 1190 * @opxcpttype E51241 * @opgroup og_sse2_pcksclr_datamove 1242 * @opxcpttype 5 1191 1243 * @optest op1=1 op2=2 -> op1=2 1192 1244 * @optest op1=0 op2=-42 -> op1=-42 -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r65871 r66306 501 501 #define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; } while (0) 502 502 #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; } while (0) 503 #define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; } while (0) 503 504 #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; } while (0) 504 505 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t *)((uintptr_t)0); CHK_PTYPE(uint128_t *, a_pu128Dst); (void)fSseWrite; } while (0) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66303 r66306 470 470 /* [BS3CG1DST_XMM14_HI] = */ 8, 471 471 /* [BS3CG1DST_XMM15_HI] = */ 8, 472 /* [BS3CG1DST_XMM0_DW0] = */ 4, 473 /* [BS3CG1DST_XMM1_DW0] = */ 4, 474 /* [BS3CG1DST_XMM2_DW0] = */ 4, 475 /* [BS3CG1DST_XMM3_DW0] = */ 4, 476 /* [BS3CG1DST_XMM4_DW0] = */ 4, 477 /* [BS3CG1DST_XMM5_DW0] = */ 4, 478 /* [BS3CG1DST_XMM6_DW0] = */ 4, 479 /* [BS3CG1DST_XMM7_DW0] = */ 4, 480 /* [BS3CG1DST_XMM8_DW0] = */ 4, 481 /* [BS3CG1DST_XMM9_DW0] = */ 4, 482 /* [BS3CG1DST_XMM10_DW0] = */ 4, 483 /* [BS3CG1DST_XMM11_DW0] = */ 4, 484 /* [BS3CG1DST_XMM12_DW0] = */ 4, 485 /* [BS3CG1DST_XMM13_DW0] = */ 4, 486 /* [BS3CG1DST_XMM14_DW0] = */ 4, 487 /* [BS3CG1DST_XMM15_DW0] = */ 4, 472 488 /* [BS3CG1DST_YMM0] = */ 32, 473 489 /* [BS3CG1DST_YMM1] = */ 32, … … 667 683 /* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t), 668 684 /* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t), 685 /* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]), 686 /* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]), 687 /* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]), 688 /* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]), 689 /* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]), 690 /* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]), 691 /* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]), 692 /* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]), 693 /* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]), 694 /* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]), 695 /* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]), 696 /* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]), 697 /* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]), 698 /* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]), 699 /* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]), 700 /* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]), 669 701 670 702 /* [BS3CG1DST_YMM0] = */ ~0U, … … 691 723 #ifdef BS3CG1_DEBUG_CTX_MOD 692 724 /** Destination field names. */ 693 static const struct { char sz[ 8]; } g_aszBs3Cg1DstFields[] =725 static const struct { char sz[10]; } g_aszBs3Cg1DstFields[] = 694 726 { 695 727 { "INVALID" }, … … 864 896 { "XMM14_HI" }, 865 897 { "XMM15_HI" }, 898 { "XMM0_DW0" }, 899 { "XMM1_DW0" }, 900 { "XMM2_DW0" }, 901 { "XMM3_DW0" }, 902 { "XMM4_DW0" }, 903 { "XMM5_DW0" }, 904 { "XMM6_DW0" }, 905 { "XMM7_DW0" }, 906 { "XMM8_DW0" }, 907 { "XMM9_DW0" }, 908 { "XMM10_DW0" }, 909 { "XMM11_DW0" }, 910 { "XMM12_DW0" }, 911 { "XMM13_DW0" }, 912 { "XMM14_DW0" }, 913 { "XMM15_DW0" }, 866 914 { "YMM0" }, 867 915 { "YMM1" }, … … 1233 1281 break; 1234 1282 1283 case BS3CG1ENC_MODRM_Wss_Vss: 1284 if (iEncoding == 0) 1285 { 1286 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)); 1287 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0); 1288 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_DW0; 1289 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0; 1290 } 1291 else if (iEncoding == 1) 1292 { 1293 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0; 1294 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)); 1295 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 4, 0, BS3CG1OPLOC_MEM_RW); 1296 } 1297 else if (iEncoding == 2) 1298 { 1299 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0; 1300 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)); 1301 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 4, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW); 1302 } 1303 else 1304 break; 1305 pThis->cbCurInstr = off; 1306 iEncoding++; 1307 break; 1308 1235 1309 case BS3CG1ENC_MODRM_Wsd_Vsd: 1236 1310 if (iEncoding == 0) … … 1490 1564 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 1491 1565 pThis->aOperands[1].idxField = BS3CG1DST_INVALID; 1566 break; 1567 1568 case BS3CG1ENC_MODRM_Wss_Vss: 1569 pThis->iRmOp = 0; 1570 pThis->iRegOp = 1; 1571 pThis->aOperands[0].cbOp = 4; 1572 pThis->aOperands[1].cbOp = 4; 1573 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX; 1574 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; 1492 1575 break; 1493 1576 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r66303 r66306 44 44 BS3CG1OP_Eb, 45 45 BS3CG1OP_Ev, 46 BS3CG1OP_Wss, 46 47 BS3CG1OP_Wsd, 47 48 BS3CG1OP_Wps, … … 50 51 BS3CG1OP_Gb, 51 52 BS3CG1OP_Gv, 53 BS3CG1OP_Vss, 52 54 BS3CG1OP_Vsd, 53 55 BS3CG1OP_Vps, … … 80 82 BS3CG1ENC_MODRM_Eb_Gb, 81 83 BS3CG1ENC_MODRM_Ev_Gv, 84 BS3CG1ENC_MODRM_Wss_Vss, 82 85 BS3CG1ENC_MODRM_Wsd_Vsd, 83 86 BS3CG1ENC_MODRM_Wps_Vps, … … 461 464 BS3CG1DST_XMM14_HI, 462 465 BS3CG1DST_XMM15_HI, 466 BS3CG1DST_XMM0_DW0, 467 BS3CG1DST_XMM1_DW0, 468 BS3CG1DST_XMM2_DW0, 469 BS3CG1DST_XMM3_DW0, 470 BS3CG1DST_XMM4_DW0, 471 BS3CG1DST_XMM5_DW0, 472 BS3CG1DST_XMM6_DW0, 473 BS3CG1DST_XMM7_DW0, 474 BS3CG1DST_XMM8_DW0, 475 BS3CG1DST_XMM9_DW0, 476 BS3CG1DST_XMM10_DW0, 477 BS3CG1DST_XMM11_DW0, 478 BS3CG1DST_XMM12_DW0, 479 BS3CG1DST_XMM13_DW0, 480 BS3CG1DST_XMM14_DW0, 481 BS3CG1DST_XMM15_DW0, 463 482 /* AVX registers. */ 464 483 BS3CG1DST_YMM0,
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