VirtualBox

Changeset 65960 in vbox


Ignore:
Timestamp:
Mar 6, 2017 11:21:22 PM (8 years ago)
Author:
vboxsync
Message:

DevATA: Started some small cleanups, merge PIIX3ATABmDma.h into DevATA.cpp because it is only used there. Don't use the p prefix for variables containing guest physical addresses and are not meant to be dereferenced directly. Some comments and code layout changes

Location:
trunk/src/VBox/Devices
Files:
1 deleted
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Storage/DevATA.cpp

    r65648 r65960  
    6464#include <VBox/ata.h>
    6565
    66 #include "PIIX3ATABmDma.h"
    6766#include "ATAPIPassthrough.h"
    6867#include "VBoxDD.h"
    … …  
    110109#define ATA_MEDIA_NO_DISC                    0x70    /**< Door closed, no medium */
    111110
     111/** @defgroup grp_piix3atabmdma     PIIX3 ATA Bus Master DMA
     112 * @{
     113 */
     114
     115/** @name BM_STATUS
     116 * @{
     117 */
     118/** Currently performing a DMA operation. */
     119#define BM_STATUS_DMAING 0x01
     120/** An error occurred during the DMA operation. */
     121#define BM_STATUS_ERROR  0x02
     122/** The DMA unit has raised the IDE interrupt line. */
     123#define BM_STATUS_INT    0x04
     124/** User-defined bit 0, commonly used to signal that drive 0 supports DMA. */
     125#define BM_STATUS_D0DMA  0x20
     126/** User-defined bit 1, commonly used to signal that drive 1 supports DMA. */
     127#define BM_STATUS_D1DMA  0x40
     128/** @} */
     129
     130/** @name BM_CMD
     131 * @{
     132 */
     133/** Start the DMA operation. */
     134#define BM_CMD_START     0x01
     135/** Data transfer direction: from device to memory if set. */
     136#define BM_CMD_WRITE     0x08
     137/** @} */
     138
     139/** @} */
    112140
    113141/*********************************************************************************************************************************
    114142*   Structures and Typedefs                                                                                                      *
    115143*********************************************************************************************************************************/
     144/** @defgroup grp_piix3atabmdma     PIIX3 ATA Bus Master DMA
     145 * @{
     146 */
     147/** PIIX3 Bus Master DMA unit state. */
     148typedef struct BMDMAState
     149{
     150    /** Command register. */
     151    uint8_t    u8Cmd;
     152    /** Status register. */
     153    uint8_t    u8Status;
     154    /** Address of the MMIO region in the guest's memory space. */
     155    RTGCPHYS32 GCPhysAddr;
     156} BMDMAState;
     157
     158/** PIIX3 Bus Master DMA descriptor entry. */
     159typedef struct BMDMADesc
     160{
     161    /** Address of the DMA source/target buffer. */
     162    RTGCPHYS32 GCPhysBuffer;
     163    /** Size of the DMA source/target buffer. */
     164    uint32_t   cbBuffer;
     165} BMDMADesc;
     166/** @} */
     167
     168
    116169/**
    117170 * The state of an ATA device.
    … …  
    124177{
    125178    /** Flag indicating whether the current command uses LBA48 mode. */
    126     bool fLBA48;
     179    bool                                fLBA48;
    127180    /** Flag indicating whether this drive implements the ATAPI command set. */
    128     bool fATAPI;
     181    bool                                fATAPI;
    129182    /** Set if this interface has asserted the IRQ. */
    130     bool fIrqPending;
     183    bool                                fIrqPending;
    131184    /** Currently configured number of sectors in a multi-sector transfer. */
    132     uint8_t cMultSectors;
     185    uint8_t                             cMultSectors;
    133186    /** PCHS disk geometry. */
    134     PDMMEDIAGEOMETRY PCHSGeometry;
     187    PDMMEDIAGEOMETRY                    PCHSGeometry;
    135188    /** Total number of sectors on this disk. */
    136     uint64_t cTotalSectors;
     189    uint64_t                            cTotalSectors;
    137190    /** Sector size of the medium. */
    138     uint32_t cbSector;
     191    uint32_t                            cbSector;
    139192    /** Number of sectors to transfer per IRQ. */
    140     uint32_t cSectorsPerIRQ;
     193    uint32_t                            cSectorsPerIRQ;
    141194
    142195    /** ATA/ATAPI register 1: feature (write-only). */
    143     uint8_t uATARegFeature;
     196    uint8_t                             uATARegFeature;
    144197    /** ATA/ATAPI register 1: feature, high order byte. */
    145     uint8_t uATARegFeatureHOB;
     198    uint8_t                             uATARegFeatureHOB;
    146199    /** ATA/ATAPI register 1: error (read-only). */
    147     uint8_t uATARegError;
     200    uint8_t                             uATARegError;
    148201    /** ATA/ATAPI register 2: sector count (read/write). */
    149     uint8_t uATARegNSector;
     202    uint8_t                             uATARegNSector;
    150203    /** ATA/ATAPI register 2: sector count, high order byte. */
    151     uint8_t uATARegNSectorHOB;
     204    uint8_t                             uATARegNSectorHOB;
    152205    /** ATA/ATAPI register 3: sector (read/write). */
    153     uint8_t uATARegSector;
     206    uint8_t                             uATARegSector;
    154207    /** ATA/ATAPI register 3: sector, high order byte. */
    155     uint8_t uATARegSectorHOB;
     208    uint8_t                             uATARegSectorHOB;
    156209    /** ATA/ATAPI register 4: cylinder low (read/write). */
    157     uint8_t uATARegLCyl;
     210    uint8_t                             uATARegLCyl;
    158211    /** ATA/ATAPI register 4: cylinder low, high order byte. */
    159     uint8_t uATARegLCylHOB;
     212    uint8_t                             uATARegLCylHOB;
    160213    /** ATA/ATAPI register 5: cylinder high (read/write). */
    161     uint8_t uATARegHCyl;
     214    uint8_t                             uATARegHCyl;
    162215    /** ATA/ATAPI register 5: cylinder high, high order byte. */
    163     uint8_t uATARegHCylHOB;
     216    uint8_t                             uATARegHCylHOB;
    164217    /** ATA/ATAPI register 6: select drive/head (read/write). */
    165     uint8_t uATARegSelect;
     218    uint8_t                             uATARegSelect;
    166219    /** ATA/ATAPI register 7: status (read-only). */
    167     uint8_t uATARegStatus;
     220    uint8_t                             uATARegStatus;
    168221    /** ATA/ATAPI register 7: command (write-only). */
    169     uint8_t uATARegCommand;
     222    uint8_t                             uATARegCommand;
    170223    /** ATA/ATAPI drive control register (write-only). */
    171     uint8_t uATARegDevCtl;
     224    uint8_t                             uATARegDevCtl;
    172225
    173226    /** Currently active transfer mode (MDMA/UDMA) and speed. */
    174     uint8_t uATATransferMode;
     227    uint8_t                             uATATransferMode;
    175228    /** Current transfer direction. */
    176     uint8_t uTxDir;
     229    uint8_t                             uTxDir;
    177230    /** Index of callback for begin transfer. */
    178     uint8_t iBeginTransfer;
     231    uint8_t                             iBeginTransfer;
    179232    /** Index of callback for source/sink of data. */
    180     uint8_t iSourceSink;
     233    uint8_t                             iSourceSink;
    181234    /** Flag indicating whether the current command transfers data in DMA mode. */
    182     bool fDMA;
     235    bool                                fDMA;
    183236    /** Set to indicate that ATAPI transfer semantics must be used. */
    184     bool fATAPITransfer;
     237    bool                                fATAPITransfer;
    185238
    186239    /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
    187     uint32_t cbTotalTransfer;
     240    uint32_t                            cbTotalTransfer;
    188241    /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
    189     uint32_t cbElementaryTransfer;
     242    uint32_t                            cbElementaryTransfer;
    190243    /** Maximum ATAPI elementary transfer size, PIO only. */
    191     uint32_t cbPIOTransferLimit;
     244    uint32_t                            cbPIOTransferLimit;
    192245    /** ATAPI passthrough transfer size, shared PIO/DMA */
    193     uint32_t cbAtapiPassthroughTransfer;
     246    uint32_t                            cbAtapiPassthroughTransfer;
    194247    /** Current read/write buffer position, shared PIO/DMA. */
    195     uint32_t iIOBufferCur;
     248    uint32_t                            iIOBufferCur;
    196249    /** First element beyond end of valid buffer content, shared PIO/DMA. */
    197     uint32_t iIOBufferEnd;
     250    uint32_t                            iIOBufferEnd;
    198251    /** Align the following fields correctly. */
    199     uint32_t Alignment0;
     252    uint32_t                            Alignment0;
    200253
    201254    /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
    202     uint32_t iIOBufferPIODataStart;
     255    uint32_t                            iIOBufferPIODataStart;
    203256    /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
    204     uint32_t iIOBufferPIODataEnd;
     257    uint32_t                            iIOBufferPIODataEnd;
    205258
    206259    /** ATAPI current LBA position. */
    207     uint32_t iATAPILBA;
     260    uint32_t                            iATAPILBA;
    208261    /** ATAPI current sector size. */
    209     uint32_t cbATAPISector;
     262    uint32_t                            cbATAPISector;
    210263    /** ATAPI current command. */
    211     uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
     264    uint8_t                             aATAPICmd[ATAPI_PACKET_SIZE];
    212265    /** ATAPI sense data. */
    213     uint8_t abATAPISense[ATAPI_SENSE_SIZE];
     266    uint8_t                             abATAPISense[ATAPI_SENSE_SIZE];
    214267    /** HACK: Countdown till we report a newly unmounted drive as mounted. */
    215     uint8_t cNotifiedMediaChange;
     268    uint8_t                             cNotifiedMediaChange;
    216269    /** The same for GET_EVENT_STATUS for mechanism */
    217     volatile uint32_t MediaEventStatus;
     270    volatile uint32_t                   MediaEventStatus;
    218271
    219272    /** Media type if known. */
    220     volatile uint32_t MediaTrackType;
     273    volatile uint32_t                   MediaTrackType;
    221274
    222275    /** The status LED state for this drive. */
    223     PDMLED Led;
     276    PDMLED                              Led;
    224277
    225278    /** Size of I/O buffer. */
    226     uint32_t cbIOBuffer;
     279    uint32_t                            cbIOBuffer;
    227280    /** Pointer to the I/O buffer. */
    228     R3PTRTYPE(uint8_t *) pbIOBufferR3;
     281    R3PTRTYPE(uint8_t *)                pbIOBufferR3;
    229282    /** Pointer to the I/O buffer. */
    230     R0PTRTYPE(uint8_t *) pbIOBufferR0;
     283    R0PTRTYPE(uint8_t *)                pbIOBufferR0;
    231284    /** Pointer to the I/O buffer. */
    232     RCPTRTYPE(uint8_t *) pbIOBufferRC;
    233 
    234     RTRCPTR Aligmnent1; /**< Align the statistics at an 8-byte boundary. */
     285    RCPTRTYPE(uint8_t *)                pbIOBufferRC;
     286
     287    RTRCPTR                             Aligmnent1; /**< Align the statistics at an 8-byte boundary. */
    235288
    236289    /*
    … …  
    239292
    240293    /* Release statistics: number of ATA DMA commands. */
    241     STAMCOUNTER StatATADMA;
     294    STAMCOUNTER                         StatATADMA;
    242295    /* Release statistics: number of ATA PIO commands. */
    243     STAMCOUNTER StatATAPIO;
     296    STAMCOUNTER                         StatATAPIO;
    244297    /* Release statistics: number of ATAPI PIO commands. */
    245     STAMCOUNTER StatATAPIDMA;
     298    STAMCOUNTER                         StatATAPIDMA;
    246299    /* Release statistics: number of ATAPI PIO commands. */
    247     STAMCOUNTER StatATAPIPIO;
     300    STAMCOUNTER                         StatATAPIPIO;
    248301#ifdef VBOX_INSTRUMENT_DMA_WRITES
    249302    /* Release statistics: number of DMA sector writes and the time spent. */
    250     STAMPROFILEADV StatInstrVDWrites;
     303    STAMPROFILEADV                      StatInstrVDWrites;
    251304#endif
    252305
    253306    /** Statistics: number of read operations and the time spent reading. */
    254     STAMPROFILEADV  StatReads;
     307    STAMPROFILEADV                      StatReads;
    255308    /** Statistics: number of bytes read. */
    256     STAMCOUNTER     StatBytesRead;
     309    STAMCOUNTER                         StatBytesRead;
    257310    /** Statistics: number of write operations and the time spent writing. */
    258     STAMPROFILEADV  StatWrites;
     311    STAMPROFILEADV                      StatWrites;
    259312    /** Statistics: number of bytes written. */
    260     STAMCOUNTER     StatBytesWritten;
     313    STAMCOUNTER                         StatBytesWritten;
    261314    /** Statistics: number of flush operations and the time spend flushing. */
    262     STAMPROFILE     StatFlushes;
     315    STAMPROFILE                         StatFlushes;
    263316
    264317    /** Enable passing through commands directly to the ATAPI drive. */
    265     bool            fATAPIPassthrough;
     318    bool                                fATAPIPassthrough;
    266319    /** Flag whether to overwrite inquiry data in passthrough mode. */
    267     bool            fOverwriteInquiry;
     320    bool                                fOverwriteInquiry;
    268321    /** Number of errors we've reported to the release log.
    269322     * This is to prevent flooding caused by something going horribly wrong.
    270323     * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
    271324     * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
    272     uint32_t        cErrors;
     325    uint32_t                            cErrors;
    273326    /** Timestamp of last started command. 0 if no command pending. */
    274     uint64_t        u64CmdTS;
     327    uint64_t                            u64CmdTS;
    275328
    276329    /** Pointer to the attached driver's base interface. */
    277     R3PTRTYPE(PPDMIBASE)            pDrvBase;
     330    R3PTRTYPE(PPDMIBASE)                pDrvBase;
    278331    /** Pointer to the attached driver's block interface. */
    279     R3PTRTYPE(PPDMIMEDIA)           pDrvMedia;
     332    R3PTRTYPE(PPDMIMEDIA)               pDrvMedia;
    280333    /** Pointer to the attached driver's mount interface.
    281334     * This is NULL if the driver isn't a removable unit. */
    282     R3PTRTYPE(PPDMIMOUNT)           pDrvMount;
     335    R3PTRTYPE(PPDMIMOUNT)               pDrvMount;
    283336    /** The base interface. */
    284     PDMIBASE                        IBase;
     337    PDMIBASE                            IBase;
    285338    /** The block port interface. */
    286     PDMIMEDIAPORT                   IPort;
     339    PDMIMEDIAPORT                       IPort;
    287340    /** The mount notify interface. */
    288     PDMIMOUNTNOTIFY                 IMountNotify;
     341    PDMIMOUNTNOTIFY                     IMountNotify;
    289342    /** The LUN #. */
    290     RTUINT                          iLUN;
     343    RTUINT                              iLUN;
    291344#if HC_ARCH_BITS == 64
    292     RTUINT                          Alignment2; /**< Align pDevInsR3 correctly. */
     345    RTUINT                              Alignment2; /**< Align pDevInsR3 correctly. */
    293346#endif
    294347    /** Pointer to device instance. */
    … …  
    330383
    331384
     385/**
     386 * Transfer request forwarded to the async I/O thread.
     387 */
    332388typedef struct ATATransferRequest
    333389{
     390    /** The interface index the request is for. */
     391    uint8_t  iIf;
     392    /** The index of the begin transfer callback to call. */
     393    uint8_t  iBeginTransfer;
     394    /** The index of the source sink callback to call for doing the transfer. */
     395    uint8_t  iSourceSink;
     396    /** How many bytes to transfer. */
     397    uint32_t cbTotalTransfer;
     398    /** Transfer direction. */
     399    uint8_t  uTxDir;
     400} ATATransferRequest;
     401
     402
     403/**
     404 * Abort request forwarded to the async I/O thread.
     405 */
     406typedef struct ATAAbortRequest
     407{
     408    /** The interface index the request is for. */
    334409    uint8_t iIf;
    335     uint8_t iBeginTransfer;
    336     uint8_t iSourceSink;
    337     uint32_t cbTotalTransfer;
    338     uint8_t uTxDir;
    339 } ATATransferRequest;
    340 
    341 
    342 typedef struct ATAAbortRequest
    343 {
    344     uint8_t iIf;
    345     bool fResetDrive;
     410    /** Flag whether to reset the drive. */
     411    bool    fResetDrive;
    346412} ATAAbortRequest;
    347413
    348414
     415/**
     416 * Request type indicator.
     417 */
    349418typedef enum
    350419{
    … …  
    364433
    365434
     435/**
     436 * Combining structure for an ATA request to the async I/O thread
     437 * started with the request type insicator.
     438 */
    366439typedef struct ATARequest
    367440{
    368     ATAAIO ReqType;
     441    /** Request type. */
     442    ATAAIO                 ReqType;
     443    /** Request type dependent data. */
    369444    union
    370445    {
     446        /** Transfer request specific data. */
    371447        ATATransferRequest t;
    372         ATAAbortRequest a;
     448        /** Abort request specific data. */
     449        ATAAbortRequest    a;
    373450    } u;
    374451} ATARequest;
    375452
    376453
     454/**
     455 * The state of an ATA controller containing to devices (master and slave).
     456 */
    377457typedef struct ATACONTROLLER
    378458{
    379459    /** The base of the first I/O Port range. */
    380     RTIOPORT    IOPortBase1;
     460    RTIOPORT            IOPortBase1;
    381461    /** The base of the second I/O Port range. (0 if none) */
    382     RTIOPORT    IOPortBase2;
     462    RTIOPORT            IOPortBase2;
    383463    /** The assigned IRQ. */
    384     RTUINT      irq;
     464    RTUINT              irq;
    385465    /** Access critical section */
    386     PDMCRITSECT lock;
     466    PDMCRITSECT         lock;
    387467
    388468    /** Selected drive. */
    389     uint8_t     iSelectedIf;
     469    uint8_t             iSelectedIf;
    390470    /** The interface on which to handle async I/O. */
    391     uint8_t     iAIOIf;
     471    uint8_t             iAIOIf;
    392472    /** The state of the async I/O thread. */
    393     uint8_t     uAsyncIOState;
     473    uint8_t             uAsyncIOState;
    394474    /** Flag indicating whether the next transfer is part of the current command. */
    395     bool        fChainedTransfer;
     475    bool                fChainedTransfer;
    396476    /** Set when the reset processing is currently active on this controller. */
    397     bool        fReset;
     477    bool                fReset;
    398478    /** Flag whether the current transfer needs to be redone. */
    399     bool        fRedo;
     479    bool                fRedo;
    400480    /** Flag whether the redo suspend has been finished. */
    401     bool        fRedoIdle;
     481    bool                fRedoIdle;
    402482    /** Flag whether the DMA operation to be redone is the final transfer. */
    403     bool        fRedoDMALastDesc;
     483    bool                fRedoDMALastDesc;
    404484    /** The BusMaster DMA state. */
    405     BMDMAState  BmDma;
     485    BMDMAState          BmDma;
    406486    /** Pointer to first DMA descriptor. */
    407     RTGCPHYS32  pFirstDMADesc;
     487    RTGCPHYS32          GCPhysFirstDMADesc;
    408488    /** Pointer to last DMA descriptor. */
    409     RTGCPHYS32  pLastDMADesc;
     489    RTGCPHYS32          GCPhysLastDMADesc;
    410490    /** Pointer to current DMA buffer (for redo operations). */
    411     RTGCPHYS32  pRedoDMABuffer;
     491    RTGCPHYS32          GCPhysRedoDMABuffer;
    412492    /** Size of current DMA buffer (for redo operations). */
    413     uint32_t    cbRedoDMABuffer;
     493    uint32_t            cbRedoDMABuffer;
    414494
    415495    /** The ATA/ATAPI interfaces of this controller. */
    416     ATADevState aIfs[2];
     496    ATADevState         aIfs[2];
    417497
    418498    /** Pointer to device instance. */
    … …  
    446526    /** The lock protecting the request queue. */
    447527    PDMCRITSECT         AsyncIORequestLock;
    448 #if 0 /*HC_ARCH_BITS == 32*/
    449     uint32_t            Alignment0;
    450 #endif
    451528
    452529    /** Timestamp we started the reset. */
    … …  
    454531
    455532    /* Statistics */
    456     STAMCOUNTER     StatAsyncOps;
    457     uint64_t        StatAsyncMinWait;
    458     uint64_t        StatAsyncMaxWait;
    459     STAMCOUNTER     StatAsyncTimeUS;
    460     STAMPROFILEADV  StatAsyncTime;
    461     STAMPROFILE     StatLockWait;
     533    STAMCOUNTER         StatAsyncOps;
     534    uint64_t            StatAsyncMinWait;
     535    uint64_t            StatAsyncMaxWait;
     536    STAMCOUNTER         StatAsyncTimeUS;
     537    STAMPROFILEADV      StatAsyncTime;
     538    STAMPROFILE         StatLockWait;
    462539} ATACONTROLLER, *PATACONTROLLER;
    463540AssertCompileMemberAlignment(ATACONTROLLER, lock, 8);
    … …  
    486563typedef struct PCIATAState
    487564{
    488     PDMPCIDEV           dev;
     565    PDMPCIDEV                       dev;
    489566    /** The controllers. */
    490     ATACONTROLLER       aCts[2];
     567    ATACONTROLLER                   aCts[2];
    491568    /** Pointer to device instance. */
    492     PPDMDEVINSR3        pDevIns;
     569    PPDMDEVINSR3                    pDevIns;
    493570    /** Status LUN: Base interface. */
    494     PDMIBASE            IBase;
     571    PDMIBASE                        IBase;
    495572    /** Status LUN: Leds interface. */
    496     PDMILEDPORTS        ILeds;
     573    PDMILEDPORTS                    ILeds;
    497574    /** Status LUN: Partner of ILeds. */
    498575    R3PTRTYPE(PPDMILEDCONNECTORS)   pLedsConnector;
    … …  
    500577    R3PTRTYPE(PPDMIMEDIANOTIFY)     pMediaNotify;
    501578    /** Flag whether RC is enabled. */
    502     bool                fRCEnabled;
     579    bool                            fRCEnabled;
    503580    /** Flag whether R0 is enabled. */
    504     bool                fR0Enabled;
     581    bool                            fR0Enabled;
    505582    /** Flag indicating chipset being emulated. */
    506     uint8_t             u8Type;
    507     bool                Alignment0[HC_ARCH_BITS == 64 ? 5 : 1 ]; /**< Align the struct size. */
     583    uint8_t                         u8Type;
     584    bool                            Alignment0[HC_ARCH_BITS == 64 ? 5 : 1 ]; /**< Align the struct size. */
    508585} PCIATAState;
    509 
    510 #define PDMIBASE_2_PCIATASTATE(pInterface)      ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, IBase)) )
    511 #define PDMILEDPORTS_2_PCIATASTATE(pInterface)  ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, ILeds)) )
    512 #define PDMIMEDIAPORT_2_ATASTATE(pInterface)    ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
    513 #define PDMIMOUNT_2_ATASTATE(pInterface)        ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMount)) )
    514 #define PDMIMOUNTNOTIFY_2_ATASTATE(pInterface)  ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMountNotify)) )
    515 #define PCIDEV_2_PCIATASTATE(pPciDev)           ( (PCIATAState *)(pPciDev) )
    516586
    517587#define ATACONTROLLER_IDX(pController) ( (pController) - PDMINS_2_DATA(CONTROLLER_2_DEVINS(pController), PCIATAState *)->aCts )
    … …  
    520590#define ATADEVSTATE_2_DEVINS(pIf)              ( (pIf)->CTX_SUFF(pDevIns) )
    521591#define CONTROLLER_2_DEVINS(pController)       ( (pController)->CTX_SUFF(pDevIns) )
    522 #define PDMIBASE_2_ATASTATE(pInterface)        ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
    523 #define PDMIMEDIAPORT_2_ATASTATE(pInterface)   ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
    524592
    525593#ifndef VBOX_DEVICE_STRUCT_TESTCASE
    … …  
    37073775static DECLCALLBACK(void) ataR3MountNotify(PPDMIMOUNTNOTIFY pInterface)
    37083776{
    3709     ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
     3777    ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IMountNotify);
    37103778    Log(("%s: changing LUN#%d\n", __FUNCTION__, pIf->iLUN));
    37113779
    … …  
    37333801static DECLCALLBACK(void) ataR3UnmountNotify(PPDMIMOUNTNOTIFY pInterface)
    37343802{
    3735     ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
     3803    ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IMountNotify);
    37363804    Log(("%s:\n", __FUNCTION__));
    37373805    pIf->cTotalSectors = 0;
    … …  
    51135181    ATADevState *s = &pCtl->aIfs[pCtl->iAIOIf];
    51145182    bool fRedo;
    5115     RTGCPHYS32 pDesc;
     5183    RTGCPHYS32 GCPhysDesc;
    51165184    uint32_t cbTotalTransfer, cbElementaryTransfer;
    51175185    uint32_t iIOBufferCur, iIOBufferEnd;
    5118     uint32_t dmalen;
    51195186    PDMMEDIATXDIR uTxDir;
    51205187    bool fLastDesc = false;
    … …  
    51405207         cbTotalTransfer, cbElementaryTransfer,
    51415208         iIOBufferCur, iIOBufferEnd));
    5142     for (pDesc = pCtl->pFirstDMADesc; pDesc <= pCtl->pLastDMADesc; pDesc += sizeof(BMDMADesc))
     5209    for (GCPhysDesc = pCtl->GCPhysFirstDMADesc;
     5210         GCPhysDesc <= pCtl->GCPhysLastDMADesc;
     5211         GCPhysDesc += sizeof(BMDMADesc))
    51435212    {
    51445213        BMDMADesc DMADesc;
    5145         RTGCPHYS32 pBuffer;
     5214        RTGCPHYS32 GCPhysBuffer;
    51465215        uint32_t cbBuffer;
    51475216
    51485217        if (RT_UNLIKELY(fRedo))
    51495218        {
    5150             pBuffer = pCtl->pRedoDMABuffer;
     5219            GCPhysBuffer = pCtl->GCPhysRedoDMABuffer;
    51515220            cbBuffer = pCtl->cbRedoDMABuffer;
    51525221            fLastDesc = pCtl->fRedoDMALastDesc;
    5153             DMADesc.pBuffer = DMADesc.cbBuffer = 0; /* Shut up MSC. */
     5222            DMADesc.GCPhysBuffer = DMADesc.cbBuffer = 0; /* Shut up MSC. */
    51545223        }
    51555224        else
    51565225        {
    5157             PDMDevHlpPhysRead(pDevIns, pDesc, &DMADesc, sizeof(BMDMADesc));
    5158             pBuffer = RT_LE2H_U32(DMADesc.pBuffer);
     5226            PDMDevHlpPhysRead(pDevIns, GCPhysDesc, &DMADesc, sizeof(BMDMADesc));
     5227            GCPhysBuffer = RT_LE2H_U32(DMADesc.GCPhysBuffer);
    51595228            cbBuffer = RT_LE2H_U32(DMADesc.cbBuffer);
    51605229            fLastDesc = !!(cbBuffer & 0x80000000);
    … …  
    51705239            if (RT_LIKELY(!fRedo))
    51715240            {
    5172                 dmalen = RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur);
     5241                uint32_t cbXfer = RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur);
    51735242                Log2(("%s: DMA desc %#010x: addr=%#010x size=%#010x orig_size=%#010x\n", __FUNCTION__,
    5174                        (int)pDesc, pBuffer, cbBuffer, RT_LE2H_U32(DMADesc.cbBuffer) & 0xfffe));
     5243                       (int)GCPhysDesc, GCPhysBuffer, cbBuffer, RT_LE2H_U32(DMADesc.cbBuffer) & 0xfffe));
    51755244
    51765245                if (uTxDir == PDMMEDIATXDIR_FROM_DEVICE)
    5177                     PDMDevHlpPCIPhysWrite(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
     5246                    PDMDevHlpPCIPhysWrite(pDevIns, GCPhysBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, cbXfer);
    51785247                else
    5179                     PDMDevHlpPCIPhysRead(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
    5180 
    5181                 iIOBufferCur += dmalen;
    5182                 cbTotalTransfer -= dmalen;
    5183                 cbBuffer -= dmalen;
    5184                 pBuffer += dmalen;
     5248                    PDMDevHlpPCIPhysRead(pDevIns, GCPhysBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, cbXfer);
     5249
     5250                iIOBufferCur    += cbXfer;
     5251                cbTotalTransfer -= cbXfer;
     5252                cbBuffer        -= cbXfer;
     5253                GCPhysBuffer    += cbXfer;
    51855254            }
    51865255            if (    iIOBufferCur == iIOBufferEnd
    … …  
    52105279                    if (RT_UNLIKELY(fRedo))
    52115280                    {
    5212                         pCtl->pFirstDMADesc = pDesc;
    5213                         pCtl->pRedoDMABuffer = pBuffer;
     5281                        pCtl->GCPhysFirstDMADesc = GCPhysDesc;
     5282                        pCtl->GCPhysRedoDMABuffer = GCPhysBuffer;
    52145283                        pCtl->cbRedoDMABuffer = cbBuffer;
    52155284                        pCtl->fRedoDMALastDesc = fLastDesc;
    … …  
    52305299                {
    52315300                    /* This forces the loop to exit immediately. */
    5232                     pDesc = pCtl->pLastDMADesc + 1;
     5301                    GCPhysDesc = pCtl->GCPhysLastDMADesc + 1;
    52335302                }
    52345303
    … …  
    52585327                ataR3DMATransferStop(s);
    52595328            /* This forces the loop to exit immediately. */
    5260             pDesc = pCtl->pLastDMADesc + 1;
     5329            GCPhysDesc = pCtl->GCPhysLastDMADesc + 1;
    52615330        }
    52625331
    … …  
    55605629                    /* The specs say that the descriptor table must not cross a
    55615630                     * 4K boundary. */
    5562                     pCtl->pFirstDMADesc = bm->pvAddr;
    5563                     pCtl->pLastDMADesc = RT_ALIGN_32(bm->pvAddr + 1, _4K) - sizeof(BMDMADesc);
     5631                    pCtl->GCPhysFirstDMADesc = bm->GCPhysAddr;
     5632                    pCtl->GCPhysLastDMADesc = RT_ALIGN_32(bm->GCPhysAddr + 1, _4K) - sizeof(BMDMADesc);
    55645633                }
    55655634                ataR3DMATransfer(pCtl);
    … …  
    58775946static uint32_t ataBMDMAAddrReadL(PATACONTROLLER pCtl, uint32_t addr)
    58785947{
    5879     uint32_t val = (uint32_t)pCtl->BmDma.pvAddr;
     5948    uint32_t val = (uint32_t)pCtl->BmDma.GCPhysAddr;
    58805949    RT_NOREF1(addr);
    58815950    Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
    … …  
    58875956    RT_NOREF1(addr);
    58885957    Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
    5889     pCtl->BmDma.pvAddr = val & ~3;
     5958    pCtl->BmDma.GCPhysAddr = val & ~3;
    58905959}
    58915960
    … …  
    58945963    RT_NOREF1(addr);
    58955964    Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
    5896     pCtl->BmDma.pvAddr = (pCtl->BmDma.pvAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
     5965    pCtl->BmDma.GCPhysAddr = (pCtl->BmDma.GCPhysAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
    58975966
    58985967}
    … …  
    59025971    Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
    59035972    RT_NOREF1(addr);
    5904     pCtl->BmDma.pvAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.pvAddr);
     5973    pCtl->BmDma.GCPhysAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.GCPhysAddr);
    59055974}
    59065975
    … …  
    59856054                                              RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
    59866055{
    5987     RT_NOREF(iRegion, cb, enmType);
    5988     PCIATAState *pThis = PCIDEV_2_PCIATASTATE(pPciDev);
     6056    RT_NOREF(iRegion, cb, enmType, pPciDev);
     6057    PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
    59896058    int         rc = VINF_SUCCESS;
    59906059    Assert(enmType == PCI_ADDRESS_SPACE_IO);
    … …  
    60326101static DECLCALLBACK(void *) ataR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
    60336102{
    6034     PCIATAState *pThis = PDMIBASE_2_PCIATASTATE(pInterface);
     6103    PCIATAState *pThis = RT_FROM_MEMBER(pInterface, PCIATAState, IBase);
    60356104    PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
    60366105    PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
    … …  
    60516120static DECLCALLBACK(int) ataR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
    60526121{
    6053     PCIATAState *pThis = PDMILEDPORTS_2_PCIATASTATE(pInterface);
     6122    PCIATAState *pThis = RT_FROM_MEMBER(pInterface, PCIATAState, ILeds);
    60546123    if (iLUN < 4)
    60556124    {
    … …  
    60756144static DECLCALLBACK(void *) ataR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
    60766145{
    6077     ATADevState *pIf = PDMIBASE_2_ATASTATE(pInterface);
     6146    ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IBase);
    60786147    PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIf->IBase);
    60796148    PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pIf->IPort);
    … …  
    60916160                                                  uint32_t *piInstance, uint32_t *piLUN)
    60926161{
    6093     ATADevState *pIf = PDMIMEDIAPORT_2_ATASTATE(pInterface);
     6162    ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IPort);
    60946163    PPDMDEVINS pDevIns = pIf->CTX_SUFF(pDevIns);
    60956164
    … …  
    66046673        SSMR3PutBool(pSSM, pThis->aCts[i].fRedoDMALastDesc);
    66056674        SSMR3PutMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
    6606         SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pFirstDMADesc);
    6607         SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pLastDMADesc);
    6608         SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pRedoDMABuffer);
     6675        SSMR3PutGCPhys32(pSSM, pThis->aCts[i].GCPhysFirstDMADesc);
     6676        SSMR3PutGCPhys32(pSSM, pThis->aCts[i].GCPhysLastDMADesc);
     6677        SSMR3PutGCPhys32(pSSM, pThis->aCts[i].GCPhysRedoDMABuffer);
    66096678        SSMR3PutU32(pSSM, pThis->aCts[i].cbRedoDMABuffer);
    66106679
    … …  
    67776846        SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedoDMALastDesc);
    67786847        SSMR3GetMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
    6779         SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pFirstDMADesc);
    6780         SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pLastDMADesc);
    6781         SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pRedoDMABuffer);
     6848        SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].GCPhysFirstDMADesc);
     6849        SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].GCPhysLastDMADesc);
     6850        SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].GCPhysRedoDMABuffer);
    67826851        SSMR3GetU32(pSSM, &pThis->aCts[i].cbRedoDMABuffer);
    67836852
    … …  
    69857054        pThis->aCts[i].BmDma.u8Status =   (pThis->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)
    69867055                                        | (pThis->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);
    6987         pThis->aCts[i].BmDma.pvAddr = 0;
     7056        pThis->aCts[i].BmDma.GCPhysAddr = 0;
    69887057
    69897058        pThis->aCts[i].fReset = true;

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r65922 r65960  
    799799    GEN_CHECK_OFF(BMDMAState, u8Cmd);
    800800    GEN_CHECK_OFF(BMDMAState, u8Status);
    801     GEN_CHECK_OFF(BMDMAState, pvAddr);
     801    GEN_CHECK_OFF(BMDMAState, GCPhysAddr);
    802802    GEN_CHECK_SIZE(BMDMADesc);
    803     GEN_CHECK_OFF(BMDMADesc, pBuffer);
     803    GEN_CHECK_OFF(BMDMADesc, GCPhysBuffer);
    804804    GEN_CHECK_OFF(BMDMADesc, cbBuffer);
    805805    GEN_CHECK_SIZE(ATADevState);
    … …  
    921921    GEN_CHECK_OFF(ATACONTROLLER, fRedoDMALastDesc);
    922922    GEN_CHECK_OFF(ATACONTROLLER, BmDma);
    923     GEN_CHECK_OFF(ATACONTROLLER, pFirstDMADesc);
    924     GEN_CHECK_OFF(ATACONTROLLER, pLastDMADesc);
    925     GEN_CHECK_OFF(ATACONTROLLER, pRedoDMABuffer);
     923    GEN_CHECK_OFF(ATACONTROLLER, GCPhysFirstDMADesc);
     924    GEN_CHECK_OFF(ATACONTROLLER, GCPhysLastDMADesc);
     925    GEN_CHECK_OFF(ATACONTROLLER, GCPhysRedoDMABuffer);
    926926    GEN_CHECK_OFF(ATACONTROLLER, cbRedoDMABuffer);
    927927    GEN_CHECK_OFF(ATACONTROLLER, aIfs);
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