Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (revision 65950) +++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (revision 65951) @@ -33,4 +33,6 @@ """ __version__ = "$Revision$" + +# pylint: disable=anomalous-backslash-in-string # Standard python imports. @@ -278,19 +280,20 @@ 'interrupt': 'DISOPTYPE_INTERRUPT', ##< 'illegal': 'DISOPTYPE_ILLEGAL', ##< - 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. */ - 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. */ + 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. + 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. 'inhibit_irqs': 'DISOPTYPE_INHIBIT_IRQS', ##< Will or can inhibit irqs (sti, pop ss, mov ss) */ 'portio_read': 'DISOPTYPE_PORTIO_READ', ##< 'portio_write': 'DISOPTYPE_PORTIO_WRITE', ##< - 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode */ - 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode */ - 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size */ - 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes */ - 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte */ - 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b */ - 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */ - 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */ - 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */ - 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! */ + 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode + 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode + 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size + 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes + 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte + 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b + 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes + ## (only in 16 & 32 bits mode!) + 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! + 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! + 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! 'ignores_op_size': '', ##< Ignores both operand size prefixes. }; @@ -567,4 +570,5 @@ Checks if sValue is a pair. """ + _ = sValue; return False; @@ -595,7 +599,7 @@ if fClear != 0: aoClear = TestType.get(self, '%#x' % (~fClear)) - assert self.isAndOrPair(sValue) == True; + assert self.isAndOrPair(sValue) is True; return (aoClear[0], aoSet[0]); - assert self.isAndOrPair(sValue) == False; + assert self.isAndOrPair(sValue) is False; return aoSet; @@ -842,5 +846,5 @@ -class Instruction(object): +class Instruction(object): # pylint: disable=too-many-instance-attributes """ Instruction. @@ -856,5 +860,5 @@ self.aoOperands = []; # type: list(Operand) self.sPrefix = None; ##< Single prefix: None, 0x66, 0xf3, 0xf2 - self.sOpcode = None; + self.sOpcode = None; # type: str self.sEncoding = None; self.asFlTest = None; @@ -959,15 +963,15 @@ if self.sOpcode is None: raise Exception('No opcode byte for %s!' % (self,)); + sOpcode = str(self.sOpcode); # pylint type confusion workaround. # Full hex byte form. - if self.sOpcode[:2] == '0x': - return int(self.sOpcode, 16); + if sOpcode[:2] == '0x': + return int(sOpcode, 16); # The /r form: - if self.sOpcode[0] == '/' and self.sOpcode[1].isdigit() and len(self.sOpcode) == 2: - return int(self.sOpcode[1:]) << 3; - - raise Exception('unsupported opcode byte spec "%s" for %s' % (self.sOpcode, self,)); - return -1; + if sOpcode[0] == '/' and sOpcode[1].isdigit() and len(sOpcode) == 2: + return int(sOpcode[1:]) << 3; + + raise Exception('unsupported opcode byte spec "%s" for %s' % (sOpcode, self,)); @@ -1014,5 +1018,4 @@ 'grpP': InstructionMap('grpP', asLeadOpcodes = ['0x0f', '0x0d',], sSelector = '/r'), # AMD: prefetch - 'three0f38': InstructionMap('three0f38', asLeadOpcodes = ['0x0f', '0x38',]), 'three0f38': InstructionMap('three0f38', asLeadOpcodes = ['0x0f', '0x38',]), 'three0f3a': InstructionMap('three0f3a', asLeadOpcodes = ['0x0f', '0x3a',]), @@ -1152,4 +1155,5 @@ def debug(self, sMessage): """ + For debugging. """ if self.fDebug: @@ -1335,5 +1339,5 @@ """ asRet = []; - for asLines in assSections: + for asLines in aasSections: if len(asLines) > 0: asRet.append(' '.join([sLine.strip() for sLine in asLines])); @@ -1401,5 +1405,5 @@ """ oInstr = self.ensureInstructionForOpTag(iTagLine); - if len(self.aoInstructions) > 0 and len(aasSections) > 0: + if len(aasSections) > 0: oInstr.asDescSections.extend(self.flattenSections(aasSections)); return True; @@ -1467,5 +1471,5 @@ elif sWhere not in g_kdOpLocations: return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s' - % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),), iTagLine); + % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),)); # Insert the operand, refusing to overwrite an existing one. @@ -1642,5 +1646,4 @@ 'sf': 'X86_EFL_SF', 'zf': 'X86_EFL_ZF', - 'cf': 'X86_EFL_CF', 'pf': 'X86_EFL_PF', 'if': 'X86_EFL_IF', @@ -1770,5 +1773,5 @@ sMinCpu = asCpus[0]; if sMinCpu in g_kdCpuNames: - self.sMinCpu = sMinCpu; + oInstr.sMinCpu = sMinCpu; else: return self.errorComment(iTagLine, '%s: invalid CPU name: %s (names: %s)' @@ -1882,5 +1885,5 @@ return True; - def parseTagOpTest(self, sTag, aasSections, iTagLine, iEndLine): + def parseTagOpTest(self, sTag, aasSections, iTagLine, iEndLine): # pylint: disable=too-many-locals """ Tag: \@optest @@ -2019,4 +2022,5 @@ % (sTag, asSelectors, asInputs, asOutputs,)); + _ = iEndLine; return True; @@ -2039,9 +2043,9 @@ if not self.oReFunctionName.match(sFunction): return self.errorComment(iTagLine, '%s: invalid VMM function name: "%s" (valid: %s)' - % (sTag, Name, self.oReFunctionName.pattern)); + % (sTag, sFunction, self.oReFunctionName.pattern)); if oInstr.sFunction is not None: return self.errorComment(iTagLine, '%s: attempting to overwrite VMM function name "%s" with "%s"' - % (sTag, oInstr.sStats, sStats,)); + % (sTag, oInstr.sFunction, sFunction,)); oInstr.sFunction = sFunction; @@ -2067,5 +2071,5 @@ if not self.oReStatsName.match(sStats): return self.errorComment(iTagLine, '%s: invalid VMM statistics name: "%s" (valid: %s)' - % (sTag, Name, self.oReStatsName.pattern)); + % (sTag, sStats, self.oReStatsName.pattern)); if oInstr.sStats is not None: @@ -2201,5 +2205,5 @@ offOpen = sInvocation.find('('); if offOpen <= 0: - raiseError("macro invocation open parenthesis not found"); + self.raiseError("macro invocation open parenthesis not found"); sName = sInvocation[:offOpen].strip(); if not self.oReMacroName.match(sName): @@ -2258,5 +2262,6 @@ return None; - def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands): + def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, # pylint: disable=too-many-arguments + sDisHints, sIemHints, asOperands): """ Processes one of the a IEMOP_MNEMONIC0EX, IEMOP_MNEMONIC1EX, IEMOP_MNEMONIC2EX, @@ -2289,5 +2294,5 @@ else: self.error('%s: already saw a IEMOP_MNEMONIC* macro on line %u for this instruction' - % (sMacro, self.iLineMnemonicMacro,)); + % (sMacro, oInstr.iLineMnemonicMacro,)); # Mnemonic @@ -2300,5 +2305,5 @@ if len(oInstr.aoOperands) not in [0, len(asOperands)]: self.error('%s: number of operands given by @opN does not match macro: %s vs %s' - % (sMacro, len(oInstr.aoOperands), len(aoOperands),)); + % (sMacro, len(oInstr.aoOperands), len(asOperands),)); for iOperand, sType in enumerate(asOperands): sWhere = g_kdOpTypes.get(sType, [None, None])[1]; @@ -2368,4 +2373,5 @@ + _ = sAsm; return True; @@ -2376,5 +2382,5 @@ """ if asOperands == 0: - return self.workerIemOpMnemonicEx(sLower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); + return self.workerIemOpMnemonicEx(sMacro, sLower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); return self.workerIemOpMnemonicEx(sMacro, sLower + '_' + '_'.join(asOperands), sLower + ' ' + ','.join(asOperands), sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); @@ -2431,15 +2437,16 @@ self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[7], asArgs[8], [asArgs[6],]); - # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2EX'); if asArgs is not None: self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[8], asArgs[9], [asArgs[6], asArgs[7]]); - # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3EX'); if asArgs is not None: self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[9], asArgs[10], [asArgs[6], asArgs[7], asArgs[8],]); - # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, + # a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4EX'); if asArgs is not None: @@ -2455,15 +2462,15 @@ if asArgs is not None: self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[5], asArgs[6], [asArgs[4],]); - # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2'); if asArgs is not None: self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[6], asArgs[7], [asArgs[4], asArgs[5],]); - # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3'); if asArgs is not None: self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[7], asArgs[8], [asArgs[4], asArgs[5], asArgs[6],]); - # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \ + # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4'); if asArgs is not None: @@ -2603,5 +2610,7 @@ """ - for sName, oMap in sorted(iter(g_dInstructionMaps.items()), key = lambda k_v: k_v[1].sEncoding + ''.join(k_v[1].asLeadOpcodes)): + for sName, oMap in sorted(iter(g_dInstructionMaps.items()), + key = lambda aKV: aKV[1].sEncoding + ''.join(aKV[1].asLeadOpcodes)): + assert oMap.sName == sName; asLines = []; @@ -2743,5 +2752,6 @@ sLine += s; - # OP("psrlw %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PSRLW, OP_PARM_Vdq, OP_PARM_Wdq, OP_PARM_NONE, DISOPTYPE_HARMLESS), + # OP("psrlw %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PSRLW, OP_PARM_Vdq, OP_PARM_Wdq, OP_PARM_NONE, + # DISOPTYPE_HARMLESS), # define OP(pszOpcode, idxParse1, idxParse2, idxParse3, opcode, param1, param2, param3, optype) \ # { pszOpcode, idxParse1, idxParse2, idxParse3, 0, opcode, param1, param2, param3, 0, 0, optype }