- Timestamp:
- Jan 13, 2017 6:03:48 PM (8 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r65286 r65292 1538 1538 cRegions = 2; 1539 1539 1540 bool fSuppressMem = false; 1540 1541 bool fActiveMemRegion = false; 1541 1542 bool fActiveIORegion = false; … … 1548 1549 uint8_t u8ResourceType = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, u32Address, 1); 1549 1550 1551 bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH | PCI_ADDRESS_SPACE_IO))) 1552 == PCI_ADDRESS_SPACE_MEM_PREFETCH; 1550 1553 bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO))) 1551 1554 == PCI_ADDRESS_SPACE_BAR64; 1552 1555 bool fIsPio = ((u8ResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO); 1553 1556 uint64_t cbRegSize64 = 0; 1557 1558 /* Hack: since this PCI init code cannot handle prefetchable BARs on 1559 * anything besides the primary bus, it's for now the best solution 1560 * to leave such BARs uninitialized and keep memory transactions 1561 * disabled. The OS will hopefully be clever enough to fix this. 1562 * Prefetchable BARs are the only ones which can be truly big (and 1563 * are almost always 64-bit BARs). The non-prefetchable ones will not 1564 * cause running out of space in the PCI memory hole. */ 1565 if (fPrefetch && uBus != 0) 1566 { 1567 fSuppressMem = true; 1568 if (f64Bit) 1569 iRegion++; /* skip next region */ 1570 continue; 1571 } 1554 1572 1555 1573 if (f64Bit) … … 1648 1666 /* Update the command word appropriately. */ 1649 1667 uint8_t uCmd = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_COMMAND, 2); 1650 if (fActiveMemRegion )1668 if (fActiveMemRegion && !fSuppressMem) 1651 1669 uCmd |= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */ 1652 1670 if (fActiveIORegion) … … 1856 1874 pPciRoot->uPciBiosMmio64 = cbAbove4GB + _4G; 1857 1875 1858 /* NB: Assume that if PCI controller MMIO range is enabled, it is at the bottomof the memory hole. */1876 /* NB: Assume that if PCI controller MMIO range is enabled, it is below the beginning of the memory hole. */ 1859 1877 if (pPciRoot->u64PciConfigMMioAddress) 1860 1878 { … … 2402 2420 } 2403 2421 2422 for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++) 2423 { 2424 PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion]; 2425 uint64_t const cbRegion = pRegion->size; 2426 2427 if (cbRegion == 0) 2428 continue; 2429 2430 uint32_t uAddr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion)); 2431 const char * pszDesc; 2432 char szDescBuf[128]; 2433 2434 bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO))) 2435 == PCI_ADDRESS_SPACE_BAR64; 2436 if (pRegion->type & PCI_ADDRESS_SPACE_IO) 2437 { 2438 pszDesc = "IO"; 2439 uAddr &= ~0x3; 2440 } 2441 else 2442 { 2443 RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s", 2444 f64Bit ? "64" : "32", 2445 pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : ""); 2446 pszDesc = szDescBuf; 2447 uAddr &= ~0xf; 2448 } 2449 2450 devpciR3InfoIndent(pHlp, iIndentLvl + 2); 2451 pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion); 2452 if (f64Bit) 2453 { 2454 uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1)); 2455 uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High); 2456 pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion - 1); 2457 iRegion++; 2458 } 2459 else 2460 pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion - 1); 2461 } 2462 2463 devpciR3InfoIndent(pHlp, iIndentLvl + 2); 2404 2464 uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND); 2405 if ((iCmd & (VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY)) != 0)2406 {2407 for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)2408 {2409 PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion];2410 uint64_t const cbRegion = pRegion->size;2411 2412 if (cbRegion == 0)2413 continue;2414 2415 uint32_t uAddr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));2416 const char * pszDesc;2417 char szDescBuf[128];2418 2419 bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))2420 == PCI_ADDRESS_SPACE_BAR64;2421 if (pRegion->type & PCI_ADDRESS_SPACE_IO)2422 {2423 pszDesc = "IO";2424 uAddr &= ~0x3;2425 }2426 else2427 {2428 RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",2429 f64Bit ? "64" : "32",2430 pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : "");2431 pszDesc = szDescBuf;2432 uAddr &= ~0xf;2433 }2434 2435 devpciR3InfoIndent(pHlp, iIndentLvl + 2);2436 pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion);2437 if (f64Bit)2438 {2439 uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));2440 uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High);2441 pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion - 1);2442 iRegion++;2443 }2444 else2445 pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion - 1);2446 }2447 }2448 2449 devpciR3InfoIndent(pHlp, iIndentLvl + 2);2450 2465 uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS); 2451 2466 pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04x\n", iCmd, iStatus);
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