Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (revision 65264) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (revision 65265) @@ -146,7 +146,65 @@ STAMPROFILE StatBusyDelayEmts; - STAMPROFILE StatR3CmdPresent; - STAMPROFILE StatR3CmdDrawPrimitive; - STAMPROFILE StatR3CmdSurfaceDMA; + STAMPROFILE StatR3Cmd3dPresentProf; + STAMPROFILE StatR3Cmd3dDrawPrimitivesProf; + STAMPROFILE StatR3Cmd3dSurfaceDmaProf; + STAMCOUNTER StatR3CmdDefineGmr2; + STAMCOUNTER StatR3CmdDefineGmr2Free; + STAMCOUNTER StatR3CmdDefineGmr2Modify; + STAMCOUNTER StatR3CmdRemapGmr2; + STAMCOUNTER StatR3CmdRemapGmr2Modify; + STAMCOUNTER StatR3CmdInvalidCmd; + STAMCOUNTER StatR3CmdFence; + STAMCOUNTER StatR3CmdUpdate; + STAMCOUNTER StatR3CmdUpdateVerbose; + STAMCOUNTER StatR3CmdDefineCursor; + STAMCOUNTER StatR3CmdDefineAlphaCursor; + STAMCOUNTER StatR3CmdEscape; + STAMCOUNTER StatR3CmdDefineScreen; + STAMCOUNTER StatR3CmdDestroyScreen; + STAMCOUNTER StatR3CmdDefineGmrFb; + STAMCOUNTER StatR3CmdBlitGmrFbToScreen; + STAMCOUNTER StatR3CmdBlitScreentoGmrFb; + STAMCOUNTER StatR3CmdAnnotationFill; + STAMCOUNTER StatR3CmdAnnotationCopy; + STAMCOUNTER StatR3Cmd3dSurfaceDefine; + STAMCOUNTER StatR3Cmd3dSurfaceDefineV2; + STAMCOUNTER StatR3Cmd3dSurfaceDestroy; + STAMCOUNTER StatR3Cmd3dSurfaceCopy; + STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt; + STAMCOUNTER StatR3Cmd3dSurfaceDma; + STAMCOUNTER StatR3Cmd3dSurfaceScreen; + STAMCOUNTER StatR3Cmd3dContextDefine; + STAMCOUNTER StatR3Cmd3dContextDestroy; + STAMCOUNTER StatR3Cmd3dSetTransform; + STAMCOUNTER StatR3Cmd3dSetZRange; + STAMCOUNTER StatR3Cmd3dSetRenderState; + STAMCOUNTER StatR3Cmd3dSetRenderTarget; + STAMCOUNTER StatR3Cmd3dSetTextureState; + STAMCOUNTER StatR3Cmd3dSetMaterial; + STAMCOUNTER StatR3Cmd3dSetLightData; + STAMCOUNTER StatR3Cmd3dSetLightEnable; + STAMCOUNTER StatR3Cmd3dSetViewPort; + STAMCOUNTER StatR3Cmd3dSetClipPlane; + STAMCOUNTER StatR3Cmd3dClear; + STAMCOUNTER StatR3Cmd3dPresent; + STAMCOUNTER StatR3Cmd3dPresentReadBack; + STAMCOUNTER StatR3Cmd3dShaderDefine; + STAMCOUNTER StatR3Cmd3dShaderDestroy; + STAMCOUNTER StatR3Cmd3dSetShader; + STAMCOUNTER StatR3Cmd3dSetShaderConst; + STAMCOUNTER StatR3Cmd3dDrawPrimitives; + STAMCOUNTER StatR3Cmd3dSetScissorRect; + STAMCOUNTER StatR3Cmd3dBeginQuery; + STAMCOUNTER StatR3Cmd3dEndQuery; + STAMCOUNTER StatR3Cmd3dWaitForQuery; + STAMCOUNTER StatR3Cmd3dGenerateMipmaps; + STAMCOUNTER StatR3Cmd3dActivateSurface; + STAMCOUNTER StatR3Cmd3dDeactivateSurface; + + STAMCOUNTER StatR3RegConfigDoneWr; + STAMCOUNTER StatR3RegGmrDescriptorWr; + STAMCOUNTER StatR3RegGmrDescriptorWrErrors; + STAMCOUNTER StatR3RegGmrDescriptorWrFree; STAMCOUNTER StatFifoCommands; @@ -223,7 +281,66 @@ #endif SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts), - SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent), - SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive), - SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface), + + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree), + SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands), SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors), @@ -293,8 +410,9 @@ * @returns Index register string or "UNKNOWN" * @param pThis VMSVGA State + * @param idxReg The index register. */ -static const char *vmsvgaIndexToString(PVGASTATE pThis) +static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg) { - switch (pThis->svga.u32IndexReg) + switch (idxReg) { case SVGA_REG_ID: @@ -400,7 +518,7 @@ default: - if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion) + if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion) return "SVGA_SCRATCH_BASE reg"; - if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS) + if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS) return "SVGA_PALETTE_BASE reg"; return "UNKNOWN"; @@ -591,13 +709,24 @@ { int rc = VINF_SUCCESS; - *pu32 = 0; - switch (pThis->svga.u32IndexReg) + + /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */ + uint32_t idxReg = pThis->svga.u32IndexReg; + if ( idxReg >= SVGA_REG_CAPABILITIES + && pThis->svga.u32SVGAId == SVGA_ID_0) + { + idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES; + Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg)); + } + + switch (idxReg) { case SVGA_REG_ID: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd); *pu32 = pThis->svga.u32SVGAId; break; case SVGA_REG_ENABLE: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd); *pu32 = pThis->svga.fEnabled; break; @@ -605,4 +734,5 @@ case SVGA_REG_WIDTH: { + STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd); if ( pThis->svga.fEnabled && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED) @@ -623,4 +753,5 @@ case SVGA_REG_HEIGHT: { + STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd); if ( pThis->svga.fEnabled && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED) @@ -640,8 +771,10 @@ case SVGA_REG_MAX_WIDTH: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd); *pu32 = pThis->svga.u32MaxWidth; break; case SVGA_REG_MAX_HEIGHT: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd); *pu32 = pThis->svga.u32MaxHeight; break; @@ -649,4 +782,5 @@ case SVGA_REG_DEPTH: /* This returns the color depth of the current mode. */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd); switch (pThis->svga.uBpp) { @@ -665,4 +799,5 @@ case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd); if ( pThis->svga.fEnabled && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED) @@ -681,4 +816,5 @@ case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd); if ( pThis->svga.fEnabled && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED) @@ -697,4 +833,5 @@ case SVGA_REG_PSEUDOCOLOR: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd); *pu32 = 0; break; @@ -749,15 +886,18 @@ break; } - switch (pThis->svga.u32IndexReg) + switch (idxReg) { case SVGA_REG_RED_MASK: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd); *pu32 = u32RedMask; break; case SVGA_REG_GREEN_MASK: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd); *pu32 = u32GreenMask; break; case SVGA_REG_BLUE_MASK: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd); *pu32 = u32BlueMask; break; @@ -768,4 +908,5 @@ case SVGA_REG_BYTES_PER_LINE: { + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd); if ( pThis->svga.fEnabled && pThis->svga.cbScanline) @@ -785,8 +926,10 @@ case SVGA_REG_VRAM_SIZE: /* VRAM size */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd); *pu32 = pThis->vram_size; break; case SVGA_REG_FB_START: /* Frame buffer physical address. */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd); Assert(pThis->GCPhysVRAM <= 0xffffffff); *pu32 = pThis->GCPhysVRAM; @@ -794,4 +937,5 @@ case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd); /* Always zero in our case. */ *pu32 = 0; @@ -803,4 +947,6 @@ rc = VINF_IOM_R3_IOPORT_READ; #else + STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd); + /* VMWare testcases want at least 4 MB in case the hardware is disabled. */ if ( pThis->svga.fEnabled @@ -820,8 +966,10 @@ case SVGA_REG_CAPABILITIES: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd); *pu32 = pThis->svga.u32RegCaps; break; case SVGA_REG_MEM_START: /* FIFO start */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd); Assert(pThis->svga.GCPhysFIFO <= 0xffffffff); *pu32 = pThis->svga.GCPhysFIFO; @@ -829,16 +977,20 @@ case SVGA_REG_MEM_SIZE: /* FIFO size */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd); *pu32 = pThis->svga.cbFIFO; break; case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd); *pu32 = pThis->svga.fConfigured; break; case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd); *pu32 = 0; break; case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd); if (pThis->svga.fBusy) { @@ -899,20 +1051,25 @@ case SVGA_REG_GUEST_ID: /* Set guest OS identifier */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd); *pu32 = pThis->svga.u32GuestId; break; case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd); *pu32 = pThis->svga.cScratchRegion; break; case SVGA_REG_MEM_REGS: /* Number of FIFO registers */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd); *pu32 = SVGA_FIFO_NUM_REGS; break; case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd); *pu32 = pThis->svga.u32PitchLock; break; case SVGA_REG_IRQMASK: /* Interrupt mask */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd); *pu32 = pThis->svga.u32IrqMask; break; @@ -920,8 +1077,10 @@ /* See "Guest memory regions" below. */ case SVGA_REG_GMR_ID: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd); *pu32 = pThis->svga.u32CurrentGMRId; break; case SVGA_REG_GMR_DESCRIPTOR: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd); /* Write only */ *pu32 = 0; @@ -929,29 +1088,31 @@ case SVGA_REG_GMR_MAX_IDS: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd); *pu32 = VMSVGA_MAX_GMR_IDS; break; case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd); *pu32 = VMSVGA_MAX_GMR_PAGES; break; case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd); *pu32 = pThis->svga.fTraces; break; case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd); *pu32 = VMSVGA_MAX_GMR_PAGES; break; case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd); *pu32 = VMSVGA_SURFACE_SIZE; break; case SVGA_REG_TOP: /* Must be 1 more than the last register */ - break; - - case SVGA_PALETTE_BASE: /* Base of SVGA color map */ - break; - /* Next 768 (== 256*3) registers exist for colormap */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd); + break; /* Mouse cursor support. */ @@ -960,39 +1121,74 @@ case SVGA_REG_CURSOR_Y: case SVGA_REG_CURSOR_ON: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd); break; /* Legacy multi-monitor support */ case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd); *pu32 = 1; break; case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd); + *pu32 = 0; + break; + case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd); + *pu32 = 0; + break; + case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd); + *pu32 = 0; + break; + case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd); *pu32 = 0; break; case SVGA_REG_DISPLAY_WIDTH: /* The display's width */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd); *pu32 = pThis->svga.uWidth; break; case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd); *pu32 = pThis->svga.uHeight; break; case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd); *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */ break; default: - if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE - && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion) - { - *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE]; - } - break; - } - Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc)); + { + uint32_t offReg; + if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion) + { + *pu32 = pThis->svga.au32ScratchRegion[offReg]; + STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd); + } + else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS) + { + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd); + /* Next 768 (== 256*3) registers exist for colormap */ + } + else + { +#if !defined(IN_RING3) && defined(VBOX_STRICT) + rc = VINF_IOM_R3_IOPORT_READ; +#else + STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd); + AssertMsgFailed(("reg=%#x\n", idxReg)); +#endif + } + break; + } + } + Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc)); return rc; } @@ -1109,15 +1305,27 @@ int rc = VINF_SUCCESS; - Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32)); - switch (pThis->svga.u32IndexReg) + /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */ + uint32_t idxReg = pThis->svga.u32IndexReg; + if ( idxReg >= SVGA_REG_CAPABILITIES + && pThis->svga.u32SVGAId == SVGA_ID_0) + { + idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES; + Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg)); + } + Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32)); + switch (idxReg) { case SVGA_REG_ID: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr); if ( u32 == SVGA_ID_0 || u32 == SVGA_ID_1 || u32 == SVGA_ID_2) pThis->svga.u32SVGAId = u32; + else + AssertMsgFailed(("%#x\n", u32)); break; case SVGA_REG_ENABLE: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr); if ( pThis->svga.fEnabled == u32 && pThis->last_bpp == (unsigned)pThis->svga.uBpp @@ -1187,4 +1395,5 @@ case SVGA_REG_WIDTH: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr); if (pThis->svga.uWidth != u32) { @@ -1206,4 +1415,5 @@ case SVGA_REG_HEIGHT: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr); if (pThis->svga.uHeight != u32) { @@ -1225,8 +1435,10 @@ case SVGA_REG_DEPTH: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr); /** @todo read-only?? */ break; case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr); if (pThis->svga.uBpp != u32) { @@ -1248,8 +1460,10 @@ case SVGA_REG_PSEUDOCOLOR: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr); break; case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */ #ifdef IN_RING3 + STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr); pThis->svga.fConfigured = u32; /* Disabling the FIFO enables tracing (dirty page detection) by default. */ @@ -1265,4 +1479,5 @@ case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr); if ( pThis->svga.fEnabled && pThis->svga.fConfigured) @@ -1287,15 +1502,19 @@ case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr); break; case SVGA_REG_GUEST_ID: /* Set guest OS identifier */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr); pThis->svga.u32GuestId = u32; break; case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr); pThis->svga.u32PitchLock = u32; break; case SVGA_REG_IRQMASK: /* Interrupt mask */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr); pThis->svga.u32IrqMask = u32; @@ -1315,24 +1534,33 @@ case SVGA_REG_CURSOR_Y: case SVGA_REG_CURSOR_ON: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr); break; /* Legacy multi-monitor support */ case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr); break; case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr); break; case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr); break; case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr); break; case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr); break; case SVGA_REG_DISPLAY_WIDTH: /* The display's width */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr); break; case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr); break; #ifdef VBOX_WITH_VMSVGA3D /* See "Guest memory regions" below. */ case SVGA_REG_GMR_ID: + STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr); pThis->svga.u32CurrentGMRId = u32; break; @@ -1344,4 +1572,6 @@ # else /* IN_RING3 */ { + STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr); + SVGAGuestMemDescriptor desc; RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT; @@ -1414,4 +1644,5 @@ case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr); if (pThis->svga.fTraces == u32) break; /* nothing to do */ @@ -1425,12 +1656,10 @@ case SVGA_REG_TOP: /* Must be 1 more than the last register */ - break; - - case SVGA_PALETTE_BASE: /* Base of SVGA color map */ - break; - /* Next 768 (== 256*3) registers exist for colormap */ + STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr); + break; case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */ - Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32)); + STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr); + Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32)); break; @@ -1456,14 +1685,32 @@ case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH: /* Read only - ignore. */ - Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32)); + Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32)); + STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr); break; default: - if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE - && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion) - { - pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32; - } - break; + { + uint32_t offReg; + if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion) + { + pThis->svga.au32ScratchRegion[offReg] = u32; + STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr); + } + else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS) + { + STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr); + /* Next 768 (== 256*3) registers exist for colormap */ + } + else + { +#if !defined(IN_RING3) && defined(VBOX_STRICT) + rc = VINF_IOM_R3_IOPORT_WRITE; +#else + STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr); + AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32)); +#endif + } + break; + } } return rc; @@ -2657,4 +2904,5 @@ case SVGA_CMD_INVALID_CMD: /* Nothing to do. */ + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd); break; @@ -2663,4 +2911,5 @@ SVGAFifoCmdFence *pCmdFence; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence); if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin)) { @@ -2691,4 +2940,8 @@ SVGAFifoCmdUpdate *pUpdate; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate)); + if (enmCmdId == SVGA_CMD_UPDATE) + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate); + else + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose); Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height)); vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height); @@ -2701,4 +2954,5 @@ SVGAFifoCmdDefineCursor *pCursor; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor); AssertFailed(); /** @todo implement when necessary. */ break; @@ -2714,4 +2968,5 @@ SVGAFifoCmdDefineAlphaCursor *pCursor; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor); Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY)); @@ -2768,4 +3023,5 @@ SVGAFifoCmdEscape *pEscape; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape); /* Refetch the command buffer with the variable data; undo size increase (ugly) */ @@ -2818,4 +3074,5 @@ VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd)); Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2); /* Validate current GMR id. */ @@ -2825,4 +3082,5 @@ if (!pCmd->numPages) { + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free); vmsvgaGMRFree(pThis, pCmd->gmrId); } @@ -2830,7 +3088,10 @@ { PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId]; + if (pGMR->cMaxPages) + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify); + pGMR->cMaxPages = pCmd->numPages; + /* The rest is done by the REMAP_GMR2 command. */ } - /* everything done in remap */ break; } @@ -2841,4 +3102,6 @@ SVGAFifoCmdRemapGMR2 *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2); + uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t); uint32_t cbCmd; @@ -2979,4 +3242,5 @@ RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize)); VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen); Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y)); @@ -3003,4 +3267,5 @@ SVGAFifoCmdDestroyScreen *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen); Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId)); @@ -3012,4 +3277,5 @@ SVGAFifoCmdDefineGMRFB *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb); Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth)); @@ -3025,4 +3291,5 @@ SVGAFifoCmdBlitGMRFBToScreen *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen); Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom)); @@ -3070,4 +3337,5 @@ SVGAFifoCmdBlitScreenToGMRFB *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb); /* Note! This can fetch 3d render results as well!! */ @@ -3081,4 +3349,5 @@ SVGAFifoCmdAnnotationFill *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill); Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b)); @@ -3091,4 +3360,5 @@ SVGAFifoCmdAnnotationCopy *pCmd; VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy); Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n")); @@ -3124,4 +3394,5 @@ SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine); cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize); @@ -3139,4 +3410,5 @@ SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2); cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize); @@ -3151,4 +3423,5 @@ SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy); rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid); break; @@ -3160,4 +3433,5 @@ SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy); cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox); @@ -3170,4 +3444,5 @@ SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt); rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode); @@ -3180,9 +3455,10 @@ SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma); cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox); - STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a); + STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a); rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1)); - STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a); + STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a); break; } @@ -3193,4 +3469,5 @@ SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen); cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect); @@ -3203,4 +3480,5 @@ SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine); rc = vmsvga3dContextDefine(pThis, pCmd->cid); @@ -3212,4 +3490,5 @@ SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy); rc = vmsvga3dContextDestroy(pThis, pCmd->cid); @@ -3221,4 +3500,5 @@ SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform); rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix); @@ -3230,4 +3510,5 @@ SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange); rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange); @@ -3240,4 +3521,5 @@ SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState); cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState); @@ -3250,4 +3532,5 @@ SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget); rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target); @@ -3260,4 +3543,5 @@ SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState); cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState); @@ -3270,4 +3554,5 @@ SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial); rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material); @@ -3279,4 +3564,5 @@ SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData); rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data); @@ -3288,4 +3574,5 @@ SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable); rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled); @@ -3297,4 +3584,5 @@ SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort); rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect); @@ -3306,4 +3594,5 @@ SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane); rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane); @@ -3315,6 +3604,7 @@ SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear); + uint32_t cRects; - cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect); rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1)); @@ -3327,11 +3617,14 @@ SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - uint32_t cRects; - - cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect); - - STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a); + if (enmCmdId == SVGA_3D_CMD_PRESENT) + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent); + else + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack); + + uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect); + + STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a); rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1)); - STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a); + STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a); break; } @@ -3341,7 +3634,7 @@ SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - uint32_t cbData; - - cbData = (pHdr->size - sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine); + + uint32_t cbData = (pHdr->size - sizeof(*pCmd)); rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1)); break; @@ -3352,4 +3645,5 @@ SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy); rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type); @@ -3361,4 +3655,5 @@ SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader); rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid); @@ -3370,4 +3665,5 @@ SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst); uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1; @@ -3380,7 +3676,7 @@ SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - uint32_t cVertexDivisor; - - cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives); + + uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges); Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES); Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS); @@ -3391,7 +3687,7 @@ SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL; - STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a); + STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a); rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor); - STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a); + STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a); break; } @@ -3401,4 +3697,5 @@ SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect); rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect); @@ -3410,4 +3707,5 @@ SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery); rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type); @@ -3419,4 +3717,5 @@ SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery); rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult); @@ -3428,4 +3727,5 @@ SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery); rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult); @@ -3437,4 +3737,5 @@ SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1); VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps); rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter); @@ -3443,11 +3744,15 @@ case SVGA_3D_CMD_ACTIVATE_SURFACE: + /* context id + surface id? */ + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface); + break; case SVGA_3D_CMD_DEACTIVATE_SURFACE: /* context id + surface id? */ + STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface); break; default: STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds); - AssertFailed(); + AssertMsgFailed(("enmCmdId=%d\n", enmCmdId)); break; } @@ -3457,5 +3762,5 @@ { STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds); - AssertFailed(); + AssertMsgFailed(("enmCmdId=%d\n", enmCmdId)); } } @@ -4357,7 +4662,144 @@ * Statistics. */ - STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present."); - STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive."); - STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA."); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES"); + STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES."); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK"); + STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK."); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA"); + STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA."); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT"); + STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees."); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR."); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2."); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR."); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE"); + STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE"); + + STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes"); + STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes"); + STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands."); + STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR."); + STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes."); + STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register."); + STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes."); + + STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads."); + STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads."); + STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread."); STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter."); Index: /trunk/src/VBox/Devices/Graphics/DevVGA.h =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA.h (revision 65264) +++ /trunk/src/VBox/Devices/Graphics/DevVGA.h (revision 65265) @@ -357,4 +357,83 @@ PGMPHYSHANDLERTYPE hFifoAccessHandlerType; # endif + + STAMCOUNTER StatRegBitsPerPixelWr; + STAMCOUNTER StatRegBusyWr; + STAMCOUNTER StatRegCursorXxxxWr; + STAMCOUNTER StatRegDepthWr; + STAMCOUNTER StatRegDisplayHeightWr; + STAMCOUNTER StatRegDisplayIdWr; + STAMCOUNTER StatRegDisplayIsPrimaryWr; + STAMCOUNTER StatRegDisplayPositionXWr; + STAMCOUNTER StatRegDisplayPositionYWr; + STAMCOUNTER StatRegDisplayWidthWr; + STAMCOUNTER StatRegEnableWr; + STAMCOUNTER StatRegGmrIdWr; + STAMCOUNTER StatRegGuestIdWr; + STAMCOUNTER StatRegHeightWr; + STAMCOUNTER StatRegIdWr; + STAMCOUNTER StatRegIrqMaskWr; + STAMCOUNTER StatRegNumDisplaysWr; + STAMCOUNTER StatRegNumGuestDisplaysWr; + STAMCOUNTER StatRegPaletteWr; + STAMCOUNTER StatRegPitchLockWr; + STAMCOUNTER StatRegPseudoColorWr; + STAMCOUNTER StatRegReadOnlyWr; + STAMCOUNTER StatRegScratchWr; + STAMCOUNTER StatRegSyncWr; + STAMCOUNTER StatRegTopWr; + STAMCOUNTER StatRegTracesWr; + STAMCOUNTER StatRegUnknownWr; + STAMCOUNTER StatRegWidthWr; + + STAMCOUNTER StatRegBitsPerPixelRd; + STAMCOUNTER StatRegBlueMaskRd; + STAMCOUNTER StatRegBusyRd; + STAMCOUNTER StatRegBytesPerLineRd; + STAMCOUNTER StatRegCapabilitesRd; + STAMCOUNTER StatRegConfigDoneRd; + STAMCOUNTER StatRegCursorXxxxRd; + STAMCOUNTER StatRegDepthRd; + STAMCOUNTER StatRegDisplayHeightRd; + STAMCOUNTER StatRegDisplayIdRd; + STAMCOUNTER StatRegDisplayIsPrimaryRd; + STAMCOUNTER StatRegDisplayPositionXRd; + STAMCOUNTER StatRegDisplayPositionYRd; + STAMCOUNTER StatRegDisplayWidthRd; + STAMCOUNTER StatRegEnableRd; + STAMCOUNTER StatRegFbOffsetRd; + STAMCOUNTER StatRegFbSizeRd; + STAMCOUNTER StatRegFbStartRd; + STAMCOUNTER StatRegGmrIdRd; + STAMCOUNTER StatRegGmrMaxDescriptorLengthRd; + STAMCOUNTER StatRegGmrMaxIdsRd; + STAMCOUNTER StatRegGmrsMaxPagesRd; + STAMCOUNTER StatRegGreenMaskRd; + STAMCOUNTER StatRegGuestIdRd; + STAMCOUNTER StatRegHeightRd; + STAMCOUNTER StatRegHostBitsPerPixelRd; + STAMCOUNTER StatRegIdRd; + STAMCOUNTER StatRegIrqMaskRd; + STAMCOUNTER StatRegMaxHeightRd; + STAMCOUNTER StatRegMaxWidthRd; + STAMCOUNTER StatRegMemorySizeRd; + STAMCOUNTER StatRegMemRegsRd; + STAMCOUNTER StatRegMemSizeRd; + STAMCOUNTER StatRegMemStartRd; + STAMCOUNTER StatRegNumDisplaysRd; + STAMCOUNTER StatRegNumGuestDisplaysRd; + STAMCOUNTER StatRegPaletteRd; + STAMCOUNTER StatRegPitchLockRd; + STAMCOUNTER StatRegPsuedoColorRd; + STAMCOUNTER StatRegRedMaskRd; + STAMCOUNTER StatRegScratchRd; + STAMCOUNTER StatRegScratchSizeRd; + STAMCOUNTER StatRegSyncRd; + STAMCOUNTER StatRegTopRd; + STAMCOUNTER StatRegTracesRd; + STAMCOUNTER StatRegUnknownRd; + STAMCOUNTER StatRegVramSizeRd; + STAMCOUNTER StatRegWidthRd; + STAMCOUNTER StatRegWriteOnlyRd; } VMSVGAState; #endif /* VBOX_WITH_VMSVGA */