Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 64873)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 64874)
@@ -5092,5 +5092,5 @@
     /* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.  */
     if (   pVM->hm.s.fTprPatchingAllowed
-        && (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80                                                  /* TPR offset. */
+        && (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
         && (   !(u32ErrCode & X86_TRAP_PF_P)                                                             /* Not present */
             || (u32ErrCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD))  /* MMIO page. */
@@ -5102,5 +5102,5 @@
         GCPhysApicBase &= PAGE_BASE_GC_MASK;
 
-        if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
+        if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
         {
             /* Only attempt to patch the instruction once. */
@@ -5356,6 +5356,6 @@
     /* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
     if (   pVM->hm.s.fTprPatchingAllowed
-        && (uFaultAddress & 0xfff) == 0x80  /* TPR offset. */
-        && !(u32ErrCode & X86_TRAP_PF_P)    /* Not present. */
+        && (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
+        && !(u32ErrCode & X86_TRAP_PF_P)              /* Not present. */
         && !CPUMIsGuestInLongModeEx(pCtx)
         && !CPUMGetGuestCPL(pVCpu)