- Timestamp:
- Dec 14, 2016 2:13:53 PM (8 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (4 diffs)
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r64856 r64873 3431 3431 * the interrupt when we VM-exit for other reasons. 3432 3432 */ 3433 pVCpu->hm.s.vmx.pbVirtApic[ 0x80] = u8Tpr; /* Offset 0x80 is TPR in the APIC MMIO range. */3433 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr; 3434 3434 uint32_t u32TprThreshold = 0; 3435 3435 if (fPendingIntr) … … 8815 8815 */ 8816 8816 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) 8817 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[ 0x80];8817 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]; 8818 8818 8819 8819 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu(); … … 8996 8996 * portion of the code a bit. */ 8997 8997 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) 8998 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[ 0x80])8999 { 9000 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[ 0x80]);8998 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]) 8999 { 9000 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]); 9001 9001 AssertRC(rc); 9002 9002 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE); … … 12731 12731 { 12732 12732 AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) 12733 || VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != 0x80,12733 || VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != XAPIC_OFF_TPR, 12734 12734 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n")); 12735 12735
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