Changeset 63632 in vbox

Timestamp:

Aug 25, 2016 10:58:22 AM (8 years ago)

Author:

vboxsync

Message:

VMM/APIC: Initial Hyper-V support for synthetic interrupts, Hyper-V interface for direct TPR, EOI, ICR accesses.
Support for Hyper-V compatibility mode (x2APIC interface while operating in xAPIC mode).

Location:

trunk

Files:

• include/VBox/vmm/apic.h (modified) (3 diffs)
• src/VBox/Devices/testcase/tstDeviceStructSize.cpp (modified) (1 diff)
• src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/APICAll.cpp (modified) (22 diffs)
• src/VBox/VMM/VMMR3/APIC.cpp (modified) (3 diffs)
• src/VBox/VMM/include/APICInternal.h (modified) (9 diffs)

trunk/include/VBox/vmm/apic.h

@@ -141 +141 @@
 #define XAPIC_OFF_LVT_EXT_END                XAPIC_OFF_LVT_CMCI
 
+/** @name xAPIC Interrupt Command Register bits.
+ * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)".
+ * See Intel spec. 10.5.1 "Local Vector Table".
+ * @{ */
+/**
+ * xAPIC trigger mode.
+ */
+typedef enum XAPICTRIGGERMODE
+{
+    XAPICTRIGGERMODE_EDGE = 0,
+    XAPICTRIGGERMODE_LEVEL
+} XAPICTRIGGERMODE;
+
 RT_C_DECLS_BEGIN
 
@@ -148 +161 @@
  */
 VMMR3_INT_DECL(void)        APICR3InitIpi(PVMCPU pVCpu);
+VMMR3_INT_DECL(void)        APICR3HvEnable(PVM pVM);
 /** @} */
 #endif /* IN_RING3 */
@@ -165 +179 @@
 VMMDECL(bool)               APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr);
 
+/** @name Hyper-V interface (Ring-3 and all-context API).
+ * @{ */
+#ifdef IN_RING3
+VMMR3_INT_DECL(void)        APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode);
+#endif
+VMM_INT_DECL(void)          APICHvSendInterrupt(PVMCPU pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode);
+VMM_INT_DECL(VBOXSTRICTRC)  APICHvSetTpr(PVMCPU pVCpu, uint8_t uTpr);
+VMM_INT_DECL(uint8_t)       APICHvGetTpr(PVMCPU pVCpu);
+VMM_INT_DECL(VBOXSTRICTRC)  APICHvSetIcr(PVMCPU pVCpu, uint64_t uIcr);
+VMM_INT_DECL(uint64_t)      APICHvGetIcr(PVMCPU pVCpu);
+VMM_INT_DECL(VBOXSTRICTRC)  APICHvSetEoi(PVMCPU pVCpu, uint32_t uEoi);
+/** @} */
+
 RT_C_DECLS_END
 

trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

@@ -291 +291 @@
 #ifdef VBOX_WITH_NEW_APIC
     CHECK_MEMBER_ALIGNMENT(APICDEV, pDevInsR0, 8);
+    CHECK_MEMBER_ALIGNMENT(APICDEV, pCritSectR0, 8);
     CHECK_MEMBER_ALIGNMENT(APICDEV, pDevInsRC, 8);
+    CHECK_MEMBER_ALIGNMENT(APICDEV, pCritSectRC, 8);
 #else
 # ifdef VBOX_WITH_STATISTICS

trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

@@ -773 +773 @@
     GEN_CHECK_OFF(APICCPU, StatTimerIcrWrite);
     GEN_CHECK_OFF(APICCPU, StatIcrLoWrite);
+    GEN_CHECK_OFF(APICCPU, StatIcrHiWrite);
+    GEN_CHECK_OFF(APICCPU, StatIcrFullWrite);
 # endif /* VBOX_WITH_STATISTICS */
 #else

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -1055 +1055 @@
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
+    STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrHiWrite);
     Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
 
@@ -1091 +1092 @@
  * @param   rcRZ            The return code if the operation cannot be performed
  *                          in the current context.
+ *
+ * @remarks This function is used by both x2APIC interface and the Hyper-V
+ *          interface, see APICHvSetIcr(). The Hyper-V spec isn't clear what
+ *          happens when invalid bits are set. For the time being, it will #GP
+ *          like a regular x2APIC access.
  */
 static VBOXSTRICTRC apicSetIcr(PVMCPU pVCpu, uint64_t u64Icr, int rcRZ)
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    Assert(XAPIC_IN_X2APIC_MODE(pVCpu));
 
     /* Validate. */
@@ -1104 +1109 @@
         PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
         pX2ApicPage->icr_hi.u32IcrHi = RT_HI_U32(u64Icr);
-        return apicSetIcrLo(pVCpu, uLo,  rcRZ);
+        STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrHiWrite);
+        STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrFullWrite);
+        return apicSetIcrLo(pVCpu, uLo, rcRZ);
     }
     return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ICR, APICMSRACCESS_WRITE_RSVD_BITS);
@@ -1189 +1196 @@
  *
  * @returns Strict VBox status code.
- * @param   pVCpu           The cross context virtual CPU structure.
- * @param   uTpr            The TPR value.
- */
-static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr)
+ * @param   pVCpu                   The cross context virtual CPU structure.
+ * @param   uTpr                    The TPR value.
+ * @param   fForceX2ApicBehaviour   Pretend the APIC is in x2APIC mode during
+ *                                  this write.
+ */
+static VBOXSTRICTRC apicSetTprEx(PVMCPU pVCpu, uint32_t uTpr, bool fForceX2ApicBehaviour)
 {
     VMCPU_ASSERT_EMT(pVCpu);
 
-    Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
+    Log2(("APIC%u: apicSetTprEx: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
     STAM_COUNTER_INC(&pVCpu->apic.s.StatTprWrite);
 
-    if (   XAPIC_IN_X2APIC_MODE(pVCpu)
+    bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu) || fForceX2ApicBehaviour;
+    if (   fX2ApicMode
         && (uTpr & ~XAPIC_TPR_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
@@ -1215 +1225 @@
  *
  * @returns Strict VBox status code.
- * @param   pVCpu           The cross context virtual CPU structure.
- * @param   uEoi            The EOI value.
- */
-static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi)
+ * @param   pVCpu                   The cross context virtual CPU structure.
+ * @param   uEoi                    The EOI value.
+ * @param   fForceX2ApicBehaviour   Pretend the APIC is in x2APIC mode during
+ *                                  this write.
+ */
+static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi, bool fForceX2ApicBehaviour)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -1225 +1237 @@
     STAM_COUNTER_INC(&pVCpu->apic.s.StatEoiWrite);
 
-    if (   XAPIC_IN_X2APIC_MODE(pVCpu)
+    bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu) || fForceX2ApicBehaviour;
+    if (   fX2ApicMode
         && (uEoi & ~XAPIC_EOI_WO_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
@@ -1249 +1262 @@
             { /* likely */ }
             else
-                return XAPIC_IN_X2APIC_MODE(pVCpu) ? VINF_CPUM_R3_MSR_WRITE : VINF_IOM_R3_MMIO_WRITE;
+                return fX2ApicMode ? VINF_CPUM_R3_MSR_WRITE : VINF_IOM_R3_MMIO_WRITE;
 
             /*
@@ -1311 +1324 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
+    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
+    Assert(!XAPIC_IN_X2APIC_MODE(pVCpu) || pApic->fHyperVCompatMode); RT_NOREF_PV(pApic);
 
     Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
@@ -1601 +1615 @@
         pApicCpu->uHintedTimerShift = uTimerShift;
     }
+}
+
+
+/**
+ * Gets the Interrupt Command Register (ICR), without performing any interface
+ * checks.
+ *
+ * @returns The ICR value.
+ * @param   pVCpu           The cross context virtual CPU structure.
+ */
+DECLINLINE(uint64_t) apicGetIcrNoCheck(PVMCPU pVCpu)
+{
+    PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
+    uint64_t const uHi  = pX2ApicPage->icr_hi.u32IcrHi;
+    uint64_t const uLo  = pX2ApicPage->icr_lo.all.u32IcrLo;
+    uint64_t const uIcr = RT_MAKE_U64(uLo, uHi);
+    return uIcr;
 }
 
@@ -1719 +1750 @@
         case XAPIC_OFF_TPR:
         {
-            rcStrict = apicSetTpr(pVCpu, uValue);
+            rcStrict = apicSetTprEx(pVCpu, uValue, false /* fForceX2ApicBehaviour */);
             break;
         }
@@ -1744 +1775 @@
         case XAPIC_OFF_EOI:
         {
-            rcStrict = apicSetEoi(pVCpu, uValue);
+            rcStrict = apicSetEoi(pVCpu, uValue, false /* fForceX2ApicBehaviour */);
             break;
         }
@@ -1843 +1874 @@
     RT_NOREF_PV(pDevIns);
 
+    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
 #ifndef IN_RING3
-    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     if (pApic->fRZEnabled)
     { /* likely */}
@@ -1854 +1885 @@
 
     VBOXSTRICTRC rcStrict = VINF_SUCCESS;
-    if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
+    if (RT_LIKELY(   XAPIC_IN_X2APIC_MODE(pVCpu)
+                  || pApic->fHyperVCompatMode))
     {
         switch (u32Reg)
@@ -1861 +1893 @@
             case MSR_IA32_X2APIC_ICR:
             {
-                PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
-                uint64_t const uHi = pX2ApicPage->icr_hi.u32IcrHi;
-                uint64_t const uLo = pX2ApicPage->icr_lo.all.u32IcrLo;
-                *pu64Value = RT_MAKE_U64(uLo, uHi);
+                *pu64Value = apicGetIcrNoCheck(pVCpu);
                 break;
             }
@@ -1948 +1977 @@
     RT_NOREF_PV(pDevIns);
 
+    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
 #ifndef IN_RING3
-    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     if (pApic->fRZEnabled)
     { /* likely */ }
@@ -1973 +2002 @@
     uint32_t     u32Value = RT_LO_U32(u64Value);
     VBOXSTRICTRC rcStrict = VINF_SUCCESS;
-    if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
+    if (RT_LIKELY(   XAPIC_IN_X2APIC_MODE(pVCpu)
+                  || pApic->fHyperVCompatMode))
     {
         switch (u32Reg)
@@ -1979 +2009 @@
             case MSR_IA32_X2APIC_TPR:
             {
-                rcStrict = apicSetTpr(pVCpu, u32Value);
+                rcStrict = apicSetTprEx(pVCpu, u32Value, false /* fForceX2ApicBehaviour */);
                 break;
             }
@@ -2035 +2065 @@
             case MSR_IA32_X2APIC_EOI:
             {
-                rcStrict = apicSetEoi(pVCpu, u32Value);
+                rcStrict = apicSetEoi(pVCpu, u32Value, false /* fForceX2ApicBehaviour */);
                 break;
             }
 
+            /*
+             * Windows guest using Hyper-V x2APIC MSR compatibility mode tries to write the "high"
+             * LDR bits, which is quite absurd (as it's a 32-bit register) using this invalid MSR
+             * index (0x80E). The write value was 0xffffffff on a Windows 8.1 64-bit guest. We can
+             * safely ignore this nonsense, See @bugref{8382#c7}.
+             */
+            case MSR_IA32_X2APIC_LDR + 1:
+            {
+                if (pApic->fHyperVCompatMode)
+                    rcStrict = VINF_SUCCESS;
+                else
+                    rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
+                break;
+            }
+
+            /* Special-treament (read-only normally, but not with Hyper-V) */
+            case MSR_IA32_X2APIC_LDR:
+            {
+                if (pApic->fHyperVCompatMode)
+                {
+                    rcStrict = apicSetLdr(pVCpu, u32Value);
+                    break;
+                }
+                /* fallthru */
+            }
             /* Read-only MSRs: */
             case MSR_IA32_X2APIC_ID:
             case MSR_IA32_X2APIC_VERSION:
             case MSR_IA32_X2APIC_PPR:
-            case MSR_IA32_X2APIC_LDR:
             case MSR_IA32_X2APIC_ISR0:  case MSR_IA32_X2APIC_ISR1:  case MSR_IA32_X2APIC_ISR2:  case MSR_IA32_X2APIC_ISR3:
             case MSR_IA32_X2APIC_ISR4:  case MSR_IA32_X2APIC_ISR5:  case MSR_IA32_X2APIC_ISR6:  case MSR_IA32_X2APIC_ISR7:
@@ -2232 +2286 @@
 {
     RT_NOREF_PV(pDevIns);
-    apicSetTpr(pVCpu, u8Tpr);
+    apicSetTprEx(pVCpu, u8Tpr, false /* fForceX2ApicBehaviour */);
 }
 
@@ -2879 +2933 @@
             break;
 
-        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
-        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
-        {
-            uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
+        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->au64VectorBitmap));
+        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->au64VectorBitmap); idxPib++, idxReg += 2)
+        {
+            uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->au64VectorBitmap[idxPib], 0);
             if (u64Fragment)
             {
@@ -2906 +2960 @@
             break;
 
-        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
-        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
-        {
-            uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
+        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->au64VectorBitmap));
+        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->au64VectorBitmap); idxPib++, idxReg += 2)
+        {
+            uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->au64VectorBitmap[idxPib], 0);
             if (u64Fragment)
             {
@@ -2948 +3002 @@
 }
 
+
+/**
+ * Posts an interrupt to a target APIC, Hyper-V interface.
+ *
+ * @returns true if the interrupt was accepted, false otherwise.
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   uVector             The vector of the interrupt to be posted.
+ * @param   fAutoEoi            Whether this interrupt has automatic EOI
+ *                              treatment.
+ * @param   enmTriggerMode      The trigger mode of the interrupt.
+ *
+ * @thread  Any.
+ */
+VMM_INT_DECL(void) APICHvSendInterrupt(PVMCPU pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode)
+{
+    Assert(pVCpu);
+    Assert(!fAutoEoi);    /** @todo AutoEOI.  */
+    apicPostInterrupt(pVCpu, uVector, enmTriggerMode);
+}
+
+
+/**
+ * Sets the Task Priority Register (TPR), Hyper-V interface.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   uTpr        The TPR value to set.
+ *
+ * @remarks Validates like in x2APIC mode.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) APICHvSetTpr(PVMCPU pVCpu, uint8_t uTpr)
+{
+    Assert(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
+    return apicSetTprEx(pVCpu, uTpr, true /* fForceX2ApicBehaviour */);
+}
+
+
+/**
+ * Gets the Task Priority Register (TPR), Hyper-V interface.
+ *
+ * @returns The TPR value.
+ * @param   pVCpu           The cross context virtual CPU structure.
+ */
+VMM_INT_DECL(uint8_t) APICHvGetTpr(PVMCPU pVCpu)
+{
+    Assert(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
+
+    /*
+     * The APIC could be operating in xAPIC mode and thus we should not use the apicReadMsr()
+     * interface which validates the APIC mode and will throw a #GP(0) if not in x2APIC mode.
+     * We could use the apicReadRegister() MMIO interface, but why bother getting the PDMDEVINS
+     * pointer, so just directly read the APIC page.
+     */
+    PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
+    return apicReadRaw32(pXApicPage, XAPIC_OFF_TPR);
+}
+
+
+/**
+ * Sets the Interrupt Command Register (ICR), Hyper-V interface.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   uIcr        The ICR value to set.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) APICHvSetIcr(PVMCPU pVCpu, uint64_t uIcr)
+{
+    Assert(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
+    return apicSetIcr(pVCpu, uIcr, VINF_CPUM_R3_MSR_WRITE);
+}
+
+
+/**
+ * Gets the Interrupt Command Register (ICR), Hyper-V interface.
+ *
+ * @returns The ICR value.
+ * @param   pVCpu           The cross context virtual CPU structure.
+ */
+VMM_INT_DECL(uint64_t) APICHvGetIcr(PVMCPU pVCpu)
+{
+    Assert(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
+    return apicGetIcrNoCheck(pVCpu);
+}
+
+
+/**
+ * Sets the End-Of-Interrupt (EOI) register, Hyper-V interface.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu           The cross context virtual CPU structure.
+ * @param   uEoi            The EOI value.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) APICHvSetEoi(PVMCPU pVCpu, uint32_t uEoi)
+{
+    Assert(pVCpu);
+    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
+    return apicSetEoi(pVCpu, uEoi, true /* fForceX2ApicBehaviour */);
+}
+

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -355 +355 @@
 
 /**
+ * Sets whether Hyper-V compatibile x2APIC mode is enabled or not.
+ *
+ * @param   pVM                 The cross context VM structure.
+ * @param   fHyperVCompatMode   Whether the compatibility mode is enabled.
+ */
+VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
+{
+    Assert(pVM);
+    PAPIC pApic = VM_TO_APIC(pVM);
+    pApic->fHyperVCompatMode = fHyperVCompatMode;
+}
+
+
+/**
  * Helper for dumping an APIC 256-bit sparse register.
  *
@@ -413 +427 @@
     RT_ZERO(ApicReg);
     ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
-    ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->aVectorBitmap);
-    AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->aVectorBitmap));
+    ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
+    AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
     for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
     {
-        uint64_t const uFragment   = pApicPib->aVectorBitmap[idxPib];
+        uint64_t const uFragment   = pApicPib->au64VectorBitmap[idxPib];
         uint32_t const uFragmentLo = RT_LO_U32(uFragment);
         uint32_t const uFragmentHi = RT_HI_U32(uFragment);
@@ -1832 +1846 @@
         APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite,    "Number of times the ICR Lo (send IPI) is written.",
                          "/Devices/APIC/%u/IcrLoWrite");
+        APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite,    "Number of times the ICR Hi is written.",
+                         "/Devices/APIC/%u/IcrHiWrite");
+        APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite,  "Number of times the ICR full (send IPI, x2APIC) is written.",
+                         "/Devices/APIC/%u/IcrFullWrite");
     }
 # undef APIC_PROF_COUNTER

trunk/src/VBox/VMM/include/APICInternal.h

@@ -63 +63 @@
                                                   & (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD)) \
                                               ==    (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD) )
+
 /** Get an xAPIC page offset for an x2APIC MSR value. */
 #define X2APIC_GET_XAPIC_OFF(a_uMsr)         ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))
@@ -1066 +1067 @@
 /** @} */
 
-/** @name xAPIC Interrupt Command Register bits.
- * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)".
- * See Intel spec. 10.5.1 "Local Vector Table".
- * @{ */
-/**
- * xAPIC trigger mode.
- */
-typedef enum XAPICTRIGGERMODE
-{
-    XAPICTRIGGERMODE_EDGE = 0,
-    XAPICTRIGGERMODE_LEVEL
-} XAPICTRIGGERMODE;
-
 /**
  * xAPIC destination shorthand.
@@ -1123 +1111 @@
 /** @} */
 
+/** @def APIC_CACHE_LINE_SIZE
+ * Padding (in bytes) for aligning data in different cache lines. Present
+ * generation x86 CPUs use 64-byte cache lines[1]. However, Intel NetBurst
+ * architecture supposedly uses 128-byte cache lines[2]. Since 128 is a
+ * multiple of 64, we use the larger one here.
+ *
+ * [1] - Intel spec "Table 11-1. Characteristics of the Caches, TLBs, Store
+ *       Buffer, and Write Combining Buffer in Intel 64 and IA-32 Processors"
+ * [2] - Intel spec. 8.10.6.7 "Place Locks and Semaphores in Aligned, 128-Byte
+ *       Blocks of Memory".
+ */
+#define APIC_CACHE_LINE_SIZE              128
+
 /**
  * APIC Pending-Interrupt Bitmap (PIB).
@@ -1128 +1129 @@
 typedef struct APICPIB
 {
-    uint64_t volatile aVectorBitmap[4];
+    uint64_t volatile au64VectorBitmap[4];
     uint32_t volatile fOutstandingNotification;
-    uint8_t           au8Reserved[28];
+    uint8_t           au8Reserved[APIC_CACHE_LINE_SIZE - sizeof(uint32_t) - (sizeof(uint64_t) * 4)];
 } APICPIB;
 AssertCompileMemberOffset(APICPIB, fOutstandingNotification, 256 / 8);
-AssertCompileSize(APICPIB, 64);
+AssertCompileSize(APICPIB, APIC_CACHE_LINE_SIZE);
 /** Pointer to a pending-interrupt bitmap. */
 typedef APICPIB *PAPICPIB;
@@ -1167 +1168 @@
     PCPDMAPICHLPRC              pApicHlpRC;
     /** The PDM critical section - RC Ptr. */
-    RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
+    RCPTRTYPE(PPDMCRITSECT)     pCritSectRC;
     /** Alignment padding. */
     RCPTRTYPE(void *)           pvAlignment2;
@@ -1227 +1228 @@
     /** Whether RZ is enabled or not (applies to MSR handling as well). */
     bool                        fRZEnabled;
+    /** Whether Hyper-V x2APIC compatibility mode is enabled. */
+    bool                        fHyperVCompatMode;
     /** Alignment padding. */
-    bool                        afAlignment0[7];
+    bool                        afAlignment[2];
     /** The max supported APIC mode from CFGM.  */
     PDMAPICMODE                 enmMaxMode;
+    /** Alignment padding. */
+    uint32_t                    u32Alignment1;
     /** @} */
 } APIC;
@@ -1237 +1242 @@
 /** Pointer to const APIC VM instance data. */
 typedef APIC const *PCAPIC;
+AssertCompileMemberAlignment(APIC, cbApicPib, 8);
+AssertCompileMemberAlignment(APIC, fVirtApicRegsEnabled, 8);
+AssertCompileMemberAlignment(APIC, enmMaxMode, 8);
+AssertCompileSizeAlignment(APIC, 8);
 
 /**
@@ -1285 +1294 @@
     /** The APIC PIB for level-sensitive interrupts. */
     APICPIB                     ApicPibLevel;
+    /** @} */
+
+    /** @name Other miscellaneous data.
+     * @{ */
     /** Whether the LINT0 interrupt line is active. */
     bool volatile               fActiveLint0;
@@ -1361 +1374 @@
     /** Number of times the ICR Lo (send IPI) is written. */
     STAMCOUNTER                 StatIcrLoWrite;
+    /** Number of times the ICR Hi is written. */
+    STAMCOUNTER                 StatIcrHiWrite;
+    /** Number of times the full ICR (x2APIC send IPI) is written. */
+    STAMCOUNTER                 StatIcrFullWrite;
     /** @} */
 #endif