VirtualBox

Changeset 62410 in vbox for trunk


Ignore:
Timestamp:
Jul 21, 2016 8:26:33 PM (8 years ago)
Author:
vboxsync
Message:

bs3kit: Added a instruction test case for imul & idiv.

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
4 added
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/ValidationKit/bootsectors/Makefile.kmk

    r61701 r62410  
    292292#       $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3-cpu-decoding-1-asm.o16
    293293
     294
     295# CPU instructions #2 (first being bootsector2-cpu-instr-1).
     296MISCBINS += bs3-cpu-instr-2
     297bs3-cpu-instr-2_TEMPLATE = VBoxBS3KitImg
     298bs3-cpu-instr-2_INCS  = .
     299bs3-cpu-instr-2_DEFS  =  BS3_CMN_INSTANTIATE_FILE1=bs3-cpu-instr-2-template.c
     300bs3-cpu-instr-2_DEFS += BS3_MODE_INSTANTIATE_FILE1=bs3-cpu-instr-2-template.c
     301bs3-cpu-instr-2_SOURCES = \
     302        bs3kit/bs3-first-rm.asm \
     303        bs3-cpu-instr-2.c \
     304        bs3-cpu-instr-2-asm.asm \
     305       bs3kit/bs3-cmn-instantiate-x0.c16 \
     306       bs3kit/bs3-cmn-instantiate.c32 \
     307       bs3kit/bs3-cmn-instantiate.c64
     308bs3-cpu-instr-2-template.o:: \
     309        $$(bs3-cpu-instr-2_0_OUTDIR)/bs3kit/bs3-cmn-instantiate-x0.o16 \
     310        $$(bs3-cpu-instr-2_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o32 \
     311        $$(bs3-cpu-instr-2_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o64 \
     312        $$(bs3-cpu-instr-2_0_OUTDIR)/bs3-cpu-instr-2-asm.o16
     313
    294314endif # VBOX_WITH_BS3KIT
    295315
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32

    r61547 r62410  
    7171     */
    7272#if 1
    73     /* Using currently undefined 0x0f 0x38 sequences. */
    74     {        0,  2,   3,         { 0x0f, 0x38, RM_EAX_EAX, } },
    75     {        0,  2+1, 3+1,       { P_LK, 0x0f, 0x38, RM_EAX_EAX, } },
    76     {        0,  2+1, 3+1,       { P_RN, 0x0f, 0x38, RM_EAX_EAX, } },
    77     {        0,  2+1, 3+1,       { P_RZ, 0x0f, 0x38, RM_EAX_EAX, } },
    78     {        0,  2+2, 3+2, { P_LK, P_LK, 0x0f, 0x38, RM_EAX_EAX, } },
    79 #endif
    80 #if 1
     73    /* Using currently undefined 0x0f 0x7a sequences. */
     74    {        0, 3,   3,               { 0x0f, 0x7a, RM_EAX_EAX, } },
     75    {        0, 3+1, 3+1,       { P_LK, 0x0f, 0x7a, RM_EAX_EAX, } },
     76    {        0, 3+1, 3+1,       { P_RN, 0x0f, 0x7a, RM_EAX_EAX, } },
     77    {        0, 3+1, 3+1,       { P_RZ, 0x0f, 0x7a, RM_EAX_EAX, } },
     78    {        0, 3+2, 3+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_EAX, } },
     79#endif
     80#if 0
    8181    /* The XADD instruction has empty lines for 66, f3 and f2 prefixes.
    8282       AMD doesn't do anything special for XADD Ev,Gv as the intel table would indicate. */
     
    9090    {    F_486,   99,  5, { P_RZ, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } },
    9191#endif
    92 #if 1
     92#if 0
    9393    /* The movnti instruction is confined to the unprefixed lined in the intel manuals. Check how the other lines work. */
    9494    {   F_SSE2,    3,  3,             { 0x0f, 0xc3, RM_EAX_EAX, } },        /* invalid - reg,reg */
     
    100100    {   F_SSE2,    5,  5, { P_RZ, P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } },  /* invalid */
    101101#endif
     102#if 1
    102103    /* The lddqu instruction requires a 0xf2 prefix, intel only lists 0x66 and empty
    103104       prefix for it.  Check what they really mean by that*/
     
    117118    {   F_SSE3,   99,  5,      { P_OZ, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
    118119    {   F_SSE3,   99,  6,{ P_OZ, P_RN, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
     120#endif
     121    {   F_SSE2,   99,  3,            { 0x0f, 0x7e, RM_EAX_EAX, } },
     122    {   F_SSE2,   99,  4,      { P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } },
     123    {   F_SSE2,    5,  5,{ P_RZ, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, // WTF?
     124    {   F_SSE2,    5,  5,{ P_OZ, P_RZ, 0x0f, 0x7e, RM_EAX_EAX, } },
     125    {   F_SSE2,   99,  5,{ P_RN, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } },
     126    {   F_SSE2,   99,  4,      { P_RN, 0x0f, 0x7e, RM_EAX_EAX, } },
     127    {   F_SSE2,    4,  4,      { P_RZ, 0x0f, 0x7e, RM_EAX_EAX, } },
    119128/** @todo crc32 / movbe  */
    120129};
     
    147156            while (cb >= 1)
    148157            {
     158                unsigned const   cErrorsBefore = Bs3TestSubErrorCount();
    149159                uint8_t BS3_FAR *pbRip = &pbPages[X86_PAGE_SIZE - cb];
    150160                Bs3MemCpy(pbRip, &g_aSimpleTests[i].abOpcodes[0], cb);
     
    158168                {
    159169                    if (TrapFrame.bXcpt != X86_XCPT_UD)
    160                         Bs3TestFailedF("i=%d cb=%d cbUd=%d cb=%d: expected #UD got %#x\n",
    161                                        i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes, TrapFrame.bXcpt);
     170                        Bs3TestFailedF("i=%d cb=%d cbUd=%d cbOp=%d: expected #UD got %#x at %RX32\n",
     171                                       i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes,
     172                                       TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
    162173                }
    163174                else if (cb < g_aSimpleTests[i].cbOpcodes)
    164175                {
    165176                    if (TrapFrame.bXcpt != X86_XCPT_PF)
    166                         Bs3TestFailedF("i=%d cb=%d cbUd=%d cb=%d: expected #PF (on) got %#x\n",
    167                                        i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes, TrapFrame.bXcpt);
     177                        Bs3TestFailedF("i=%d cb=%d cbUd=%d cbOp=%d: expected #PF (on) got %#x at %RX32\n",
     178                                       i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes,
     179                                       TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
    168180                    else if (TrapFrame.Ctx.rip.u32 != (uintptr_t)pbRip)
    169                         Bs3TestFailedF("i=%d cb=%d cbUd=%d cb=%d: expected #PF rip of %p (on) got %#RX32\n",
     181                        Bs3TestFailedF("i=%d cb=%d cbUd=%d cbOp=%d: expected #PF rip of %p (on) got %#RX32\n",
    170182                                       i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes,
    171183                                       pbRip, TrapFrame.Ctx.rip.u32);
     
    174186                {
    175187                    if (TrapFrame.bXcpt != X86_XCPT_PF)
    176                         Bs3TestFailedF("i=%d cb=%d cbUd=%d cb=%d: expected #PF (after) got %#x\n",
    177                                        i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes, TrapFrame.bXcpt);
     188                        Bs3TestFailedF("i=%d cb=%d cbUd=%d cbOp=%d: expected #PF (after) got %#x at %RX32\n",
     189                                       i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes,
     190                                       TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
    178191                    else if (TrapFrame.Ctx.rip.u32 != (uintptr_t)&pbPages[X86_PAGE_SIZE])
    179                         Bs3TestFailedF("i=%d cb=%d cbUd=%d cb=%d: expected #PF rip of %p (after) got %#RX32\n",
     192                        Bs3TestFailedF("i=%d cb=%d cbUd=%d cbOp=%d: expected #PF rip of %p (after) got %#RX32\n",
    180193                                       i, cb, g_aSimpleTests[i].cbUd, g_aSimpleTests[i].cbOpcodes,
    181194                                       &pbPages[X86_PAGE_SIZE], TrapFrame.Ctx.rip.u32);
    182195                }
     196                if (Bs3TestSubErrorCount() != cErrorsBefore)
     197                {
     198                    Bs3TestPrintf("  %.*Rhxs", cb, &g_aSimpleTests[i].abOpcodes[0]);
     199                    if (cb < g_aSimpleTests[i].cbOpcodes)
     200                        Bs3TestPrintf("[%.*Rhxs]", g_aSimpleTests[i].cbOpcodes - cb, &g_aSimpleTests[i].abOpcodes[cb]);
     201                    Bs3TestPrintf("\n");
     202                }
     203
     204                /* next */
    183205                cb--;
    184206            }
  • trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h

    r61487 r62410  
    24202420 * @param   pRegCtx     Where to store the register context.
    24212421 */
    2422 BS3_CMN_PROTO_NOSB(void, Bs3RegCtxSave,(PCBS3REGCTX pRegCtx));
     2422BS3_CMN_PROTO_NOSB(void, Bs3RegCtxSave,(PBS3REGCTX pRegCtx));
    24232423
    24242424/**
     
    24372437 * @param   cbExtraStack    Number of bytes of additional stack to allocate.
    24382438 */
    2439 BS3_CMN_PROTO_FARSTUB(8, void, Bs3RegCtxSaveEx,(PCBS3REGCTX pRegCtx, uint8_t bBitMode, uint16_t cbExtraStack));
     2439BS3_CMN_PROTO_FARSTUB(8, void, Bs3RegCtxSaveEx,(PBS3REGCTX pRegCtx, uint8_t bBitMode, uint16_t cbExtraStack));
    24402440
    24412441/**
     
    30273027 * A set of standard protypes to go with #BS3TESTMODEENTRY_CMN. */
    30283028#define BS3TESTMODE_PROTOTYPES_CMN(a_BaseNm) \
    3029     FNBS3TESTDOMODE BS3_FAR_CODE    RT_CONCAT(a_BaseNm, _c16); \
    3030     FNBS3TESTDOMODE BS3_FAR_CODE    RT_CONCAT(a_BaseNm, _c32); \
    3031     FNBS3TESTDOMODE BS3_FAR_CODE    RT_CONCAT(a_BaseNm, _c64)
     3029    FNBS3TESTDOMODE /*BS3_FAR_CODE*/    RT_CONCAT(a_BaseNm, _c16); \
     3030    FNBS3TESTDOMODE /*BS3_FAR_CODE*/    RT_CONCAT(a_BaseNm, _c32); \
     3031    FNBS3TESTDOMODE /*BS3_FAR_CODE*/    RT_CONCAT(a_BaseNm, _c64)
    30323032
    30333033/** @def BS3TESTMODEENTRY_MODE
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