Index: /trunk/include/VBox/err.h =================================================================== --- /trunk/include/VBox/err.h (revision 61846) +++ /trunk/include/VBox/err.h (revision 61847) @@ -2765,4 +2765,6 @@ /** Pending interrupt is masked by TPR. */ #define VERR_APIC_INTR_MASKED_BY_TPR (-6701) +/** APIC did not accept the interrupt. */ +#define VERR_APIC_INTR_DISCARDED (-6702) /** @} */ Index: /trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp =================================================================== --- /trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp (revision 61846) +++ /trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp (revision 61847) @@ -224,31 +224,23 @@ #ifdef VBOX_WITH_STATISTICS - /** Number of MMIO reads in R0. */ - STAMCOUNTER StatMmioReadR0; + /** Number of MMIO reads in RZ. */ + STAMCOUNTER StatMmioReadRZ; /** Number of MMIO reads in R3. */ STAMCOUNTER StatMmioReadR3; - /** Number of MMIO reads in RC. */ - STAMCOUNTER StatMmioReadRC; - - /** Number of MMIO writes in R0. */ - STAMCOUNTER StatMmioWriteR0; + + /** Number of MMIO writes in RZ. */ + STAMCOUNTER StatMmioWriteRZ; /** Number of MMIO writes in R3. */ STAMCOUNTER StatMmioWriteR3; - /** Number of MMIO writes in RC. */ - STAMCOUNTER StatMmioWriteRC; - - /** Number of SetIrq calls in R0. */ - STAMCOUNTER StatSetIrqR0; + + /** Number of SetIrq calls in RZ. */ + STAMCOUNTER StatSetIrqRZ; /** Number of SetIrq calls in R3. */ STAMCOUNTER StatSetIrqR3; - /** Number of SetIrq calls in RC. */ - STAMCOUNTER StatSetIrqRC; - - /** Number of SetEoi calls in R0. */ - STAMCOUNTER StatSetEoiR0; + + /** Number of SetEoi calls in RZ. */ + STAMCOUNTER StatSetEoiRZ; /** Number of SetEoi calls in R3. */ STAMCOUNTER StatSetEoiR3; - /** Number of SetEoi calls in RC. */ - STAMCOUNTER StatSetEoiRC; /** Number of redundant edge-triggered interrupts. */ @@ -262,4 +254,9 @@ /** Number of returns to ring-3 due to Set RTE lock contention. */ STAMCOUNTER StatSetRteContention; + /** Number of level-triggered interrupts dispatched to the local APIC(s). */ + STAMCOUNTER StatLevelIrqSent; + /** Number of EOIs received for level-triggered interrupts from the local + * APIC(s). */ + STAMCOUNTER StatEoiReceived; #endif } IOAPIC; @@ -406,5 +403,9 @@ u32TagSrc); /* Can't reschedule to R3. */ - Assert(rc == VINF_SUCCESS); + Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); +#ifdef DEBUG_ramshankar + if (rc == VERR_APIC_INTR_DISCARDED) + AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte)); +#endif /* @@ -417,8 +418,10 @@ * ioapicSetIrq() callback. */ - if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL) + if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL + && rc == VINF_SUCCESS) { Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL); pThis->au64RedirTable[idxRte] |= IOAPIC_RTE_REMOTE_IRR; + STAM_COUNTER_INC(&pThis->StatLevelIrqSent); } } @@ -479,5 +482,5 @@ uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK); uint32_t const u32RteLo = RT_LO_U32(u64Rte); - uint64_t const u64RteNewHi = ((uint64_t)(uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) << 32) | u32RtePreserveHi; + uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) | u32RtePreserveHi) << 32); pThis->au64RedirTable[idxRte] = u64RteNewHi | u32RteLo; } @@ -569,5 +572,5 @@ { PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); - STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetEoi)); + STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi)); LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector)); @@ -581,6 +584,8 @@ if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector) { + Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte)); pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR; fRemoteIrrCleared = true; + STAM_COUNTER_INC(&pThis->StatEoiReceived); Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector)); @@ -612,5 +617,5 @@ LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc)); - STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetIrq)); + STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq)); if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable))) @@ -738,5 +743,5 @@ uTagSrc); /* Can't reschedule to R3. */ - Assert(rc == VINF_SUCCESS); + Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); } @@ -748,5 +753,5 @@ { PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); - STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioRead)); + STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); int rc = VINF_SUCCESS; @@ -781,5 +786,5 @@ PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); - STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioWrite)); + STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); Assert(!(GCPhysAddr & 3)); @@ -1247,9 +1252,8 @@ * Statistics. */ - bool fHasRC = !HMIsEnabledNotMacro(PDMDevHlpGetVM(pDevIns)); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioReadR0", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R0."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioWriteR0", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R0."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetIrqR0", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R0."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetEoiR0", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R0."); + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ."); + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ."); + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ."); + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ."); PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3"); @@ -1258,12 +1262,4 @@ PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3."); - if (fHasRC) - { - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioReadRC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RC."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioWriteRC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RC."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetIrqRC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RC."); - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetEoiRC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RC."); - } - PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change)."); PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change)."); @@ -1272,4 +1268,7 @@ PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3."); PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3."); + + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s)."); + PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s)."); #endif Index: /trunk/src/VBox/Devices/PC/DevIoApic.cpp =================================================================== --- /trunk/src/VBox/Devices/PC/DevIoApic.cpp (revision 61846) +++ /trunk/src/VBox/Devices/PC/DevIoApic.cpp (revision 61847) @@ -180,5 +180,5 @@ /* We must be sure that attempts to reschedule in R3 never get here */ - Assert(rc == VINF_SUCCESS); + Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); } } @@ -524,5 +524,5 @@ /* We must be sure that attempts to reschedule in R3 never get here */ - Assert(rc == VINF_SUCCESS); + Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); } Index: /trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp =================================================================== --- /trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp (revision 61846) +++ /trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp (revision 61847) @@ -339,5 +339,5 @@ CHECK_MEMBER_ALIGNMENT(IOAPIC, au64RedirTable, 8); # ifdef VBOX_WITH_STATISTICS - CHECK_MEMBER_ALIGNMENT(IOAPIC, StatMmioReadR0, 8); + CHECK_MEMBER_ALIGNMENT(IOAPIC, StatMmioReadRZ, 8); # endif #else Index: /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp =================================================================== --- /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp (revision 61846) +++ /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp (revision 61847) @@ -885,16 +885,12 @@ GEN_CHECK_OFF(IOAPIC, uIrr); # ifdef VBOX_WITH_STATISTICS - GEN_CHECK_OFF(IOAPIC, StatMmioReadR0); + GEN_CHECK_OFF(IOAPIC, StatMmioReadRZ); GEN_CHECK_OFF(IOAPIC, StatMmioReadR3); - GEN_CHECK_OFF(IOAPIC, StatMmioReadRC); - GEN_CHECK_OFF(IOAPIC, StatMmioWriteR0); + GEN_CHECK_OFF(IOAPIC, StatMmioWriteRZ); GEN_CHECK_OFF(IOAPIC, StatMmioWriteR3); - GEN_CHECK_OFF(IOAPIC, StatMmioWriteRC); - GEN_CHECK_OFF(IOAPIC, StatSetIrqR0); + GEN_CHECK_OFF(IOAPIC, StatSetIrqRZ); GEN_CHECK_OFF(IOAPIC, StatSetIrqR3); - GEN_CHECK_OFF(IOAPIC, StatSetIrqRC); - GEN_CHECK_OFF(IOAPIC, StatSetEoiR0); + GEN_CHECK_OFF(IOAPIC, StatSetEoiRZ); GEN_CHECK_OFF(IOAPIC, StatSetEoiR3); - GEN_CHECK_OFF(IOAPIC, StatSetEoiRC); # endif #else Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp (revision 61846) +++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp (revision 61847) @@ -598,12 +598,16 @@ * @param enmDeliveryMode The delivery mode. * @param pDestCpuSet The destination CPU set. + * @param pfIntrAccepted Where to store whether this interrupt was + * accepted by the target APIC(s) or not. + * Optional, can be NULL. * @param rcRZ The return code if the operation cannot be * performed in the current context. */ static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode, - XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ) -{ - VBOXSTRICTRC rcStrict = VINF_SUCCESS; - VMCPUID const cCpus = pVM->cCpus; + XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, bool *pfIntrAccepted, int rcRZ) +{ + VBOXSTRICTRC rcStrict = VINF_SUCCESS; + VMCPUID const cCpus = pVM->cCpus; + bool fAccepted = false; switch (enmDeliveryMode) { @@ -614,5 +618,5 @@ if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu) && apicIsEnabled(&pVM->aCpus[idCpu])) - apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode); + fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode); } break; @@ -624,7 +628,7 @@ if ( idCpu < pVM->cCpus && apicIsEnabled(&pVM->aCpus[idCpu])) - apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode); + fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode); else - Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n")); + AssertMsgFailed(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n")); break; } @@ -638,4 +642,5 @@ Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu)); apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI); + fAccepted = true; } } @@ -652,4 +657,5 @@ Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu)); apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI); + fAccepted = true; } } @@ -665,8 +671,10 @@ Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu)); VMMR3SendInitIpi(pVM, idCpu); + fAccepted = true; } #else /* We need to return to ring-3 to deliver the INIT. */ rcStrict = rcRZ; + fAccepted = true; #endif break; @@ -681,8 +689,10 @@ Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu)); VMMR3SendStartupIpi(pVM, idCpu, uVector); + fAccepted = true; } #else /* We need to return to ring-3 to deliver the SIPI. */ rcStrict = rcRZ; + fAccepted = true; Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ)); #endif @@ -697,4 +707,5 @@ Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu)); apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT); + fAccepted = true; } break; @@ -735,4 +746,8 @@ } } + + if (pfIntrAccepted) + *pfIntrAccepted = fAccepted; + return rcStrict; } @@ -1006,5 +1021,6 @@ } - return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ); + return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, + NULL /* pfIntrAccepted */, rcRZ); } @@ -1254,4 +1270,6 @@ apicSignalNextPendingIntr(pVCpu); } + else + AssertMsgFailed(("APIC%u: apicSetEoi: Failed to find any ISR bit\n", pVCpu->idCpu)); return VINF_SUCCESS; @@ -2275,9 +2293,12 @@ uVector)); + bool fIntrAccepted; VMCPUSET DestCpuSet; apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet); VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, - VINF_SUCCESS /* rcRZ */); - return VBOXSTRICTRC_VAL(rcStrict); + &fIntrAccepted, VINF_SUCCESS /* rcRZ */); + if (fIntrAccepted) + return VBOXSTRICTRC_VAL(rcStrict); + return VERR_APIC_INTR_DISCARDED; } @@ -2379,5 +2400,5 @@ VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu); rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, - &DestCpuSet, rcRZ); + &DestCpuSet, NULL /* pfIntrAccepted */, rcRZ); } break; @@ -2392,5 +2413,5 @@ uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt); rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, - rcRZ); + NULL /* pfIntrAccepted */, rcRZ); break; } @@ -2600,4 +2621,5 @@ * Don't use this function to try and deliver ExtINT style interrupts. * + * @returns true if the interrupt was accepted, false otherwise. * @param pVCpu The cross context virtual CPU structure. * @param uVector The vector of the interrupt to be posted. @@ -2606,12 +2628,13 @@ * @thread Any. */ -VMM_INT_DECL(void) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode) +VMM_INT_DECL(bool) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode) { Assert(pVCpu); Assert(uVector > XAPIC_ILLEGAL_VECTOR_END); - PVM pVM = pVCpu->CTX_SUFF(pVM); - PCAPIC pApic = VM_TO_APIC(pVM); - PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); + PVM pVM = pVCpu->CTX_SUFF(pVM); + PCAPIC pApic = VM_TO_APIC(pVM); + PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); + bool fAccepted = true; STAM_PROFILE_START(&pApicCpu->StatPostIntr, a); @@ -2630,5 +2653,5 @@ if (!apicTestVectorInReg(&pXApicPage->irr, uVector)) /* PAV */ { - Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector)); + Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector)); if (enmTriggerMode == XAPICTRIGGERMODE_EDGE) { @@ -2641,5 +2664,5 @@ if (!fAlreadySet) { - Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector)); + Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector)); apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING); } @@ -2656,5 +2679,5 @@ if (!fAlreadySet) { - Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector)); + Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector)); apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING); } @@ -2663,5 +2686,5 @@ else { - Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM), + Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector)); STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending); @@ -2669,7 +2692,11 @@ } else + { + fAccepted = false; apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR); + } STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a); + return fAccepted; } @@ -2817,4 +2844,5 @@ /* Update edge-triggered pending interrupts. */ + PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib); for (;;) { @@ -2823,7 +2851,5 @@ break; - PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib); AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap)); - for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2) { @@ -2845,4 +2871,5 @@ /* Update level-triggered pending interrupts. */ + pPib = (PAPICPIB)&pApicCpu->ApicPibLevel; for (;;) { @@ -2851,7 +2878,5 @@ break; - PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel; AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap)); - for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2) { Index: /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp (revision 61846) +++ /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp (revision 61847) @@ -64,4 +64,5 @@ * The local APIC has a higher priority than the PIC. */ + int rc = VERR_NO_DATA; if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC)) { @@ -71,5 +72,5 @@ uint32_t uTagSrc; uint8_t uVector; - int rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc); + rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc); if (RT_SUCCESS(rc)) { @@ -119,5 +120,5 @@ pdmUnlock(pVM); - return VERR_NO_DATA; + return rc; } Index: /trunk/src/VBox/VMM/VMMR3/APIC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/APIC.cpp (revision 61846) +++ /trunk/src/VBox/VMM/VMMR3/APIC.cpp (revision 61847) @@ -1797,5 +1797,5 @@ } while(0) - bool const fHasRC = !HMIsEnabled(pVM); + bool const fHasRC = !HMIsEnabledNotMacro(pVM); for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) { Index: /trunk/src/VBox/VMM/include/APICInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/APICInternal.h (revision 61846) +++ /trunk/src/VBox/VMM/include/APICInternal.h (revision 61847) @@ -1442,5 +1442,5 @@ uint8_t uVector, uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc); -VMM_INT_DECL(void) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode); +VMM_INT_DECL(bool) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode); VMM_INT_DECL(void) apicStartTimer(PVMCPU pVCpu, uint32_t uInitialCount); VMM_INT_DECL(void) apicStopTimer(PVMCPU pVCpu);