VirtualBox

Changeset 61847 in vbox


Ignore:
Timestamp:
Jun 23, 2016 12:03:01 PM (8 years ago)
Author:
vboxsync
Message:

IOAPIC, VMM/APIC: Use dedicated rc for when the APIC doesn't accept an IRQ (very rare but can happen).
Also added more stats, assertions to verify interrupt delivery a bit better.

Location:
trunk
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/err.h

    r61544 r61847  
    27652765/** Pending interrupt is masked by TPR. */
    27662766#define VERR_APIC_INTR_MASKED_BY_TPR                (-6701)
     2767/** APIC did not accept the interrupt. */
     2768#define VERR_APIC_INTR_DISCARDED                    (-6702)
    27672769/** @} */
    27682770

  • trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp

    r61845 r61847  
    224224
    225225#ifdef VBOX_WITH_STATISTICS
    226     /** Number of MMIO reads in R0. */
    227     STAMCOUNTER             StatMmioReadR0;
     226    /** Number of MMIO reads in RZ. */
     227    STAMCOUNTER             StatMmioReadRZ;
    228228    /** Number of MMIO reads in R3. */
    229229    STAMCOUNTER             StatMmioReadR3;
    230     /** Number of MMIO reads in RC. */
    231     STAMCOUNTER             StatMmioReadRC;
    232 
    233     /** Number of MMIO writes in R0. */
    234     STAMCOUNTER             StatMmioWriteR0;
     230
     231    /** Number of MMIO writes in RZ. */
     232    STAMCOUNTER             StatMmioWriteRZ;
    235233    /** Number of MMIO writes in R3. */
    236234    STAMCOUNTER             StatMmioWriteR3;
    237     /** Number of MMIO writes in RC. */
    238     STAMCOUNTER             StatMmioWriteRC;
    239 
    240     /** Number of SetIrq calls in R0. */
    241     STAMCOUNTER             StatSetIrqR0;
     235
     236    /** Number of SetIrq calls in RZ. */
     237    STAMCOUNTER             StatSetIrqRZ;
    242238    /** Number of SetIrq calls in R3. */
    243239    STAMCOUNTER             StatSetIrqR3;
    244     /** Number of SetIrq calls in RC. */
    245     STAMCOUNTER             StatSetIrqRC;
    246 
    247     /** Number of SetEoi calls in R0. */
    248     STAMCOUNTER             StatSetEoiR0;
     240
     241    /** Number of SetEoi calls in RZ. */
     242    STAMCOUNTER             StatSetEoiRZ;
    249243    /** Number of SetEoi calls in R3. */
    250244    STAMCOUNTER             StatSetEoiR3;
    251     /** Number of SetEoi calls in RC. */
    252     STAMCOUNTER             StatSetEoiRC;
    253245
    254246    /** Number of redundant edge-triggered interrupts. */
    … …  
    262254    /** Number of returns to ring-3 due to Set RTE lock contention. */
    263255    STAMCOUNTER             StatSetRteContention;
     256    /** Number of level-triggered interrupts dispatched to the local APIC(s). */
     257    STAMCOUNTER             StatLevelIrqSent;
     258    /** Number of EOIs received for level-triggered interrupts from the local
     259     *  APIC(s). */
     260    STAMCOUNTER             StatEoiReceived;
    264261#endif
    265262} IOAPIC;
    … …  
    406403                                                                u32TagSrc);
    407404        /* Can't reschedule to R3. */
    408         Assert(rc == VINF_SUCCESS);
     405        Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
     406#ifdef DEBUG_ramshankar
     407        if (rc == VERR_APIC_INTR_DISCARDED)
     408            AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
     409#endif
    409410
    410411        /*
    … …  
    417418         * ioapicSetIrq() callback.
    418419         */
    419         if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
     420        if (   u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
     421            && rc == VINF_SUCCESS)
    420422        {
    421423            Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
    422424            pThis->au64RedirTable[idxRte] |= IOAPIC_RTE_REMOTE_IRR;
     425            STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
    423426        }
    424427    }
    … …  
    479482            uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK);
    480483            uint32_t const u32RteLo         = RT_LO_U32(u64Rte);
    481             uint64_t const u64RteNewHi      = ((uint64_t)(uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) << 32) | u32RtePreserveHi;
     484            uint64_t const u64RteNewHi      = ((uint64_t)((uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) | u32RtePreserveHi) << 32);
    482485            pThis->au64RedirTable[idxRte]   = u64RteNewHi | u32RteLo;
    483486        }
    … …  
    569572{
    570573    PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
    571     STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetEoi));
     574    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
    572575    LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
    573576
    … …  
    581584            if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
    582585            {
     586                Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
    583587                pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
    584588                fRemoteIrrCleared = true;
     589                STAM_COUNTER_INC(&pThis->StatEoiReceived);
    585590                Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
    586591
    … …  
    612617    LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
    613618
    614     STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetIrq));
     619    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
    615620
    616621    if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
    … …  
    738743                                                            uTagSrc);
    739744    /* Can't reschedule to R3. */
    740     Assert(rc == VINF_SUCCESS);
     745    Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
    741746}
    742747
    … …  
    748753{
    749754    PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
    750     STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioRead));
     755    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
    751756
    752757    int       rc      = VINF_SUCCESS;
    … …  
    781786    PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
    782787
    783     STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioWrite));
     788    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
    784789
    785790    Assert(!(GCPhysAddr & 3));
    … …  
    12471252     * Statistics.
    12481253     */
    1249     bool fHasRC = !HMIsEnabledNotMacro(PDMDevHlpGetVM(pDevIns));
    1250     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR0,  STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioReadR0",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R0.");
    1251     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioWriteR0", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R0.");
    1252     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR0,    STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetIrqR0",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R0.");
    1253     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR0,    STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetEoiR0",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R0.");
     1254    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
     1255    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
     1256    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
     1257    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
    12541258
    12551259    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
    … …  
    12581262    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3,    STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
    12591263
    1260     if (fHasRC)
    1261     {
    1262         PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRC,  STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioReadRC",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RC.");
    1263         PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioWriteRC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RC.");
    1264         PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRC,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetIrqRC",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RC.");
    1265         PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRC,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetEoiRC",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RC.");
    1266     }
    1267 
    12681264    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr,   STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr",   STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
    12691265    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr,  STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr",  STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
    … …  
    12721268    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention,    STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
    12731269    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
     1270
     1271    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
     1272    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived,  STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
    12741273#endif
    12751274

  • trunk/src/VBox/Devices/PC/DevIoApic.cpp

    r61841 r61847  
    180180                /* We must be sure that attempts to reschedule in R3
    181181                   never get here */
    182                 Assert(rc == VINF_SUCCESS);
     182                Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
    183183            }
    184184        }
    … …  
    524524    /* We must be sure that attempts to reschedule in R3
    525525       never get here */
    526     Assert(rc == VINF_SUCCESS);
     526    Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
    527527}
    528528

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

    r61339 r61847  
    339339    CHECK_MEMBER_ALIGNMENT(IOAPIC, au64RedirTable, 8);
    340340# ifdef VBOX_WITH_STATISTICS
    341     CHECK_MEMBER_ALIGNMENT(IOAPIC, StatMmioReadR0, 8);
     341    CHECK_MEMBER_ALIGNMENT(IOAPIC, StatMmioReadRZ, 8);
    342342# endif
    343343#else

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r61776 r61847  
    885885    GEN_CHECK_OFF(IOAPIC, uIrr);
    886886# ifdef VBOX_WITH_STATISTICS
    887     GEN_CHECK_OFF(IOAPIC, StatMmioReadR0);
     887    GEN_CHECK_OFF(IOAPIC, StatMmioReadRZ);
    888888    GEN_CHECK_OFF(IOAPIC, StatMmioReadR3);
    889     GEN_CHECK_OFF(IOAPIC, StatMmioReadRC);
    890     GEN_CHECK_OFF(IOAPIC, StatMmioWriteR0);
     889    GEN_CHECK_OFF(IOAPIC, StatMmioWriteRZ);
    891890    GEN_CHECK_OFF(IOAPIC, StatMmioWriteR3);
    892     GEN_CHECK_OFF(IOAPIC, StatMmioWriteRC);
    893     GEN_CHECK_OFF(IOAPIC, StatSetIrqR0);
     891    GEN_CHECK_OFF(IOAPIC, StatSetIrqRZ);
    894892    GEN_CHECK_OFF(IOAPIC, StatSetIrqR3);
    895     GEN_CHECK_OFF(IOAPIC, StatSetIrqRC);
    896     GEN_CHECK_OFF(IOAPIC, StatSetEoiR0);
     893    GEN_CHECK_OFF(IOAPIC, StatSetEoiRZ);
    897894    GEN_CHECK_OFF(IOAPIC, StatSetEoiR3);
    898     GEN_CHECK_OFF(IOAPIC, StatSetEoiRC);
    899895# endif
    900896#else

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r61807 r61847  
    598598 * @param   enmDeliveryMode     The delivery mode.
    599599 * @param   pDestCpuSet         The destination CPU set.
     600 * @param   pfIntrAccepted      Where to store whether this interrupt was
     601 *                              accepted by the target APIC(s) or not.
     602 *                              Optional, can be NULL.
    600603 * @param   rcRZ                The return code if the operation cannot be
    601604 *                              performed in the current context.
    602605 */
    603606static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
    604                                  XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
    605 {
    606     VBOXSTRICTRC  rcStrict = VINF_SUCCESS;
    607     VMCPUID const cCpus    = pVM->cCpus;
     607                                 XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, bool *pfIntrAccepted, int rcRZ)
     608{
     609    VBOXSTRICTRC  rcStrict  = VINF_SUCCESS;
     610    VMCPUID const cCpus     = pVM->cCpus;
     611    bool          fAccepted = false;
    608612    switch (enmDeliveryMode)
    609613    {
    … …  
    614618                if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
    615619                    && apicIsEnabled(&pVM->aCpus[idCpu]))
    616                     apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
     620                    fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
    617621            }
    618622            break;
    … …  
    624628            if (   idCpu < pVM->cCpus
    625629                && apicIsEnabled(&pVM->aCpus[idCpu]))
    626                 apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
     630                fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
    627631            else
    628                 Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
     632                AssertMsgFailed(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
    629633            break;
    630634        }
    … …  
    638642                    Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
    639643                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
     644                    fAccepted = true;
    640645                }
    641646            }
    … …  
    652657                    Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
    653658                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
     659                    fAccepted = true;
    654660                }
    655661            }
    … …  
    665671                    Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
    666672                    VMMR3SendInitIpi(pVM, idCpu);
     673                    fAccepted = true;
    667674                }
    668675#else
    669676            /* We need to return to ring-3 to deliver the INIT. */
    670677            rcStrict = rcRZ;
     678            fAccepted = true;
    671679#endif
    672680            break;
    … …  
    681689                    Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
    682690                    VMMR3SendStartupIpi(pVM, idCpu, uVector);
     691                    fAccepted = true;
    683692                }
    684693#else
    685694            /* We need to return to ring-3 to deliver the SIPI. */
    686695            rcStrict = rcRZ;
     696            fAccepted = true;
    687697            Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
    688698#endif
    … …  
    697707                    Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
    698708                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
     709                    fAccepted = true;
    699710                }
    700711            break;
    … …  
    735746        }
    736747    }
     748
     749    if (pfIntrAccepted)
     750        *pfIntrAccepted = fAccepted;
     751
    737752    return rcStrict;
    738753}
    … …  
    10061021    }
    10071022
    1008     return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
     1023    return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
     1024                        NULL /* pfIntrAccepted */, rcRZ);
    10091025}
    10101026
    … …  
    12541270        apicSignalNextPendingIntr(pVCpu);
    12551271    }
     1272    else
     1273        AssertMsgFailed(("APIC%u: apicSetEoi: Failed to find any ISR bit\n", pVCpu->idCpu));
    12561274
    12571275    return VINF_SUCCESS;
    … …  
    22752293          uVector));
    22762294
     2295    bool     fIntrAccepted;
    22772296    VMCPUSET DestCpuSet;
    22782297    apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
    22792298    VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
    2280                                          VINF_SUCCESS /* rcRZ */);
    2281     return VBOXSTRICTRC_VAL(rcStrict);
     2299                                         &fIntrAccepted, VINF_SUCCESS /* rcRZ */);
     2300    if (fIntrAccepted)
     2301        return VBOXSTRICTRC_VAL(rcStrict);
     2302    return VERR_APIC_INTR_DISCARDED;
    22822303}
    22832304
    … …  
    23792400                        VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
    23802401                        rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode,
    2381                                                 &DestCpuSet, rcRZ);
     2402                                                &DestCpuSet, NULL /* pfIntrAccepted */, rcRZ);
    23822403                    }
    23832404                    break;
    … …  
    23922413                    uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
    23932414                    rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
    2394                                             rcRZ);
     2415                                            NULL /* pfIntrAccepted */, rcRZ);
    23952416                    break;
    23962417                }
    … …  
    26002621 * Don't use this function to try and deliver ExtINT style interrupts.
    26012622 *
     2623 * @returns true if the interrupt was accepted, false otherwise.
    26022624 * @param   pVCpu               The cross context virtual CPU structure.
    26032625 * @param   uVector             The vector of the interrupt to be posted.
    … …  
    26062628 * @thread  Any.
    26072629 */
    2608 VMM_INT_DECL(void) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
     2630VMM_INT_DECL(bool) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
    26092631{
    26102632    Assert(pVCpu);
    26112633    Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
    26122634
    2613     PVM      pVM      = pVCpu->CTX_SUFF(pVM);
    2614     PCAPIC   pApic    = VM_TO_APIC(pVM);
    2615     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
     2635    PVM      pVM       = pVCpu->CTX_SUFF(pVM);
     2636    PCAPIC   pApic     = VM_TO_APIC(pVM);
     2637    PAPICCPU pApicCpu  = VMCPU_TO_APICCPU(pVCpu);
     2638    bool     fAccepted = true;
    26162639
    26172640    STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
    … …  
    26302653        if (!apicTestVectorInReg(&pXApicPage->irr, uVector))     /* PAV */
    26312654        {
    2632             Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
     2655            Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
    26332656            if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
    26342657            {
    … …  
    26412664                    if (!fAlreadySet)
    26422665                    {
    2643                         Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
     2666                        Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
    26442667                        apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
    26452668                    }
    … …  
    26562679                if (!fAlreadySet)
    26572680                {
    2658                     Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
     2681                    Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
    26592682                    apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
    26602683                }
    … …  
    26632686        else
    26642687        {
    2665             Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
     2688            Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
    26662689                  pVCpu->idCpu, uVector));
    26672690            STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
    … …  
    26692692    }
    26702693    else
     2694    {
     2695        fAccepted = false;
    26712696        apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
     2697    }
    26722698
    26732699    STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
     2700    return fAccepted;
    26742701}
    26752702
    … …  
    28172844
    28182845    /* Update edge-triggered pending interrupts. */
     2846    PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
    28192847    for (;;)
    28202848    {
    … …  
    28232851            break;
    28242852
    2825         PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
    28262853        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
    2827 
    28282854        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
    28292855        {
    … …  
    28452871
    28462872    /* Update level-triggered pending interrupts. */
     2873    pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
    28472874    for (;;)
    28482875    {
    … …  
    28512878            break;
    28522879
    2853         PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
    28542880        AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
    2855 
    28562881        for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
    28572882        {

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r61685 r61847  
    6464     * The local APIC has a higher priority than the PIC.
    6565     */
     66    int rc = VERR_NO_DATA;
    6667    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
    6768    {
    … …  
    7172        uint32_t uTagSrc;
    7273        uint8_t  uVector;
    73         int rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc);
     74        rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc);
    7475        if (RT_SUCCESS(rc))
    7576        {
    … …  
    119120
    120121    pdmUnlock(pVM);
    121     return VERR_NO_DATA;
     122    return rc;
    122123}
    123124

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r61812 r61847  
    17971797    } while(0)
    17981798
    1799     bool const fHasRC = !HMIsEnabled(pVM);
     1799    bool const fHasRC = !HMIsEnabledNotMacro(pVM);
    18001800    for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
    18011801    {

  • trunk/src/VBox/VMM/include/APICInternal.h

    r61809 r61847  
    14421442                                             uint8_t uVector, uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc);
    14431443
    1444 VMM_INT_DECL(void)            apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode);
     1444VMM_INT_DECL(bool)            apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode);
    14451445VMM_INT_DECL(void)            apicStartTimer(PVMCPU pVCpu, uint32_t uInitialCount);
    14461446VMM_INT_DECL(void)            apicStopTimer(PVMCPU pVCpu);
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