- Timestamp:
- May 20, 2016 4:12:35 AM (8 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/include/APICInternal.h (modified) (2 diffs)
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trunk/src/VBox/VMM/include/APICInternal.h
r61072 r61076 81 81 /** The APIC hardware version number for Pentium 6. */ 82 82 #define XAPIC_HARDWARE_VERSION_P6 UINT8_C(0x10) 83 84 /**85 * The xAPIC sparse 256-bit register.86 */87 typedef union XAPIC256BITREG88 {89 /** The sparse-bitmap view. */90 struct91 {92 uint32_t u32Reg;93 uint32_t uReserved0[3];94 } u[8];95 /** The 32-bit view. */96 uint32_t au32[32];97 } XAPIC256BITREG;98 /** Pointer to an xAPIC sparse bitmap register. */99 typedef XAPIC256BITREG *PXAPIC256BITREG;100 /** Pointer to a const xAPIC sparse bitmap register. */101 typedef XAPIC256BITREG const *PCXAPIC256BITREG;102 AssertCompileSize(XAPIC256BITREG, 128);103 104 /**105 * The xAPIC memory layout as per Intel/AMD specs.106 */107 typedef struct XAPICPAGE108 {109 /* 0x00 - Reserved. */110 uint32_t uReserved0[8];111 /* 0x20 - APIC ID. */112 struct113 {114 uint8_t u8Reserved0[3];115 uint8_t u8ApicId;116 uint32_t u32Reserved0[3];117 } id;118 /* 0x30 - APIC version register. */119 union120 {121 struct122 {123 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4124 uint8_t u8Version;125 #else126 # error "Implement Pentium and P6 family APIC architectures"127 #endif128 uint8_t uReserved0;129 uint8_t u8MaxLvtEntry;130 uint8_t fEoiBroadcastSupression : 1;131 uint8_t u7Reserved1 : 7;132 uint32_t u32Reserved0[3];133 } u;134 struct135 {136 uint32_t u32Version;137 uint32_t u32Reserved0[3];138 } all;139 } version;140 /* 0x40 - Reserved. */141 uint32_t uReserved1[16];142 /* 0x80 - Task Priority Register (TPR). */143 struct144 {145 uint8_t u8Tpr;146 uint8_t u8Reserved0[3];147 uint32_t u32Reserved0[3];148 } tpr;149 /* 0x90 - Arbitration Priority Register (APR). */150 struct151 {152 uint8_t u8Apr;153 uint8_t u8Reserved0[3];154 uint32_t u32Reserved0[3];155 } apr;156 /* 0xA0 - Processor Priority Register (PPR). */157 struct158 {159 uint8_t u8Ppr;160 uint8_t u8Reserved0[3];161 uint32_t u32Reserved0[3];162 } ppr;163 /* 0xB0 - End Of Interrupt Register (EOI). */164 struct165 {166 uint32_t u32Eoi;167 uint32_t u32Reserved0[3];168 } eoi;169 /* 0xC0 - Remote Read Register (RRD). */170 struct171 {172 uint32_t u32Rrd;173 uint32_t u32Reserved0[3];174 } rrd;175 /* 0xD0 - Logical Destination Register (LDR). */176 union177 {178 struct179 {180 uint8_t u8Reserved0[3];181 uint8_t u8LogicalApicId;182 uint32_t u32Reserved0[3];183 } u;184 struct185 {186 uint32_t u32Ldr;187 uint32_t u32Reserved0[3];188 } all;189 } ldr;190 /* 0xE0 - Destination Format Register (DFR). */191 union192 {193 struct194 {195 uint32_t u28ReservedMb1 : 28; /* MB1 */196 uint32_t u4Model : 4;197 uint32_t u32Reserved0[3];198 } u;199 struct200 {201 uint32_t u32Dfr;202 uint32_t u32Reserved0[3];203 } all;204 } dfr;205 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */206 union207 {208 struct209 {210 uint32_t u8SpuriousVector : 8;211 uint32_t fApicSoftwareEnable : 1;212 uint32_t u3Reserved0 : 3;213 uint32_t fSupressEoiBroadcast : 1;214 uint32_t u19Reserved1 : 19;215 uint32_t u32Reserved0[3];216 } u;217 struct218 {219 uint32_t u32Svr;220 uint32_t u32Reserved0[3];221 } all;222 } svr;223 /* 0x100 - In-service Register (ISR). */224 XAPIC256BITREG isr;225 /* 0x180 - Trigger Mode Register (TMR). */226 XAPIC256BITREG tmr;227 /* 0x200 - Interrupt Request Register (IRR). */228 XAPIC256BITREG irr;229 /* 0x280 - Error Status Register (ESR). */230 union231 {232 struct233 {234 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4235 uint32_t u4Reserved0 : 4;236 #else237 # error "Implement Pentium and P6 family APIC architectures"238 #endif239 uint32_t fRedirectableIpi : 1;240 uint32_t fSendIllegalVector : 1;241 uint32_t fRcvdIllegalVector : 1;242 uint32_t fIllegalRegAddr : 1;243 uint32_t u24Reserved1 : 24;244 uint32_t u32Reserved0[3];245 } u;246 struct247 {248 uint32_t u32Errors;249 uint32_t u32Reserved0[3];250 } all;251 } esr;252 /* 0x290 - Reserved. */253 uint32_t uReserved2[28];254 /* 0x300 - Interrupt Command Register (ICR) - Low. */255 union256 {257 struct258 {259 uint32_t u8Vector : 8;260 uint32_t u3DeliveryMode : 3;261 uint32_t u1DestMode : 1;262 uint32_t u1DeliveryStatus : 1;263 uint32_t fReserved0 : 1;264 uint32_t u1Level : 1;265 uint32_t u1TriggerMode : 1;266 uint32_t u2Reserved1 : 2;267 uint32_t u2DestShorthand : 2;268 uint32_t u12Reserved2 : 12;269 uint32_t u32Reserved0[3];270 } u;271 struct272 {273 uint32_t u32IcrLo;274 uint32_t u32Reserved0[3];275 } all;276 } icr_lo;277 /* 0x310 - Interrupt Comannd Register (ICR) - High. */278 union279 {280 struct281 {282 uint32_t u24Reserved0 : 24;283 uint32_t u8Dest : 8;284 uint32_t u32Reserved0[3];285 } u;286 struct287 {288 uint32_t u32IcrHi;289 uint32_t u32Reserved0[3];290 } all;291 } icr_hi;292 /* 0x320 - Local Vector Table (LVT) Timer Register. */293 union294 {295 struct296 {297 uint32_t u8Vector : 8;298 uint32_t u4Reserved0 : 4;299 uint32_t u1DeliveryStatus : 1;300 uint32_t u3Reserved1 : 3;301 uint32_t u1Mask : 1;302 uint32_t u2TimerMode : 2;303 uint32_t u13Reserved2 : 13;304 uint32_t u32Reserved0[3];305 } u;306 struct307 {308 uint32_t u32LvtTimer;309 uint32_t u32Reserved0[3];310 } all;311 } lvt_timer;312 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */313 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4314 union315 {316 struct317 {318 uint32_t u8Vector : 8;319 uint32_t u3DeliveryMode : 3;320 uint32_t u1Reserved0 : 1;321 uint32_t u1DeliveryStatus : 1;322 uint32_t u3Reserved1 : 3;323 uint32_t u1Mask : 1;324 uint32_t u15Reserved2 : 15;325 uint32_t u32Reserved0[3];326 } u;327 struct328 {329 uint32_t u32LvtThermal;330 uint32_t u32Reserved0[3];331 } all;332 } lvt_thermal;333 #else334 # error "Implement Pentium and P6 family APIC architectures"335 #endif336 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */337 union338 {339 struct340 {341 uint32_t u8Vector : 8;342 uint32_t u3DeliveryMode : 3;343 uint32_t u1Reserved0 : 1;344 uint32_t u1DeliveryStatus : 1;345 uint32_t u3Reserved1 : 3;346 uint32_t u1Mask : 1;347 uint32_t u15Reserved2 : 15;348 uint32_t u32Reserved0[3];349 } u;350 struct351 {352 uint32_t u32LvtPerf;353 uint32_t u32Reserved0[3];354 } all;355 } lvt_perf;356 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */357 union358 {359 struct360 {361 uint32_t u8Vector : 8;362 uint32_t u3DeliveryMode : 3;363 uint32_t u1Reserved0 : 1;364 uint32_t u1DeliveryStatus : 1;365 uint32_t u1IntrPolarity : 1;366 uint32_t u1RemoteIrr : 1;367 uint32_t u1TriggerMode : 1;368 uint32_t u1Mask : 1;369 uint32_t u15Reserved2 : 15;370 uint32_t u32Reserved0[3];371 } u;372 struct373 {374 uint32_t u32LvtLint0;375 uint32_t u32Reserved0[3];376 } all;377 } lvt_lint0;378 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */379 union380 {381 struct382 {383 uint32_t u8Vector : 8;384 uint32_t u3DeliveryMode : 3;385 uint32_t u1Reserved0 : 1;386 uint32_t u1DeliveryStatus : 1;387 uint32_t u1IntrPolarity : 1;388 uint32_t u1RemoteIrr : 1;389 uint32_t u1TriggerMode : 1;390 uint32_t u1Mask : 1;391 uint32_t u15Reserved2 : 15;392 uint32_t u32Reserved0[3];393 } u;394 struct395 {396 uint32_t u32LvtLint1;397 uint32_t u32Reserved0[3];398 } all;399 } lvt_lint1;400 /* 0x370 - Local Vector Table (LVT) Error Register. */401 union402 {403 struct404 {405 uint32_t u8Vector : 8;406 uint32_t u4Reserved0 : 4;407 uint32_t u1DeliveryStatus : 1;408 uint32_t u3Reserved1 : 3;409 uint32_t u1Mask : 1;410 uint32_t u15Reserved2 : 15;411 uint32_t u32Reserved0[3];412 } u;413 struct414 {415 uint32_t u32LvtError;416 uint32_t u32Reserved0[3];417 } all;418 } lvt_error;419 /* 0x380 - Timer Initial Counter Register. */420 struct421 {422 uint32_t u32InitialCount;423 uint32_t u32Reserved0[3];424 } timer_icr;425 /* 0x390 - Timer Current Counter Register. */426 struct427 {428 uint32_t u32CurrentCount;429 uint32_t u32Reserved0[3];430 } timer_ccr;431 /* 0x3A0 - Reserved. */432 uint32_t u32Reserved3[16];433 /* 0x3E0 - Timer Divide Configuration Register. */434 union435 {436 struct437 {438 uint32_t u2DivideValue0 : 2;439 uint32_t u1Reserved0 : 1;440 uint32_t u1DivideValue1 : 1;441 uint32_t u28Reserved1 : 28;442 uint32_t u32Reserved0[3];443 } u;444 struct445 {446 uint32_t u32DivideValue;447 uint32_t u32Reserved0[3];448 } all;449 } timer_dcr;450 /* 0x3F0 - Reserved. */451 uint8_t u8Reserved0[3088];452 } XAPICPAGE;453 /** Pointer to a XAPICPAGE struct. */454 typedef XAPICPAGE *PXAPICPAGE;455 /** Pointer to a const XAPICPAGE struct. */456 typedef const XAPICPAGE *PCXAPICPAGE;457 AssertCompileSize(XAPICPAGE, 4096);458 AssertCompileMemberOffset(XAPICPAGE, id, XAPIC_OFF_ID);459 AssertCompileMemberOffset(XAPICPAGE, version, XAPIC_OFF_VERSION);460 AssertCompileMemberOffset(XAPICPAGE, tpr, XAPIC_OFF_TPR);461 AssertCompileMemberOffset(XAPICPAGE, apr, XAPIC_OFF_APR);462 AssertCompileMemberOffset(XAPICPAGE, ppr, XAPIC_OFF_PPR);463 AssertCompileMemberOffset(XAPICPAGE, eoi, XAPIC_OFF_EOI);464 AssertCompileMemberOffset(XAPICPAGE, rrd, XAPIC_OFF_RRD);465 AssertCompileMemberOffset(XAPICPAGE, ldr, XAPIC_OFF_LDR);466 AssertCompileMemberOffset(XAPICPAGE, dfr, XAPIC_OFF_DFR);467 AssertCompileMemberOffset(XAPICPAGE, svr, XAPIC_OFF_SVR);468 AssertCompileMemberOffset(XAPICPAGE, isr, XAPIC_OFF_ISR0);469 AssertCompileMemberOffset(XAPICPAGE, tmr, XAPIC_OFF_TMR0);470 AssertCompileMemberOffset(XAPICPAGE, irr, XAPIC_OFF_IRR0);471 AssertCompileMemberOffset(XAPICPAGE, esr, XAPIC_OFF_ESR);472 AssertCompileMemberOffset(XAPICPAGE, icr_lo, XAPIC_OFF_ICR_LO);473 AssertCompileMemberOffset(XAPICPAGE, icr_hi, XAPIC_OFF_ICR_HI);474 AssertCompileMemberOffset(XAPICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER);475 AssertCompileMemberOffset(XAPICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL);476 AssertCompileMemberOffset(XAPICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF);477 AssertCompileMemberOffset(XAPICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0);478 AssertCompileMemberOffset(XAPICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1);479 AssertCompileMemberOffset(XAPICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR);480 AssertCompileMemberOffset(XAPICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR);481 AssertCompileMemberOffset(XAPICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR);482 AssertCompileMemberOffset(XAPICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR);483 484 /**485 * The x2APIC memory layout as per Intel/AMD specs.486 */487 typedef struct X2APICPAGE488 {489 /* 0x00 - Reserved. */490 uint32_t uReserved0[8];491 /* 0x20 - APIC ID. */492 struct493 {494 uint32_t u32ApicId;495 uint32_t u32Reserved0[3];496 } id;497 /* 0x30 - APIC version register. */498 union499 {500 struct501 {502 uint8_t u8Version;503 uint8_t u8Reserved0;504 uint8_t u8MaxLvtEntry;505 uint8_t fEoiBroadcastSupression : 1;506 uint8_t u7Reserved1 : 7;507 uint32_t u32Reserved0[3];508 } u;509 struct510 {511 uint32_t u32Version;512 uint32_t u32Reserved2[3];513 } all;514 } version;515 /* 0x40 - Reserved. */516 uint32_t uReserved1[16];517 /* 0x80 - Task Priority Register (TPR). */518 struct519 {520 uint8_t u8Tpr;521 uint8_t u8Reserved0[3];522 uint32_t u32Reserved0[3];523 } tpr;524 /* 0x90 - Reserved. */525 uint32_t uReserved2[4];526 /* 0xA0 - Processor Priority Register (PPR). */527 struct528 {529 uint8_t u8Ppr;530 uint8_t u8Reserved0[3];531 uint32_t u32Reserved0[3];532 } ppr;533 /* 0xB0 - End Of Interrupt Register (EOI). */534 struct535 {536 uint32_t u32Eoi;537 uint32_t u32Reserved0[3];538 } eoi;539 /* 0xC0 - Remote Read Register (RRD). */540 struct541 {542 uint32_t u32Rrd;543 uint32_t u32Reserved0[3];544 } rrd;545 /* 0xD0 - Logical Destination Register (LDR). */546 struct547 {548 uint32_t u32LogicalApicId;549 uint32_t u32Reserved1[3];550 } ldr;551 /* 0xE0 - Reserved. */552 uint32_t uReserved3[4];553 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */554 union555 {556 struct557 {558 uint32_t u8SpuriousVector : 8;559 uint32_t fApicSoftwareEnable : 1;560 uint32_t u3Reserved0 : 3;561 uint32_t fSupressEoiBroadcast : 1;562 uint32_t u19Reserved1 : 19;563 uint32_t u32Reserved0[3];564 } u;565 struct566 {567 uint32_t u32Svr;568 uint32_t uReserved0[3];569 } all;570 } svr;571 /* 0x100 - In-service Register (ISR). */572 XAPIC256BITREG isr;573 /* 0x180 - Trigger Mode Register (TMR). */574 XAPIC256BITREG tmr;575 /* 0x200 - Interrupt Request Register (IRR). */576 XAPIC256BITREG irr;577 /* 0x280 - Error Status Register (ESR). */578 union579 {580 struct581 {582 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4583 uint32_t u4Reserved0 : 4;584 #else585 # error "Implement Pentium and P6 family APIC architectures"586 #endif587 uint32_t fRedirectableIpi : 1;588 uint32_t fSendIllegalVector : 1;589 uint32_t fRcvdIllegalVector : 1;590 uint32_t fIllegalRegAddr : 1;591 uint32_t u24Reserved1 : 24;592 uint32_t uReserved0[3];593 } u;594 struct595 {596 uint32_t u32Errors;597 uint32_t u32Reserved0[3];598 } all;599 } esr;600 /* 0x290 - Reserved. */601 uint32_t uReserved4[28];602 /* 0x300 - Interrupt Command Register (ICR) - Low. */603 union604 {605 struct606 {607 uint32_t u8Vector : 8;608 uint32_t u3DeliveryMode : 3;609 uint32_t u1DestMode : 1;610 uint32_t u2Reserved0 : 2;611 uint32_t u1Level : 1;612 uint32_t u1TriggerMode : 1;613 uint32_t u2Reserved1 : 2;614 uint32_t u2DestShorthand : 2;615 uint32_t u12Reserved2 : 12;616 uint32_t u32Reserved0[3];617 } u;618 struct619 {620 uint32_t u32IcrLo;621 uint32_t u32Reserved3[3];622 } all;623 } icr_lo;624 /* 0x310 - Interrupt Comannd Register (ICR) - High. */625 struct626 {627 uint32_t u32IcrHi;628 uint32_t uReserved1[3];629 } icr_hi;630 /* 0x320 - Local Vector Table (LVT) Timer Register. */631 union632 {633 struct634 {635 uint32_t u8Vector : 8;636 uint32_t u4Reserved0 : 4;637 uint32_t u1DeliveryStatus : 1;638 uint32_t u3Reserved1 : 3;639 uint32_t u1Mask : 1;640 uint32_t u2TimerMode : 2;641 uint32_t u13Reserved2 : 13;642 uint32_t u32Reserved0[3];643 } u;644 struct645 {646 uint32_t u32LvtTimer;647 uint32_t u32Reserved0[3];648 } all;649 } lvt_timer;650 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */651 union652 {653 struct654 {655 uint32_t u8Vector : 8;656 uint32_t u3DeliveryMode : 3;657 uint32_t u1Reserved0 : 1;658 uint32_t u1DeliveryStatus : 1;659 uint32_t u3Reserved1 : 3;660 uint32_t u1Mask : 1;661 uint32_t u15Reserved2 : 15;662 uint32_t u32Reserved0[3];663 } u;664 struct665 {666 uint32_t u32LvtThermal;667 uint32_t uReserved0[3];668 } all;669 } lvt_thermal;670 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */671 union672 {673 struct674 {675 uint32_t u8Vector : 8;676 uint32_t u3DeliveryMode : 3;677 uint32_t u1Reserved0 : 1;678 uint32_t u1DeliveryStatus : 1;679 uint32_t u3Reserved1 : 3;680 uint32_t u1Mask : 1;681 uint32_t u15Reserved2 : 15;682 uint32_t u32Reserved0[3];683 } u;684 struct685 {686 uint32_t u32LvtPerf;687 uint32_t u32Reserved0[3];688 } all;689 } lvt_perf;690 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */691 union692 {693 struct694 {695 uint32_t u8Vector : 8;696 uint32_t u3DeliveryMode : 3;697 uint32_t u1Reserved0 : 1;698 uint32_t u1DeliveryStatus : 1;699 uint32_t u1IntrPolarity : 1;700 uint32_t u1RemoteIrr : 1;701 uint32_t u1TriggerMode : 1;702 uint32_t u1Mask : 1;703 uint32_t u15Reserved2 : 15;704 uint32_t u32Reserved0[3];705 } u;706 struct707 {708 uint32_t u32LvtLint0;709 uint32_t u32Reserved0[3];710 } all;711 } lvt_lint0;712 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */713 union714 {715 struct716 {717 uint32_t u8Vector : 8;718 uint32_t u3DeliveryMode : 3;719 uint32_t u1Reserved0 : 1;720 uint32_t u1DeliveryStatus : 1;721 uint32_t u1IntrPolarity : 1;722 uint32_t u1RemoteIrr : 1;723 uint32_t u1TriggerMode : 1;724 uint32_t u1Mask : 1;725 uint32_t u15Reserved2 : 15;726 uint32_t u32Reserved0[3];727 } u;728 struct729 {730 uint32_t u32LvtLint1;731 uint32_t u32Reserved0[3];732 } all;733 } lvt_lint1;734 /* 0x370 - Local Vector Table (LVT) Error Register. */735 union736 {737 struct738 {739 uint32_t u8Vector : 8;740 uint32_t u4Reserved0 : 4;741 uint32_t u1DeliveryStatus : 1;742 uint32_t u3Reserved1 : 3;743 uint32_t u1Mask : 1;744 uint32_t u15Reserved2 : 15;745 uint32_t u32Reserved0[3];746 } u;747 struct748 {749 uint32_t u32LvtError;750 uint32_t u32Reserved0[3];751 } all;752 } lvt_error;753 /* 0x380 - Timer Initial Counter Register. */754 struct755 {756 uint32_t u32InitialCount;757 uint32_t u32Reserved0[3];758 } timer_icr;759 /* 0x390 - Timer Current Counter Register. */760 struct761 {762 uint32_t u32CurrentCount;763 uint32_t u32Reserved0[3];764 } timer_ccr;765 /* 0x3A0 - Reserved. */766 uint32_t uReserved5[16];767 /* 0x3E0 - Timer Divide Configuration Register. */768 union769 {770 struct771 {772 uint32_t u2DivideValue0 : 2;773 uint32_t u1Reserved0 : 1;774 uint32_t u1DivideValue1 : 1;775 uint32_t u28Reserved1 : 28;776 uint32_t u32Reserved0[3];777 } u;778 struct779 {780 uint32_t u32DivideValue;781 uint32_t u32Reserved0[3];782 } all;783 } timer_dcr;784 /* 0x3F0 - Self IPI Register. */785 struct786 {787 uint32_t u8Vector : 8;788 uint32_t u24Reserved0 : 24;789 uint32_t u32Reserved0[3];790 } self_ipi;791 /* 0x400 - Reserved. */792 uint8_t u8Reserved0[3072];793 } X2APICPAGE;794 /** Pointer to a X2APICPAGE struct. */795 typedef X2APICPAGE *PX2APICPAGE;796 /** Pointer to a const X2APICPAGE struct. */797 typedef const X2APICPAGE *PCX2APICPAGE;798 AssertCompileSize(X2APICPAGE, 4096);799 AssertCompileSize(X2APICPAGE, sizeof(XAPICPAGE));800 AssertCompileMemberOffset(X2APICPAGE, id, XAPIC_OFF_ID);801 AssertCompileMemberOffset(X2APICPAGE, version, XAPIC_OFF_VERSION);802 AssertCompileMemberOffset(X2APICPAGE, tpr, XAPIC_OFF_TPR);803 AssertCompileMemberOffset(X2APICPAGE, ppr, XAPIC_OFF_PPR);804 AssertCompileMemberOffset(X2APICPAGE, eoi, XAPIC_OFF_EOI);805 AssertCompileMemberOffset(X2APICPAGE, rrd, XAPIC_OFF_RRD);806 AssertCompileMemberOffset(X2APICPAGE, ldr, XAPIC_OFF_LDR);807 AssertCompileMemberOffset(X2APICPAGE, svr, XAPIC_OFF_SVR);808 AssertCompileMemberOffset(X2APICPAGE, isr, XAPIC_OFF_ISR0);809 AssertCompileMemberOffset(X2APICPAGE, tmr, XAPIC_OFF_TMR0);810 AssertCompileMemberOffset(X2APICPAGE, irr, XAPIC_OFF_IRR0);811 AssertCompileMemberOffset(X2APICPAGE, esr, XAPIC_OFF_ESR);812 AssertCompileMemberOffset(X2APICPAGE, icr_lo, XAPIC_OFF_ICR_LO);813 AssertCompileMemberOffset(X2APICPAGE, icr_hi, XAPIC_OFF_ICR_HI);814 AssertCompileMemberOffset(X2APICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER);815 AssertCompileMemberOffset(X2APICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL);816 AssertCompileMemberOffset(X2APICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF);817 AssertCompileMemberOffset(X2APICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0);818 AssertCompileMemberOffset(X2APICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1);819 AssertCompileMemberOffset(X2APICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR);820 AssertCompileMemberOffset(X2APICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR);821 AssertCompileMemberOffset(X2APICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR);822 AssertCompileMemberOffset(X2APICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR);823 AssertCompileMemberOffset(X2APICPAGE, self_ipi, X2APIC_OFF_SELF_IPI);824 83 825 84 /** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */ … … 1012 271 1013 272 /** 273 * The xAPIC sparse 256-bit register. 274 */ 275 typedef union XAPIC256BITREG 276 { 277 /** The sparse-bitmap view. */ 278 struct 279 { 280 uint32_t u32Reg; 281 uint32_t uReserved0[3]; 282 } u[8]; 283 /** The 32-bit view. */ 284 uint32_t au32[32]; 285 } XAPIC256BITREG; 286 /** Pointer to an xAPIC sparse bitmap register. */ 287 typedef XAPIC256BITREG *PXAPIC256BITREG; 288 /** Pointer to a const xAPIC sparse bitmap register. */ 289 typedef XAPIC256BITREG const *PCXAPIC256BITREG; 290 AssertCompileSize(XAPIC256BITREG, 128); 291 292 /** 293 * The xAPIC memory layout as per Intel/AMD specs. 294 */ 295 typedef struct XAPICPAGE 296 { 297 /* 0x00 - Reserved. */ 298 uint32_t uReserved0[8]; 299 /* 0x20 - APIC ID. */ 300 struct 301 { 302 uint8_t u8Reserved0[3]; 303 uint8_t u8ApicId; 304 uint32_t u32Reserved0[3]; 305 } id; 306 /* 0x30 - APIC version register. */ 307 union 308 { 309 struct 310 { 311 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 312 uint8_t u8Version; 313 #else 314 # error "Implement Pentium and P6 family APIC architectures" 315 #endif 316 uint8_t uReserved0; 317 uint8_t u8MaxLvtEntry; 318 uint8_t fEoiBroadcastSupression : 1; 319 uint8_t u7Reserved1 : 7; 320 uint32_t u32Reserved0[3]; 321 } u; 322 struct 323 { 324 uint32_t u32Version; 325 uint32_t u32Reserved0[3]; 326 } all; 327 } version; 328 /* 0x40 - Reserved. */ 329 uint32_t uReserved1[16]; 330 /* 0x80 - Task Priority Register (TPR). */ 331 struct 332 { 333 uint8_t u8Tpr; 334 uint8_t u8Reserved0[3]; 335 uint32_t u32Reserved0[3]; 336 } tpr; 337 /* 0x90 - Arbitration Priority Register (APR). */ 338 struct 339 { 340 uint8_t u8Apr; 341 uint8_t u8Reserved0[3]; 342 uint32_t u32Reserved0[3]; 343 } apr; 344 /* 0xA0 - Processor Priority Register (PPR). */ 345 struct 346 { 347 uint8_t u8Ppr; 348 uint8_t u8Reserved0[3]; 349 uint32_t u32Reserved0[3]; 350 } ppr; 351 /* 0xB0 - End Of Interrupt Register (EOI). */ 352 struct 353 { 354 uint32_t u32Eoi; 355 uint32_t u32Reserved0[3]; 356 } eoi; 357 /* 0xC0 - Remote Read Register (RRD). */ 358 struct 359 { 360 uint32_t u32Rrd; 361 uint32_t u32Reserved0[3]; 362 } rrd; 363 /* 0xD0 - Logical Destination Register (LDR). */ 364 union 365 { 366 struct 367 { 368 uint8_t u8Reserved0[3]; 369 uint8_t u8LogicalApicId; 370 uint32_t u32Reserved0[3]; 371 } u; 372 struct 373 { 374 uint32_t u32Ldr; 375 uint32_t u32Reserved0[3]; 376 } all; 377 } ldr; 378 /* 0xE0 - Destination Format Register (DFR). */ 379 union 380 { 381 struct 382 { 383 uint32_t u28ReservedMb1 : 28; /* MB1 */ 384 uint32_t u4Model : 4; 385 uint32_t u32Reserved0[3]; 386 } u; 387 struct 388 { 389 uint32_t u32Dfr; 390 uint32_t u32Reserved0[3]; 391 } all; 392 } dfr; 393 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */ 394 union 395 { 396 struct 397 { 398 uint32_t u8SpuriousVector : 8; 399 uint32_t fApicSoftwareEnable : 1; 400 uint32_t u3Reserved0 : 3; 401 uint32_t fSupressEoiBroadcast : 1; 402 uint32_t u19Reserved1 : 19; 403 uint32_t u32Reserved0[3]; 404 } u; 405 struct 406 { 407 uint32_t u32Svr; 408 uint32_t u32Reserved0[3]; 409 } all; 410 } svr; 411 /* 0x100 - In-service Register (ISR). */ 412 XAPIC256BITREG isr; 413 /* 0x180 - Trigger Mode Register (TMR). */ 414 XAPIC256BITREG tmr; 415 /* 0x200 - Interrupt Request Register (IRR). */ 416 XAPIC256BITREG irr; 417 /* 0x280 - Error Status Register (ESR). */ 418 union 419 { 420 struct 421 { 422 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 423 uint32_t u4Reserved0 : 4; 424 #else 425 # error "Implement Pentium and P6 family APIC architectures" 426 #endif 427 uint32_t fRedirectableIpi : 1; 428 uint32_t fSendIllegalVector : 1; 429 uint32_t fRcvdIllegalVector : 1; 430 uint32_t fIllegalRegAddr : 1; 431 uint32_t u24Reserved1 : 24; 432 uint32_t u32Reserved0[3]; 433 } u; 434 struct 435 { 436 uint32_t u32Errors; 437 uint32_t u32Reserved0[3]; 438 } all; 439 } esr; 440 /* 0x290 - Reserved. */ 441 uint32_t uReserved2[28]; 442 /* 0x300 - Interrupt Command Register (ICR) - Low. */ 443 union 444 { 445 struct 446 { 447 uint32_t u8Vector : 8; 448 uint32_t u3DeliveryMode : 3; 449 uint32_t u1DestMode : 1; 450 uint32_t u1DeliveryStatus : 1; 451 uint32_t fReserved0 : 1; 452 uint32_t u1Level : 1; 453 uint32_t u1TriggerMode : 1; 454 uint32_t u2Reserved1 : 2; 455 uint32_t u2DestShorthand : 2; 456 uint32_t u12Reserved2 : 12; 457 uint32_t u32Reserved0[3]; 458 } u; 459 struct 460 { 461 uint32_t u32IcrLo; 462 uint32_t u32Reserved0[3]; 463 } all; 464 } icr_lo; 465 /* 0x310 - Interrupt Comannd Register (ICR) - High. */ 466 union 467 { 468 struct 469 { 470 uint32_t u24Reserved0 : 24; 471 uint32_t u8Dest : 8; 472 uint32_t u32Reserved0[3]; 473 } u; 474 struct 475 { 476 uint32_t u32IcrHi; 477 uint32_t u32Reserved0[3]; 478 } all; 479 } icr_hi; 480 /* 0x320 - Local Vector Table (LVT) Timer Register. */ 481 union 482 { 483 struct 484 { 485 uint32_t u8Vector : 8; 486 uint32_t u4Reserved0 : 4; 487 uint32_t u1DeliveryStatus : 1; 488 uint32_t u3Reserved1 : 3; 489 uint32_t u1Mask : 1; 490 uint32_t u2TimerMode : 2; 491 uint32_t u13Reserved2 : 13; 492 uint32_t u32Reserved0[3]; 493 } u; 494 struct 495 { 496 uint32_t u32LvtTimer; 497 uint32_t u32Reserved0[3]; 498 } all; 499 } lvt_timer; 500 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */ 501 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 502 union 503 { 504 struct 505 { 506 uint32_t u8Vector : 8; 507 uint32_t u3DeliveryMode : 3; 508 uint32_t u1Reserved0 : 1; 509 uint32_t u1DeliveryStatus : 1; 510 uint32_t u3Reserved1 : 3; 511 uint32_t u1Mask : 1; 512 uint32_t u15Reserved2 : 15; 513 uint32_t u32Reserved0[3]; 514 } u; 515 struct 516 { 517 uint32_t u32LvtThermal; 518 uint32_t u32Reserved0[3]; 519 } all; 520 } lvt_thermal; 521 #else 522 # error "Implement Pentium and P6 family APIC architectures" 523 #endif 524 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */ 525 union 526 { 527 struct 528 { 529 uint32_t u8Vector : 8; 530 uint32_t u3DeliveryMode : 3; 531 uint32_t u1Reserved0 : 1; 532 uint32_t u1DeliveryStatus : 1; 533 uint32_t u3Reserved1 : 3; 534 uint32_t u1Mask : 1; 535 uint32_t u15Reserved2 : 15; 536 uint32_t u32Reserved0[3]; 537 } u; 538 struct 539 { 540 uint32_t u32LvtPerf; 541 uint32_t u32Reserved0[3]; 542 } all; 543 } lvt_perf; 544 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */ 545 union 546 { 547 struct 548 { 549 uint32_t u8Vector : 8; 550 uint32_t u3DeliveryMode : 3; 551 uint32_t u1Reserved0 : 1; 552 uint32_t u1DeliveryStatus : 1; 553 uint32_t u1IntrPolarity : 1; 554 uint32_t u1RemoteIrr : 1; 555 uint32_t u1TriggerMode : 1; 556 uint32_t u1Mask : 1; 557 uint32_t u15Reserved2 : 15; 558 uint32_t u32Reserved0[3]; 559 } u; 560 struct 561 { 562 uint32_t u32LvtLint0; 563 uint32_t u32Reserved0[3]; 564 } all; 565 } lvt_lint0; 566 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */ 567 union 568 { 569 struct 570 { 571 uint32_t u8Vector : 8; 572 uint32_t u3DeliveryMode : 3; 573 uint32_t u1Reserved0 : 1; 574 uint32_t u1DeliveryStatus : 1; 575 uint32_t u1IntrPolarity : 1; 576 uint32_t u1RemoteIrr : 1; 577 uint32_t u1TriggerMode : 1; 578 uint32_t u1Mask : 1; 579 uint32_t u15Reserved2 : 15; 580 uint32_t u32Reserved0[3]; 581 } u; 582 struct 583 { 584 uint32_t u32LvtLint1; 585 uint32_t u32Reserved0[3]; 586 } all; 587 } lvt_lint1; 588 /* 0x370 - Local Vector Table (LVT) Error Register. */ 589 union 590 { 591 struct 592 { 593 uint32_t u8Vector : 8; 594 uint32_t u4Reserved0 : 4; 595 uint32_t u1DeliveryStatus : 1; 596 uint32_t u3Reserved1 : 3; 597 uint32_t u1Mask : 1; 598 uint32_t u15Reserved2 : 15; 599 uint32_t u32Reserved0[3]; 600 } u; 601 struct 602 { 603 uint32_t u32LvtError; 604 uint32_t u32Reserved0[3]; 605 } all; 606 } lvt_error; 607 /* 0x380 - Timer Initial Counter Register. */ 608 struct 609 { 610 uint32_t u32InitialCount; 611 uint32_t u32Reserved0[3]; 612 } timer_icr; 613 /* 0x390 - Timer Current Counter Register. */ 614 struct 615 { 616 uint32_t u32CurrentCount; 617 uint32_t u32Reserved0[3]; 618 } timer_ccr; 619 /* 0x3A0 - Reserved. */ 620 uint32_t u32Reserved3[16]; 621 /* 0x3E0 - Timer Divide Configuration Register. */ 622 union 623 { 624 struct 625 { 626 uint32_t u2DivideValue0 : 2; 627 uint32_t u1Reserved0 : 1; 628 uint32_t u1DivideValue1 : 1; 629 uint32_t u28Reserved1 : 28; 630 uint32_t u32Reserved0[3]; 631 } u; 632 struct 633 { 634 uint32_t u32DivideValue; 635 uint32_t u32Reserved0[3]; 636 } all; 637 } timer_dcr; 638 /* 0x3F0 - Reserved. */ 639 uint8_t u8Reserved0[3088]; 640 } XAPICPAGE; 641 /** Pointer to a XAPICPAGE struct. */ 642 typedef XAPICPAGE *PXAPICPAGE; 643 /** Pointer to a const XAPICPAGE struct. */ 644 typedef const XAPICPAGE *PCXAPICPAGE; 645 AssertCompileSize(XAPICPAGE, 4096); 646 AssertCompileMemberOffset(XAPICPAGE, id, XAPIC_OFF_ID); 647 AssertCompileMemberOffset(XAPICPAGE, version, XAPIC_OFF_VERSION); 648 AssertCompileMemberOffset(XAPICPAGE, tpr, XAPIC_OFF_TPR); 649 AssertCompileMemberOffset(XAPICPAGE, apr, XAPIC_OFF_APR); 650 AssertCompileMemberOffset(XAPICPAGE, ppr, XAPIC_OFF_PPR); 651 AssertCompileMemberOffset(XAPICPAGE, eoi, XAPIC_OFF_EOI); 652 AssertCompileMemberOffset(XAPICPAGE, rrd, XAPIC_OFF_RRD); 653 AssertCompileMemberOffset(XAPICPAGE, ldr, XAPIC_OFF_LDR); 654 AssertCompileMemberOffset(XAPICPAGE, dfr, XAPIC_OFF_DFR); 655 AssertCompileMemberOffset(XAPICPAGE, svr, XAPIC_OFF_SVR); 656 AssertCompileMemberOffset(XAPICPAGE, isr, XAPIC_OFF_ISR0); 657 AssertCompileMemberOffset(XAPICPAGE, tmr, XAPIC_OFF_TMR0); 658 AssertCompileMemberOffset(XAPICPAGE, irr, XAPIC_OFF_IRR0); 659 AssertCompileMemberOffset(XAPICPAGE, esr, XAPIC_OFF_ESR); 660 AssertCompileMemberOffset(XAPICPAGE, icr_lo, XAPIC_OFF_ICR_LO); 661 AssertCompileMemberOffset(XAPICPAGE, icr_hi, XAPIC_OFF_ICR_HI); 662 AssertCompileMemberOffset(XAPICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER); 663 AssertCompileMemberOffset(XAPICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL); 664 AssertCompileMemberOffset(XAPICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF); 665 AssertCompileMemberOffset(XAPICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0); 666 AssertCompileMemberOffset(XAPICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1); 667 AssertCompileMemberOffset(XAPICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR); 668 AssertCompileMemberOffset(XAPICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR); 669 AssertCompileMemberOffset(XAPICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR); 670 AssertCompileMemberOffset(XAPICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR); 671 672 /** 673 * The x2APIC memory layout as per Intel/AMD specs. 674 */ 675 typedef struct X2APICPAGE 676 { 677 /* 0x00 - Reserved. */ 678 uint32_t uReserved0[8]; 679 /* 0x20 - APIC ID. */ 680 struct 681 { 682 uint32_t u32ApicId; 683 uint32_t u32Reserved0[3]; 684 } id; 685 /* 0x30 - APIC version register. */ 686 union 687 { 688 struct 689 { 690 uint8_t u8Version; 691 uint8_t u8Reserved0; 692 uint8_t u8MaxLvtEntry; 693 uint8_t fEoiBroadcastSupression : 1; 694 uint8_t u7Reserved1 : 7; 695 uint32_t u32Reserved0[3]; 696 } u; 697 struct 698 { 699 uint32_t u32Version; 700 uint32_t u32Reserved2[3]; 701 } all; 702 } version; 703 /* 0x40 - Reserved. */ 704 uint32_t uReserved1[16]; 705 /* 0x80 - Task Priority Register (TPR). */ 706 struct 707 { 708 uint8_t u8Tpr; 709 uint8_t u8Reserved0[3]; 710 uint32_t u32Reserved0[3]; 711 } tpr; 712 /* 0x90 - Reserved. */ 713 uint32_t uReserved2[4]; 714 /* 0xA0 - Processor Priority Register (PPR). */ 715 struct 716 { 717 uint8_t u8Ppr; 718 uint8_t u8Reserved0[3]; 719 uint32_t u32Reserved0[3]; 720 } ppr; 721 /* 0xB0 - End Of Interrupt Register (EOI). */ 722 struct 723 { 724 uint32_t u32Eoi; 725 uint32_t u32Reserved0[3]; 726 } eoi; 727 /* 0xC0 - Remote Read Register (RRD). */ 728 struct 729 { 730 uint32_t u32Rrd; 731 uint32_t u32Reserved0[3]; 732 } rrd; 733 /* 0xD0 - Logical Destination Register (LDR). */ 734 struct 735 { 736 uint32_t u32LogicalApicId; 737 uint32_t u32Reserved1[3]; 738 } ldr; 739 /* 0xE0 - Reserved. */ 740 uint32_t uReserved3[4]; 741 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */ 742 union 743 { 744 struct 745 { 746 uint32_t u8SpuriousVector : 8; 747 uint32_t fApicSoftwareEnable : 1; 748 uint32_t u3Reserved0 : 3; 749 uint32_t fSupressEoiBroadcast : 1; 750 uint32_t u19Reserved1 : 19; 751 uint32_t u32Reserved0[3]; 752 } u; 753 struct 754 { 755 uint32_t u32Svr; 756 uint32_t uReserved0[3]; 757 } all; 758 } svr; 759 /* 0x100 - In-service Register (ISR). */ 760 XAPIC256BITREG isr; 761 /* 0x180 - Trigger Mode Register (TMR). */ 762 XAPIC256BITREG tmr; 763 /* 0x200 - Interrupt Request Register (IRR). */ 764 XAPIC256BITREG irr; 765 /* 0x280 - Error Status Register (ESR). */ 766 union 767 { 768 struct 769 { 770 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 771 uint32_t u4Reserved0 : 4; 772 #else 773 # error "Implement Pentium and P6 family APIC architectures" 774 #endif 775 uint32_t fRedirectableIpi : 1; 776 uint32_t fSendIllegalVector : 1; 777 uint32_t fRcvdIllegalVector : 1; 778 uint32_t fIllegalRegAddr : 1; 779 uint32_t u24Reserved1 : 24; 780 uint32_t uReserved0[3]; 781 } u; 782 struct 783 { 784 uint32_t u32Errors; 785 uint32_t u32Reserved0[3]; 786 } all; 787 } esr; 788 /* 0x290 - Reserved. */ 789 uint32_t uReserved4[28]; 790 /* 0x300 - Interrupt Command Register (ICR) - Low. */ 791 union 792 { 793 struct 794 { 795 uint32_t u8Vector : 8; 796 uint32_t u3DeliveryMode : 3; 797 uint32_t u1DestMode : 1; 798 uint32_t u2Reserved0 : 2; 799 uint32_t u1Level : 1; 800 uint32_t u1TriggerMode : 1; 801 uint32_t u2Reserved1 : 2; 802 uint32_t u2DestShorthand : 2; 803 uint32_t u12Reserved2 : 12; 804 uint32_t u32Reserved0[3]; 805 } u; 806 struct 807 { 808 uint32_t u32IcrLo; 809 uint32_t u32Reserved3[3]; 810 } all; 811 } icr_lo; 812 /* 0x310 - Interrupt Comannd Register (ICR) - High. */ 813 struct 814 { 815 uint32_t u32IcrHi; 816 uint32_t uReserved1[3]; 817 } icr_hi; 818 /* 0x320 - Local Vector Table (LVT) Timer Register. */ 819 union 820 { 821 struct 822 { 823 uint32_t u8Vector : 8; 824 uint32_t u4Reserved0 : 4; 825 uint32_t u1DeliveryStatus : 1; 826 uint32_t u3Reserved1 : 3; 827 uint32_t u1Mask : 1; 828 uint32_t u2TimerMode : 2; 829 uint32_t u13Reserved2 : 13; 830 uint32_t u32Reserved0[3]; 831 } u; 832 struct 833 { 834 uint32_t u32LvtTimer; 835 uint32_t u32Reserved0[3]; 836 } all; 837 } lvt_timer; 838 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */ 839 union 840 { 841 struct 842 { 843 uint32_t u8Vector : 8; 844 uint32_t u3DeliveryMode : 3; 845 uint32_t u1Reserved0 : 1; 846 uint32_t u1DeliveryStatus : 1; 847 uint32_t u3Reserved1 : 3; 848 uint32_t u1Mask : 1; 849 uint32_t u15Reserved2 : 15; 850 uint32_t u32Reserved0[3]; 851 } u; 852 struct 853 { 854 uint32_t u32LvtThermal; 855 uint32_t uReserved0[3]; 856 } all; 857 } lvt_thermal; 858 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */ 859 union 860 { 861 struct 862 { 863 uint32_t u8Vector : 8; 864 uint32_t u3DeliveryMode : 3; 865 uint32_t u1Reserved0 : 1; 866 uint32_t u1DeliveryStatus : 1; 867 uint32_t u3Reserved1 : 3; 868 uint32_t u1Mask : 1; 869 uint32_t u15Reserved2 : 15; 870 uint32_t u32Reserved0[3]; 871 } u; 872 struct 873 { 874 uint32_t u32LvtPerf; 875 uint32_t u32Reserved0[3]; 876 } all; 877 } lvt_perf; 878 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */ 879 union 880 { 881 struct 882 { 883 uint32_t u8Vector : 8; 884 uint32_t u3DeliveryMode : 3; 885 uint32_t u1Reserved0 : 1; 886 uint32_t u1DeliveryStatus : 1; 887 uint32_t u1IntrPolarity : 1; 888 uint32_t u1RemoteIrr : 1; 889 uint32_t u1TriggerMode : 1; 890 uint32_t u1Mask : 1; 891 uint32_t u15Reserved2 : 15; 892 uint32_t u32Reserved0[3]; 893 } u; 894 struct 895 { 896 uint32_t u32LvtLint0; 897 uint32_t u32Reserved0[3]; 898 } all; 899 } lvt_lint0; 900 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */ 901 union 902 { 903 struct 904 { 905 uint32_t u8Vector : 8; 906 uint32_t u3DeliveryMode : 3; 907 uint32_t u1Reserved0 : 1; 908 uint32_t u1DeliveryStatus : 1; 909 uint32_t u1IntrPolarity : 1; 910 uint32_t u1RemoteIrr : 1; 911 uint32_t u1TriggerMode : 1; 912 uint32_t u1Mask : 1; 913 uint32_t u15Reserved2 : 15; 914 uint32_t u32Reserved0[3]; 915 } u; 916 struct 917 { 918 uint32_t u32LvtLint1; 919 uint32_t u32Reserved0[3]; 920 } all; 921 } lvt_lint1; 922 /* 0x370 - Local Vector Table (LVT) Error Register. */ 923 union 924 { 925 struct 926 { 927 uint32_t u8Vector : 8; 928 uint32_t u4Reserved0 : 4; 929 uint32_t u1DeliveryStatus : 1; 930 uint32_t u3Reserved1 : 3; 931 uint32_t u1Mask : 1; 932 uint32_t u15Reserved2 : 15; 933 uint32_t u32Reserved0[3]; 934 } u; 935 struct 936 { 937 uint32_t u32LvtError; 938 uint32_t u32Reserved0[3]; 939 } all; 940 } lvt_error; 941 /* 0x380 - Timer Initial Counter Register. */ 942 struct 943 { 944 uint32_t u32InitialCount; 945 uint32_t u32Reserved0[3]; 946 } timer_icr; 947 /* 0x390 - Timer Current Counter Register. */ 948 struct 949 { 950 uint32_t u32CurrentCount; 951 uint32_t u32Reserved0[3]; 952 } timer_ccr; 953 /* 0x3A0 - Reserved. */ 954 uint32_t uReserved5[16]; 955 /* 0x3E0 - Timer Divide Configuration Register. */ 956 union 957 { 958 struct 959 { 960 uint32_t u2DivideValue0 : 2; 961 uint32_t u1Reserved0 : 1; 962 uint32_t u1DivideValue1 : 1; 963 uint32_t u28Reserved1 : 28; 964 uint32_t u32Reserved0[3]; 965 } u; 966 struct 967 { 968 uint32_t u32DivideValue; 969 uint32_t u32Reserved0[3]; 970 } all; 971 } timer_dcr; 972 /* 0x3F0 - Self IPI Register. */ 973 struct 974 { 975 uint32_t u8Vector : 8; 976 uint32_t u24Reserved0 : 24; 977 uint32_t u32Reserved0[3]; 978 } self_ipi; 979 /* 0x400 - Reserved. */ 980 uint8_t u8Reserved0[3072]; 981 } X2APICPAGE; 982 /** Pointer to a X2APICPAGE struct. */ 983 typedef X2APICPAGE *PX2APICPAGE; 984 /** Pointer to a const X2APICPAGE struct. */ 985 typedef const X2APICPAGE *PCX2APICPAGE; 986 AssertCompileSize(X2APICPAGE, 4096); 987 AssertCompileSize(X2APICPAGE, sizeof(XAPICPAGE)); 988 AssertCompileMemberOffset(X2APICPAGE, id, XAPIC_OFF_ID); 989 AssertCompileMemberOffset(X2APICPAGE, version, XAPIC_OFF_VERSION); 990 AssertCompileMemberOffset(X2APICPAGE, tpr, XAPIC_OFF_TPR); 991 AssertCompileMemberOffset(X2APICPAGE, ppr, XAPIC_OFF_PPR); 992 AssertCompileMemberOffset(X2APICPAGE, eoi, XAPIC_OFF_EOI); 993 AssertCompileMemberOffset(X2APICPAGE, rrd, XAPIC_OFF_RRD); 994 AssertCompileMemberOffset(X2APICPAGE, ldr, XAPIC_OFF_LDR); 995 AssertCompileMemberOffset(X2APICPAGE, svr, XAPIC_OFF_SVR); 996 AssertCompileMemberOffset(X2APICPAGE, isr, XAPIC_OFF_ISR0); 997 AssertCompileMemberOffset(X2APICPAGE, tmr, XAPIC_OFF_TMR0); 998 AssertCompileMemberOffset(X2APICPAGE, irr, XAPIC_OFF_IRR0); 999 AssertCompileMemberOffset(X2APICPAGE, esr, XAPIC_OFF_ESR); 1000 AssertCompileMemberOffset(X2APICPAGE, icr_lo, XAPIC_OFF_ICR_LO); 1001 AssertCompileMemberOffset(X2APICPAGE, icr_hi, XAPIC_OFF_ICR_HI); 1002 AssertCompileMemberOffset(X2APICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER); 1003 AssertCompileMemberOffset(X2APICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL); 1004 AssertCompileMemberOffset(X2APICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF); 1005 AssertCompileMemberOffset(X2APICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0); 1006 AssertCompileMemberOffset(X2APICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1); 1007 AssertCompileMemberOffset(X2APICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR); 1008 AssertCompileMemberOffset(X2APICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR); 1009 AssertCompileMemberOffset(X2APICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR); 1010 AssertCompileMemberOffset(X2APICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR); 1011 AssertCompileMemberOffset(X2APICPAGE, self_ipi, X2APIC_OFF_SELF_IPI); 1012 1013 /** 1014 1014 * APIC MSR access error. 1015 1015 * @note The values must match the array indices in apicMsrAccessError().
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