VirtualBox

Changeset 61072 in vbox for trunk


Ignore:
Timestamp:
May 20, 2016 2:59:40 AM (8 years ago)
Author:
vboxsync
Message:

VMM/APIC: Get rid of a couple of duplicate macros, and added a couple of ones to x86.h.

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/VBox/vmm/apic.h

    r61044 r61072  
    3434 * @{
    3535 */
    36 
    37 /** Gets the APIC base physical address. */
    38 #define MSR_APICBASE_GET_PHYSADDR(a)         ((a) & PAGE_BASE_GC_MASK)
    39 /** Gets the APIC mode. */
    40 #define MSR_APICBASE_GET_MODE(a)             (((a) >> 10) & UINT64_C(3))
    41 /** The APIC global enable bit. */
    42 /** @todo r=bird: Please do   N O T  use _BIT for what clearly are masks!
    43  *  See x86.h and vm.h for examples of how we use _BIT elsewhere!
    44  * Besides, you are duplicating existing x86.h defines here
    45  * (MSR_IA32_APICBASE_XXX). */
    46 #define MSR_APICBASE_XAPIC_ENABLE_BIT        RT_BIT_64(11)
    47 /** The x2APIC global enable bit. */
    48 #define MSR_APICBASE_X2APIC_ENABLE_BIT       RT_BIT_64(10)
    49 /** The APIC bootstrap processor bit. */
    50 #define MSR_APICBASE_BOOTSTRAP_CPU_BIT       RT_BIT_64(8)
    51 /** The default APIC base address. */
    52 #define XAPIC_APICBASE_PHYSADDR              UINT64_C(0xfee00000)
    53 /** The APIC base MSR - Is the APIC enabled?  */
    54 #define MSR_APICBASE_IS_ENABLED(a_Msr)       RT_BOOL((a_Msr) & MSR_APICBASE_XAPIC_ENABLE_BIT)
    5536
    5637/** Offset of APIC ID Register. */
  • trunk/include/iprt/x86.h

    r60996 r61072  
    10581058 *  width. */
    10591059# define MSR_IA32_APICBASE_BASE_MIN         UINT64_C(0x0000000ffffff000)
     1060/** The default physical base address of the APIC. */
     1061# define MSR_IA32_APICBASE_ADDR             UINT64_C(0x00000000fee00000)
     1062/** Gets the physical base address from the MSR. */
     1063# define MSR_IA32_APICBASE_GET_ADDR(a_Msr)  ((a_Msr) & X86_PAGE_4K_BASE_MASK)
    10601064#endif
    10611065
     
    14881492/** The default page offset mask. */
    14891493#define X86_PAGE_OFFSET_MASK                X86_PAGE_4K_OFFSET_MASK
    1490 /** The defaultpage base mask for virtual addresses. */
     1494/** The default page base mask for virtual addresses. */
    14911495#define X86_PAGE_BASE_MASK                  X86_PAGE_4K_BASE_MASK
    14921496/** The default page base mask for virtual addresses - 32bit version. */
  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r61041 r61072  
    376376APICMODE apicGetMode(uint64_t uApicBaseMsr)
    377377{
    378     uint32_t const uMode   = MSR_APICBASE_GET_MODE(uApicBaseMsr);
     378    uint32_t const uMode   = (uApicBaseMsr >> 10) & UINT64_C(3);
    379379    APICMODE const enmMode = (APICMODE)uMode;
    380380#ifdef VBOX_STRICT
     
    403403{
    404404    PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    405     return MSR_APICBASE_IS_ENABLED(pApicCpu->uApicBaseMsr);
     405    return pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN;
    406406}
    407407
     
    19961996     */
    19971997    /** @todo Handle per-VCPU APIC base relocation. */
    1998     if (MSR_APICBASE_GET_PHYSADDR(uBaseMsr) != XAPIC_APICBASE_PHYSADDR)
     1998    if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR)
    19991999    {
    20002000        LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu,
    2001                       MSR_APICBASE_GET_PHYSADDR(uBaseMsr)));
     2001                      MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)));
    20022002        return VERR_CPUM_RAISE_GP_0;
    20032003    }
     
    20332033                 */
    20342034                APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
    2035                 uBaseMsr &= ~(MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT);
     2035                uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
    20362036                CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
    20372037                LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
     
    20472047                }
    20482048
    2049                 uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
     2049                uBaseMsr |= MSR_IA32_APICBASE_EN;
    20502050                CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
    20512051                LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
     
    20612061                }
    20622062
    2063                 /* Don't allow enabling x2APIC if the VM is configured with the APIC disabled. */
    2064                 uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT;
     2063                uBaseMsr |= MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD;
    20652064
    20662065                /*
  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r61041 r61072  
    236236    PAPICCPU pApicCpu     = VMCPU_TO_APICCPU(pVCpu);
    237237    PAPIC    pApic        = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    238     uint64_t uApicBaseMsr = XAPIC_APICBASE_PHYSADDR;
     238    uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;;
    239239    if (pVCpu->idCpu == 0)
    240         uApicBaseMsr |= MSR_APICBASE_BOOTSTRAP_CPU_BIT;
     240        uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
    241241
    242242    /* If the VM was configured with disabled mode, don't enable xAPIC mode. */
    243243    if (pApic->enmOriginalMode != APICMODE_DISABLED)
    244244    {
    245         uApicBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
     245        uApicBaseMsr |= MSR_IA32_APICBASE_EN;
    246246
    247247        /** @todo CPUID bits needs to be done on a per-VCPU basis! */
     
    415415    pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC:\n", pVCpu->idCpu);
    416416    pHlp->pfnPrintf(pHlp, "  APIC Base MSR                 = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
    417                     MSR_APICBASE_GET_PHYSADDR(uBaseMsr));
     417                    MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
    418418    pHlp->pfnPrintf(pHlp, "  Mode                          = %#x (%s)\n", enmMode, apicGetModeName(enmMode));
    419419    if (fX2ApicMode)
     
    15861586     */
    15871587    PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
    1588     RTGCPHYS GCPhysApicBase = MSR_APICBASE_GET_PHYSADDR(pApicCpu0->uApicBaseMsr);
     1588    RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
    15891589
    15901590    rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
  • trunk/src/VBox/VMM/include/APICInternal.h

    r61045 r61072  
    4747/** Whether the APIC is in X2APIC mode or not. */
    4848#define XAPIC_IN_X2APIC_MODE(a_pVCpu)        (   (  ((a_pVCpu)->apic.s.uApicBaseMsr) \
    49                                                   & (MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT)) \
    50                                               ==    (MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT) )
     49                                                  & (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD)) \
     50                                              ==    (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD) )
    5151/** Get an xAPIC page offset for an x2APIC MSR value. */
    5252#define X2APIC_GET_XAPIC_OFF(a_uMsr)         ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette