- Timestamp:
- May 20, 2016 2:59:40 AM (8 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
-
include/VBox/vmm/apic.h (modified) (1 diff)
-
include/iprt/x86.h (modified) (2 diffs)
-
src/VBox/VMM/VMMAll/APICAll.cpp (modified) (6 diffs)
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src/VBox/VMM/VMMR3/APIC.cpp (modified) (3 diffs)
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src/VBox/VMM/include/APICInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/apic.h
r61044 r61072 34 34 * @{ 35 35 */ 36 37 /** Gets the APIC base physical address. */38 #define MSR_APICBASE_GET_PHYSADDR(a) ((a) & PAGE_BASE_GC_MASK)39 /** Gets the APIC mode. */40 #define MSR_APICBASE_GET_MODE(a) (((a) >> 10) & UINT64_C(3))41 /** The APIC global enable bit. */42 /** @todo r=bird: Please do N O T use _BIT for what clearly are masks!43 * See x86.h and vm.h for examples of how we use _BIT elsewhere!44 * Besides, you are duplicating existing x86.h defines here45 * (MSR_IA32_APICBASE_XXX). */46 #define MSR_APICBASE_XAPIC_ENABLE_BIT RT_BIT_64(11)47 /** The x2APIC global enable bit. */48 #define MSR_APICBASE_X2APIC_ENABLE_BIT RT_BIT_64(10)49 /** The APIC bootstrap processor bit. */50 #define MSR_APICBASE_BOOTSTRAP_CPU_BIT RT_BIT_64(8)51 /** The default APIC base address. */52 #define XAPIC_APICBASE_PHYSADDR UINT64_C(0xfee00000)53 /** The APIC base MSR - Is the APIC enabled? */54 #define MSR_APICBASE_IS_ENABLED(a_Msr) RT_BOOL((a_Msr) & MSR_APICBASE_XAPIC_ENABLE_BIT)55 36 56 37 /** Offset of APIC ID Register. */ -
trunk/include/iprt/x86.h
r60996 r61072 1058 1058 * width. */ 1059 1059 # define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000) 1060 /** The default physical base address of the APIC. */ 1061 # define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000) 1062 /** Gets the physical base address from the MSR. */ 1063 # define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK) 1060 1064 #endif 1061 1065 … … 1488 1492 /** The default page offset mask. */ 1489 1493 #define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK 1490 /** The default page base mask for virtual addresses. */1494 /** The default page base mask for virtual addresses. */ 1491 1495 #define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK 1492 1496 /** The default page base mask for virtual addresses - 32bit version. */ -
trunk/src/VBox/VMM/VMMAll/APICAll.cpp
r61041 r61072 376 376 APICMODE apicGetMode(uint64_t uApicBaseMsr) 377 377 { 378 uint32_t const uMode = MSR_APICBASE_GET_MODE(uApicBaseMsr);378 uint32_t const uMode = (uApicBaseMsr >> 10) & UINT64_C(3); 379 379 APICMODE const enmMode = (APICMODE)uMode; 380 380 #ifdef VBOX_STRICT … … 403 403 { 404 404 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); 405 return MSR_APICBASE_IS_ENABLED(pApicCpu->uApicBaseMsr);405 return pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN; 406 406 } 407 407 … … 1996 1996 */ 1997 1997 /** @todo Handle per-VCPU APIC base relocation. */ 1998 if (MSR_ APICBASE_GET_PHYSADDR(uBaseMsr) != XAPIC_APICBASE_PHYSADDR)1998 if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR) 1999 1999 { 2000 2000 LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu, 2001 MSR_ APICBASE_GET_PHYSADDR(uBaseMsr)));2001 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr))); 2002 2002 return VERR_CPUM_RAISE_GP_0; 2003 2003 } … … 2033 2033 */ 2034 2034 APICR3Reset(pVCpu, false /* fResetApicBaseMsr */); 2035 uBaseMsr &= ~(MSR_ APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT);2035 uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD); 2036 2036 CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC); 2037 2037 LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu)); … … 2047 2047 } 2048 2048 2049 uBaseMsr |= MSR_ APICBASE_XAPIC_ENABLE_BIT;2049 uBaseMsr |= MSR_IA32_APICBASE_EN; 2050 2050 CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC); 2051 2051 LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu)); … … 2061 2061 } 2062 2062 2063 /* Don't allow enabling x2APIC if the VM is configured with the APIC disabled. */ 2064 uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT; 2063 uBaseMsr |= MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD; 2065 2064 2066 2065 /* -
trunk/src/VBox/VMM/VMMR3/APIC.cpp
r61041 r61072 236 236 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); 237 237 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM)); 238 uint64_t uApicBaseMsr = XAPIC_APICBASE_PHYSADDR;238 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;; 239 239 if (pVCpu->idCpu == 0) 240 uApicBaseMsr |= MSR_ APICBASE_BOOTSTRAP_CPU_BIT;240 uApicBaseMsr |= MSR_IA32_APICBASE_BSP; 241 241 242 242 /* If the VM was configured with disabled mode, don't enable xAPIC mode. */ 243 243 if (pApic->enmOriginalMode != APICMODE_DISABLED) 244 244 { 245 uApicBaseMsr |= MSR_ APICBASE_XAPIC_ENABLE_BIT;245 uApicBaseMsr |= MSR_IA32_APICBASE_EN; 246 246 247 247 /** @todo CPUID bits needs to be done on a per-VCPU basis! */ … … 415 415 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC:\n", pVCpu->idCpu); 416 416 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr, 417 MSR_ APICBASE_GET_PHYSADDR(uBaseMsr));417 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)); 418 418 pHlp->pfnPrintf(pHlp, " Mode = %#x (%s)\n", enmMode, apicGetModeName(enmMode)); 419 419 if (fX2ApicMode) … … 1586 1586 */ 1587 1587 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]); 1588 RTGCPHYS GCPhysApicBase = MSR_ APICBASE_GET_PHYSADDR(pApicCpu0->uApicBaseMsr);1588 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr); 1589 1589 1590 1590 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */, -
trunk/src/VBox/VMM/include/APICInternal.h
r61045 r61072 47 47 /** Whether the APIC is in X2APIC mode or not. */ 48 48 #define XAPIC_IN_X2APIC_MODE(a_pVCpu) ( ( ((a_pVCpu)->apic.s.uApicBaseMsr) \ 49 & (MSR_ APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT)) \50 == (MSR_ APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT) )49 & (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD)) \ 50 == (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD) ) 51 51 /** Get an xAPIC page offset for an x2APIC MSR value. */ 52 52 #define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))
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