- Timestamp:
- May 19, 2016 10:20:40 PM (8 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
-
VMMAll/IEMAll.cpp (modified) (11 diffs)
-
VMMAll/IEMAllInstructions.cpp.h (modified) (161 diffs)
-
testcase/tstIEMCheckMc.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r61015 r61064 5231 5231 * Hook for preparing to use the host FPU. 5232 5232 * 5233 * This is necessary in ring-0 and raw-mode context .5233 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5234 5234 * 5235 5235 * @param pIemCpu The IEM per CPU data. 5236 5236 */ 5237 5237 DECLINLINE(void) iemFpuPrepareUsage(PIEMCPU pIemCpu) 5238 { 5239 #ifdef IN_RING3 5240 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM); 5241 #else 5242 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM); 5243 /** @todo RZ: FIXME */ 5244 //# error "Implement me" 5245 #endif 5246 } 5247 5248 5249 /** 5250 * Hook for preparing to use the host FPU for SSE 5251 * 5252 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5253 * 5254 * @param pIemCpu The IEM per CPU data. 5255 */ 5256 DECLINLINE(void) iemFpuPrepareUsageSse(PIEMCPU pIemCpu) 5257 { 5258 iemFpuPrepareUsage(pIemCpu); 5259 } 5260 5261 5262 /** 5263 * Hook for actualizing the guest FPU state before the interpreter reads it. 5264 * 5265 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5266 * 5267 * @param pIemCpu The IEM per CPU data. 5268 */ 5269 DECLINLINE(void) iemFpuActualizeStateForRead(PIEMCPU pIemCpu) 5238 5270 { 5239 5271 #ifdef IN_RING3 … … 5247 5279 5248 5280 /** 5249 * Hook for preparing to use the host FPU for SSE5250 * 5251 * This is necessary in ring-0 and raw-mode context .5281 * Hook for actualizing the guest FPU state before the interpreter changes it. 5282 * 5283 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5252 5284 * 5253 5285 * @param pIemCpu The IEM per CPU data. 5254 5286 */ 5255 DECLINLINE(void) iemFpuPrepareUsageSse(PIEMCPU pIemCpu) 5256 { 5287 DECLINLINE(void) iemFpuActualizeStateForChange(PIEMCPU pIemCpu) 5288 { 5289 #ifdef IN_RING3 5290 NOREF(pIemCpu); 5291 #else 5292 //CPUMRZFpuActualizeForChange(IEMCPU_TO_VMCPU(pIemCpu)); 5257 5293 iemFpuPrepareUsage(pIemCpu); 5294 #endif 5295 } 5296 5297 5298 /** 5299 * Hook for actualizing the guest XMM0..15 register state for read only. 5300 * 5301 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5302 * 5303 * @param pIemCpu The IEM per CPU data. 5304 */ 5305 DECLINLINE(void) iemFpuActualizeSseStateForRead(PIEMCPU pIemCpu) 5306 { 5307 #if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM) 5308 NOREF(pIemCpu); 5309 #else 5310 iemFpuActualizeStateForRead(pIemCpu); 5311 #endif 5312 } 5313 5314 5315 /** 5316 * Hook for actualizing the guest XMM0..15 register state for read+write. 5317 * 5318 * This is necessary in ring-0 and raw-mode context (nop in ring-3). 5319 * 5320 * @param pIemCpu The IEM per CPU data. 5321 */ 5322 DECLINLINE(void) iemFpuActualizeSseStateForChange(PIEMCPU pIemCpu) 5323 { 5324 #if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM) 5325 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM); 5326 #else 5327 iemFpuActualizeStateForChange(pIemCpu); 5328 #endif 5258 5329 } 5259 5330 … … 9195 9266 #define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \ 9196 9267 do { \ 9197 iemFpuPrepareUsage(pIemCpu); \9198 9268 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0)); \ 9199 9269 } while (0) … … 9208 9278 #define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \ 9209 9279 do { \ 9210 iemFpuPrepareUsage(pIemCpu); \9211 9280 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1)); \ 9212 9281 } while (0) … … 9222 9291 #define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 9223 9292 do { \ 9224 iemFpuPrepareUsage(pIemCpu); \9225 9293 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1), (a2)); \ 9226 9294 } while (0) … … 9326 9394 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \ 9327 9395 iemFpuStackPushOverflowWithMemOp(pIemCpu, a_iEffSeg, a_GCPtrEff) 9328 /** Indicates that we (might) have modified the FPU state. */ 9329 #define IEM_MC_USED_FPU() \ 9330 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM) 9396 /** Prepares for using the FPU state. 9397 * Ensures that we can use the host FPU in the current context (RC+R0. 9398 * Ensures the guest FPU state in the CPUMCTX is up to date. */ 9399 #define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pIemCpu) 9400 /** Actualizes the guest FPU state so it can be accessed read-only fashion. */ 9401 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pIemCpu) 9402 /** Actualizes the guest FPU state so it can be accessed and modified. */ 9403 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pIemCpu) 9404 9405 /** Prepares for using the SSE state. 9406 * Ensures that we can use the host SSE/FPU in the current context (RC+R0. 9407 * Ensures the guest SSE state in the CPUMCTX is up to date. */ 9408 #define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pIemCpu) 9409 /** Actualizes the guest XMM0..15 register state for read-only access. */ 9410 #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pIemCpu) 9411 /** Actualizes the guest XMM0..15 register state for read-write access. */ 9412 #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pIemCpu) 9331 9413 9332 9414 /** … … 9339 9421 #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \ 9340 9422 do { \ 9341 iemFpuPrepareUsage(pIemCpu); \9423 IEM_MC_PREPARE_FPU_USAGE(); \ 9342 9424 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1)); \ 9343 9425 } while (0) … … 9353 9435 #define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 9354 9436 do { \ 9355 iemFpuPrepareUsage(pIemCpu); \9437 IEM_MC_PREPARE_FPU_USAGE(); \ 9356 9438 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1), (a2)); \ 9357 9439 } while (0) … … 9367 9449 #define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \ 9368 9450 do { \ 9369 iemFpuPrepareUsageSse(pIemCpu); \9451 IEM_MC_PREPARE_SSE_USAGE(); \ 9370 9452 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1)); \ 9371 9453 } while (0) … … 9381 9463 #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 9382 9464 do { \ 9383 iemFpuPrepareUsageSse(pIemCpu); \9465 IEM_MC_PREPARE_SSE_USAGE(); \ 9384 9466 a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87, (a0), (a1), (a2)); \ 9385 9467 } while (0) 9386 9387 9468 9388 9469 /** @note Not for IOPL or IF testing. */ … … 9441 9522 #define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) { 9442 9523 #define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (*(uint64_t *)iemGRegRef(pIemCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) { 9524 9443 9525 #define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \ 9444 9526 if (iemFpuStRegNotEmpty(pIemCpu, (a_iSt)) == VINF_SUCCESS) { -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h
r61059 r61064 1710 1710 else 1711 1711 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 1712 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 1712 1713 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg, 1713 1714 (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 1730 1731 else 1731 1732 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 1733 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 1732 1734 1733 1735 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); … … 1757 1759 else 1758 1760 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 1761 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 1759 1762 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB, 1760 1763 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); … … 1777 1780 else 1778 1781 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 1782 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 1779 1783 1780 1784 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); … … 1793 1797 1794 1798 /** Opcode 0x0f 0x2b. */ 1795 #ifndef VBOX_WITH_REM /** @todo figure out why this causes moderate regressions when enabled... Enabled for non-REM to hopefully make some headway there... */1796 1799 FNIEMOP_DEF(iemOp_movntps_Mps_Vps__movntpd_Mpd_Vpd) 1797 1800 { … … 1813 1816 else 1814 1817 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 1818 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 1815 1819 1816 1820 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); … … 1825 1829 return VINF_SUCCESS; 1826 1830 } 1827 #else1828 FNIEMOP_STUB(iemOp_movntps_Mps_Vps__movntpd_Mpd_Vpd);1829 #endif1830 1831 1831 1832 … … 2174 2175 IEM_MC_ARG(uint64_t const *, pSrc, 1); 2175 2176 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2177 IEM_MC_PREPARE_SSE_USAGE(); 2176 2178 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2177 2179 IEM_MC_REF_XREG_U64_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 2196 2198 IEM_MC_FETCH_MEM_U64_ALIGN_U128(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2197 2199 2200 IEM_MC_PREPARE_SSE_USAGE(); 2198 2201 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2199 2202 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc); … … 2219 2222 IEM_MC_ARG(uint32_t const *, pSrc, 1); 2220 2223 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 2224 IEM_MC_PREPARE_FPU_USAGE(); 2221 2225 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2222 2226 IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK); … … 2241 2245 IEM_MC_FETCH_MEM_U32(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2242 2246 2247 IEM_MC_PREPARE_FPU_USAGE(); 2243 2248 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2244 2249 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc); … … 2318 2323 IEM_MC_ARG(uint128_t const *, pSrc, 1); 2319 2324 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2325 IEM_MC_PREPARE_SSE_USAGE(); 2320 2326 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2321 2327 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 2340 2346 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */ 2341 2347 2348 IEM_MC_PREPARE_SSE_USAGE(); 2342 2349 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2343 2350 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc); … … 2363 2370 IEM_MC_ARG(uint64_t const *, pSrc, 1); 2364 2371 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 2372 IEM_MC_PREPARE_FPU_USAGE(); 2365 2373 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2366 2374 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK); … … 2385 2393 IEM_MC_FETCH_MEM_U64(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2386 2394 2395 IEM_MC_PREPARE_FPU_USAGE(); 2387 2396 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2388 2397 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc); … … 2456 2465 IEM_MC_BEGIN(0, 1); 2457 2466 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2467 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2458 2468 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 2459 2469 { … … 2476 2486 IEM_MC_BEGIN(0, 2); 2477 2487 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2478 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2488 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); /** @todo order */ 2479 2489 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); 2480 2490 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2491 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2481 2492 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 2482 2493 { … … 2504 2515 IEM_MC_BEGIN(0, 1); 2505 2516 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 2517 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 2506 2518 IEM_MC_LOCAL(uint64_t, u64Tmp); 2507 2519 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) … … 2521 2533 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); 2522 2534 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2535 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 2523 2536 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 2524 2537 { … … 2564 2577 */ 2565 2578 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2566 IEM_MC_BEGIN(0, 1); 2567 IEM_MC_LOCAL(uint128_t, u128Tmp); 2579 IEM_MC_BEGIN(0, 0); 2568 2580 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2569 IEM_MC_FETCH_XREG_U128(u128Tmp, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); 2570 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg, u128Tmp); 2581 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2582 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg, 2583 (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); 2571 2584 IEM_MC_ADVANCE_RIP(); 2572 2585 IEM_MC_END(); … … 2584 2597 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2585 2598 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2599 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 2586 2600 if (fAligned) 2587 2601 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pIemCpu->iEffSeg, GCPtrEffSrc); … … 2608 2622 IEM_MC_LOCAL(uint64_t, u64Tmp); 2609 2623 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 2624 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 2610 2625 IEM_MC_FETCH_MREG_U64(u64Tmp, bRm & X86_MODRM_RM_MASK); 2611 2626 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp); … … 2625 2640 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2626 2641 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 2642 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 2627 2643 IEM_MC_FETCH_MEM_U64(u64Tmp, pIemCpu->iEffSeg, GCPtrEffSrc); 2628 2644 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp); … … 2679 2695 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2); 2680 2696 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2697 IEM_MC_PREPARE_SSE_USAGE(); 2681 2698 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2682 2699 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 2703 2720 2704 2721 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2722 IEM_MC_PREPARE_SSE_USAGE(); 2705 2723 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2706 2724 IEM_MC_CALL_SSE_AIMPL_3(pfnAImpl, pDst, pSrc, bEvilArg); … … 2727 2745 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2); 2728 2746 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT(); 2747 IEM_MC_PREPARE_FPU_USAGE(); 2729 2748 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2730 2749 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK); … … 2751 2770 2752 2771 IEM_MC_FETCH_MEM_U64(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2772 IEM_MC_PREPARE_FPU_USAGE(); 2753 2773 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 2754 2774 IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg); … … 2959 2979 IEM_MC_ARG(uint128_t const *, pSrc, 1); 2960 2980 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 2981 IEM_MC_PREPARE_SSE_USAGE(); 2961 2982 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2962 2983 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 2981 3002 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 2982 3003 3004 IEM_MC_PREPARE_SSE_USAGE(); 2983 3005 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 2984 3006 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc); … … 3002 3024 IEM_MC_ARG(uint64_t const *, pSrc, 1); 3003 3025 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 3026 IEM_MC_PREPARE_FPU_USAGE(); 3004 3027 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 3005 3028 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK); … … 3024 3047 IEM_MC_FETCH_MEM_U64(uSrc, pIemCpu->iEffSeg, GCPtrEffSrc); 3025 3048 3049 IEM_MC_PREPARE_FPU_USAGE(); 3026 3050 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 3027 3051 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc); … … 3088 3112 IEM_MC_BEGIN(0, 1); 3089 3113 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 3114 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 3090 3115 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3091 3116 { … … 3111 3136 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); 3112 3137 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3138 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 3113 3139 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3114 3140 { … … 3136 3162 IEM_MC_BEGIN(0, 1); 3137 3163 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 3164 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 3138 3165 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3139 3166 { … … 3159 3186 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); 3160 3187 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3188 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 3161 3189 if (pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3162 3190 { … … 3202 3230 */ 3203 3231 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3204 IEM_MC_BEGIN(0, 1); 3205 IEM_MC_LOCAL(uint128_t, u128Tmp); 3232 IEM_MC_BEGIN(0, 0); 3206 3233 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 3207 IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 3208 IEM_MC_STORE_XREG_U128((bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB, u128Tmp); 3234 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 3235 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB, 3236 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 3209 3237 IEM_MC_ADVANCE_RIP(); 3210 3238 IEM_MC_END(); … … 3222 3250 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3223 3251 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 3252 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 3253 3224 3254 IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 3225 3255 if (fAligned) … … 3247 3277 IEM_MC_LOCAL(uint64_t, u64Tmp); 3248 3278 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 3279 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 3249 3280 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 3250 3281 IEM_MC_STORE_MREG_U64(bRm & X86_MODRM_RM_MASK, u64Tmp); … … 3264 3295 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3265 3296 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 3297 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 3298 3266 3299 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 3267 3300 IEM_MC_STORE_MEM_U64(pIemCpu->iEffSeg, GCPtrEffSrc, u64Tmp); … … 6771 6804 IEM_MC_ARG(uint128_t const *, pSrc, 1); 6772 6805 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 6806 IEM_MC_PREPARE_SSE_USAGE(); 6773 6807 IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); 6774 6808 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB); … … 6785 6819 IEM_MC_ARG(uint64_t const *, pSrc, 1); 6786 6820 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT(); 6821 IEM_MC_PREPARE_FPU_USAGE(); 6787 6822 IEM_MC_REF_GREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); 6788 6823 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK); … … 6831 6866 6832 6867 /** Opcode 0x0f 0xe7. */ 6833 #if 0 //ndef VBOX_WITH_REM6834 6868 FNIEMOP_DEF(iemOp_movntq_Mq_Pq__movntdq_Mdq_Vdq) 6835 6869 { … … 6853 6887 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6854 6888 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 6889 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 6855 6890 6856 6891 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pIemCpu->uRexReg); … … 6869 6904 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6870 6905 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT(); 6906 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 6871 6907 6872 6908 IEM_MC_FETCH_MREG_U64(uSrc, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK); … … 6886 6922 return VINF_SUCCESS; 6887 6923 } 6888 #else6889 FNIEMOP_STUB(iemOp_movntq_Mq_Pq__movntdq_Mdq_Vdq);6890 #endif6891 6924 6892 6925 … … 13126 13159 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13127 13160 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13161 IEM_MC_PREPARE_FPU_USAGE(); 13128 13162 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK) 13129 13163 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2); … … 13132 13166 IEM_MC_FPU_STACK_UNDERFLOW(0); 13133 13167 IEM_MC_ENDIF(); 13134 IEM_MC_USED_FPU();13135 13168 IEM_MC_ADVANCE_RIP(); 13136 13169 … … 13158 13191 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13159 13192 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13193 IEM_MC_PREPARE_FPU_USAGE(); 13160 13194 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK) 13161 13195 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2); … … 13164 13198 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX); 13165 13199 IEM_MC_ENDIF(); 13166 IEM_MC_USED_FPU();13167 13200 IEM_MC_ADVANCE_RIP(); 13168 13201 … … 13190 13223 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13191 13224 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13225 IEM_MC_PREPARE_FPU_USAGE(); 13192 13226 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK) 13193 13227 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2); … … 13196 13230 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(UINT8_MAX); 13197 13231 IEM_MC_ENDIF(); 13198 IEM_MC_USED_FPU();13199 13232 IEM_MC_ADVANCE_RIP(); 13200 13233 … … 13291 13324 IEM_MC_FETCH_MEM_R32(r32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 13292 13325 13326 IEM_MC_PREPARE_FPU_USAGE(); 13293 13327 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 13294 13328 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr32Val2); … … 13297 13331 IEM_MC_FPU_STACK_UNDERFLOW(0); 13298 13332 IEM_MC_ENDIF(); 13299 IEM_MC_USED_FPU();13300 13333 IEM_MC_ADVANCE_RIP(); 13301 13334 … … 13341 13374 IEM_MC_FETCH_MEM_R32(r32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 13342 13375 13376 IEM_MC_PREPARE_FPU_USAGE(); 13343 13377 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 13344 13378 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r32, pu16Fsw, pr80Value1, pr32Val2); … … 13347 13381 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 13348 13382 IEM_MC_ENDIF(); 13349 IEM_MC_USED_FPU();13350 13383 IEM_MC_ADVANCE_RIP(); 13351 13384 … … 13375 13408 IEM_MC_FETCH_MEM_R32(r32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 13376 13409 13410 IEM_MC_PREPARE_FPU_USAGE(); 13377 13411 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 13378 13412 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r32, pu16Fsw, pr80Value1, pr32Val2); … … 13381 13415 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 13382 13416 IEM_MC_ENDIF(); 13383 IEM_MC_USED_FPU();13384 13417 IEM_MC_ADVANCE_RIP(); 13385 13418 … … 13480 13513 IEM_MC_FETCH_MEM_R32(r32Val, pIemCpu->iEffSeg, GCPtrEffSrc); 13481 13514 13515 IEM_MC_PREPARE_FPU_USAGE(); 13482 13516 IEM_MC_IF_FPUREG_IS_EMPTY(7) 13483 13517 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r32_to_r80, pFpuRes, pr32Val); … … 13486 13520 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 13487 13521 IEM_MC_ENDIF(); 13488 IEM_MC_USED_FPU();13489 13522 IEM_MC_ADVANCE_RIP(); 13490 13523 … … 13511 13544 13512 13545 IEM_MC_MEM_MAP(pr32Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 13546 IEM_MC_PREPARE_FPU_USAGE(); 13513 13547 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13514 13548 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r32, pu16Fsw, pr32Dst, pr80Value); … … 13522 13556 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 13523 13557 IEM_MC_ENDIF(); 13524 IEM_MC_USED_FPU();13525 13558 IEM_MC_ADVANCE_RIP(); 13526 13559 … … 13547 13580 13548 13581 IEM_MC_MEM_MAP(pr32Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 13582 IEM_MC_PREPARE_FPU_USAGE(); 13549 13583 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13550 13584 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r32, pu16Fsw, pr32Dst, pr80Value); … … 13558 13592 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 13559 13593 IEM_MC_ENDIF(); 13560 IEM_MC_USED_FPU();13561 13594 IEM_MC_ADVANCE_RIP(); 13562 13595 … … 13629 13662 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13630 13663 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13664 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 13631 13665 IEM_MC_FETCH_FCW(u16Fcw); 13632 13666 IEM_MC_STORE_MEM_U16(pIemCpu->iEffSeg, GCPtrEffDst, u16Fcw); … … 13646 13680 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13647 13681 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13682 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 13648 13683 /** @todo Testcase: looks like FNOP leaves FOP alone but updates FPUIP. Could be 13649 13684 * intel optimizations. Investigate. */ 13650 13685 IEM_MC_UPDATE_FPU_OPCODE_IP(); 13651 IEM_MC_USED_FPU();13652 13686 IEM_MC_ADVANCE_RIP(); /* C0-C3 are documented as undefined, we leave them unmodified. */ 13653 13687 IEM_MC_END(); … … 13669 13703 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13670 13704 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13705 13706 IEM_MC_PREPARE_FPU_USAGE(); 13671 13707 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, bRm & X86_MODRM_RM_MASK) 13672 13708 IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value); … … 13675 13711 IEM_MC_FPU_STACK_PUSH_UNDERFLOW(); 13676 13712 IEM_MC_ENDIF(); 13677 IEM_MC_USED_FPU(); 13713 13678 13714 IEM_MC_ADVANCE_RIP(); 13679 13715 IEM_MC_END(); … … 13698 13734 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13699 13735 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13736 13737 IEM_MC_PREPARE_FPU_USAGE(); 13700 13738 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK) 13701 13739 IEM_MC_SET_FPU_RESULT(FpuRes, X86_FSW_C1, pr80Value2); … … 13705 13743 IEM_MC_CALL_CIMPL_1(iemCImpl_fxch_underflow, iStReg); 13706 13744 IEM_MC_ENDIF(); 13707 IEM_MC_USED_FPU(); 13745 13708 13746 IEM_MC_ADVANCE_RIP(); 13709 13747 IEM_MC_END(); … … 13727 13765 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13728 13766 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13767 13768 IEM_MC_PREPARE_FPU_USAGE(); 13729 13769 IEM_MC_IF_FPUREG_NOT_EMPTY(0) 13730 13770 IEM_MC_UPDATE_FSW_THEN_POP(u16Fsw); … … 13732 13772 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(0); 13733 13773 IEM_MC_ENDIF(); 13734 IEM_MC_USED_FPU(); 13774 13735 13775 IEM_MC_ADVANCE_RIP(); 13736 13776 IEM_MC_END(); … … 13743 13783 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13744 13784 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13785 13786 IEM_MC_PREPARE_FPU_USAGE(); 13745 13787 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13746 13788 IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value); … … 13749 13791 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(iDstReg); 13750 13792 IEM_MC_ENDIF(); 13751 IEM_MC_USED_FPU(); 13793 13752 13794 IEM_MC_ADVANCE_RIP(); 13753 13795 IEM_MC_END(); … … 13774 13816 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13775 13817 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13818 IEM_MC_PREPARE_FPU_USAGE(); 13776 13819 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13777 13820 IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pFpuRes, pr80Value); … … 13780 13823 IEM_MC_FPU_STACK_UNDERFLOW(0); 13781 13824 IEM_MC_ENDIF(); 13782 IEM_MC_USED_FPU();13783 13825 IEM_MC_ADVANCE_RIP(); 13784 13826 … … 13820 13862 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13821 13863 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13864 IEM_MC_PREPARE_FPU_USAGE(); 13822 13865 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13823 13866 IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pu16Fsw, pr80Value); … … 13826 13869 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX); 13827 13870 IEM_MC_ENDIF(); 13828 IEM_MC_USED_FPU();13829 13871 IEM_MC_ADVANCE_RIP(); 13830 13872 … … 13865 13907 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13866 13908 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 13909 IEM_MC_PREPARE_FPU_USAGE(); 13867 13910 IEM_MC_IF_FPUREG_IS_EMPTY(7) 13868 13911 IEM_MC_CALL_FPU_AIMPL_1(pfnAImpl, pFpuRes); … … 13871 13914 IEM_MC_FPU_STACK_PUSH_OVERFLOW(); 13872 13915 IEM_MC_ENDIF(); 13873 IEM_MC_USED_FPU();13874 13916 IEM_MC_ADVANCE_RIP(); 13875 13917 … … 13966 14008 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 13967 14009 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14010 IEM_MC_PREPARE_FPU_USAGE(); 13968 14011 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 13969 14012 IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pFpuResTwo, pr80Value); … … 13972 14015 IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(); 13973 14016 IEM_MC_ENDIF(); 13974 IEM_MC_USED_FPU();13975 14017 IEM_MC_ADVANCE_RIP(); 13976 14018 … … 14007 14049 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14008 14050 14051 IEM_MC_PREPARE_FPU_USAGE(); 14009 14052 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0) 14010 14053 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2); … … 14013 14056 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(bRm & X86_MODRM_RM_MASK); 14014 14057 IEM_MC_ENDIF(); 14015 IEM_MC_USED_FPU();14016 14058 IEM_MC_ADVANCE_RIP(); 14017 14059 … … 14059 14101 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14060 14102 14103 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 14061 14104 IEM_MC_FPU_STACK_DEC_TOP(); 14062 14105 IEM_MC_UPDATE_FSW_CONST(0); 14063 14106 14064 IEM_MC_USED_FPU();14065 14107 IEM_MC_ADVANCE_RIP(); 14066 14108 IEM_MC_END(); … … 14083 14125 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14084 14126 14127 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 14085 14128 IEM_MC_FPU_STACK_INC_TOP(); 14086 14129 IEM_MC_UPDATE_FSW_CONST(0); 14087 14130 14088 IEM_MC_USED_FPU();14089 14131 IEM_MC_ADVANCE_RIP(); 14090 14132 IEM_MC_END(); … … 14250 14292 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14251 14293 14294 IEM_MC_PREPARE_FPU_USAGE(); 14252 14295 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14253 14296 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) … … 14258 14301 IEM_MC_FPU_STACK_UNDERFLOW(0); 14259 14302 IEM_MC_ENDIF(); 14260 IEM_MC_USED_FPU();14261 14303 IEM_MC_ADVANCE_RIP(); 14262 14304 … … 14278 14320 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14279 14321 14322 IEM_MC_PREPARE_FPU_USAGE(); 14280 14323 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14281 14324 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) … … 14286 14329 IEM_MC_FPU_STACK_UNDERFLOW(0); 14287 14330 IEM_MC_ENDIF(); 14288 IEM_MC_USED_FPU();14289 14331 IEM_MC_ADVANCE_RIP(); 14290 14332 … … 14306 14348 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14307 14349 14350 IEM_MC_PREPARE_FPU_USAGE(); 14308 14351 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14309 14352 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) … … 14314 14357 IEM_MC_FPU_STACK_UNDERFLOW(0); 14315 14358 IEM_MC_ENDIF(); 14316 IEM_MC_USED_FPU();14317 14359 IEM_MC_ADVANCE_RIP(); 14318 14360 … … 14334 14376 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14335 14377 14378 IEM_MC_PREPARE_FPU_USAGE(); 14336 14379 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14337 14380 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) … … 14342 14385 IEM_MC_FPU_STACK_UNDERFLOW(0); 14343 14386 IEM_MC_ENDIF(); 14344 IEM_MC_USED_FPU();14345 14387 IEM_MC_ADVANCE_RIP(); 14346 14388 … … 14368 14410 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 14369 14411 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14412 14413 IEM_MC_PREPARE_FPU_USAGE(); 14370 14414 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, 1) 14371 14415 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2); … … 14374 14418 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(); 14375 14419 IEM_MC_ENDIF(); 14376 IEM_MC_USED_FPU();14377 14420 IEM_MC_ADVANCE_RIP(); 14378 14421 … … 14413 14456 IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 14414 14457 14458 IEM_MC_PREPARE_FPU_USAGE(); 14415 14459 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 14416 14460 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pi32Val2); … … 14419 14463 IEM_MC_FPU_STACK_UNDERFLOW(0); 14420 14464 IEM_MC_ENDIF(); 14421 IEM_MC_USED_FPU();14422 14465 IEM_MC_ADVANCE_RIP(); 14423 14466 … … 14463 14506 IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 14464 14507 14508 IEM_MC_PREPARE_FPU_USAGE(); 14465 14509 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 14466 14510 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2); … … 14469 14513 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 14470 14514 IEM_MC_ENDIF(); 14471 IEM_MC_USED_FPU();14472 14515 IEM_MC_ADVANCE_RIP(); 14473 14516 … … 14497 14540 IEM_MC_FETCH_MEM_I32(i32Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 14498 14541 14542 IEM_MC_PREPARE_FPU_USAGE(); 14499 14543 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 14500 14544 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2); … … 14503 14547 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 14504 14548 IEM_MC_ENDIF(); 14505 IEM_MC_USED_FPU();14506 14549 IEM_MC_ADVANCE_RIP(); 14507 14550 … … 14603 14646 IEM_MC_FETCH_MEM_I32(i32Val, pIemCpu->iEffSeg, GCPtrEffSrc); 14604 14647 14648 IEM_MC_PREPARE_FPU_USAGE(); 14605 14649 IEM_MC_IF_FPUREG_IS_EMPTY(7) 14606 14650 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i32_to_r80, pFpuRes, pi32Val); … … 14609 14653 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 14610 14654 IEM_MC_ENDIF(); 14611 IEM_MC_USED_FPU();14612 14655 IEM_MC_ADVANCE_RIP(); 14613 14656 … … 14634 14677 14635 14678 IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 14679 IEM_MC_PREPARE_FPU_USAGE(); 14636 14680 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 14637 14681 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i32, pu16Fsw, pi32Dst, pr80Value); … … 14645 14689 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 14646 14690 IEM_MC_ENDIF(); 14647 IEM_MC_USED_FPU();14648 14691 IEM_MC_ADVANCE_RIP(); 14649 14692 … … 14670 14713 14671 14714 IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 14715 IEM_MC_PREPARE_FPU_USAGE(); 14672 14716 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 14673 14717 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i32, pu16Fsw, pi32Dst, pr80Value); … … 14681 14725 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 14682 14726 IEM_MC_ENDIF(); 14683 IEM_MC_USED_FPU();14684 14727 IEM_MC_ADVANCE_RIP(); 14685 14728 … … 14706 14749 14707 14750 IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 14751 IEM_MC_PREPARE_FPU_USAGE(); 14708 14752 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 14709 14753 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i32, pu16Fsw, pi32Dst, pr80Value); … … 14717 14761 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 14718 14762 IEM_MC_ENDIF(); 14719 IEM_MC_USED_FPU();14720 14763 IEM_MC_ADVANCE_RIP(); 14721 14764 … … 14744 14787 IEM_MC_FETCH_MEM_R80(r80Val, pIemCpu->iEffSeg, GCPtrEffSrc); 14745 14788 14789 IEM_MC_PREPARE_FPU_USAGE(); 14746 14790 IEM_MC_IF_FPUREG_IS_EMPTY(7) 14747 14791 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r80_from_r80, pFpuRes, pr80Val); … … 14750 14794 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 14751 14795 IEM_MC_ENDIF(); 14752 IEM_MC_USED_FPU();14753 14796 IEM_MC_ADVANCE_RIP(); 14754 14797 … … 14775 14818 14776 14819 IEM_MC_MEM_MAP(pr80Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 14820 IEM_MC_PREPARE_FPU_USAGE(); 14777 14821 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 14778 14822 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r80, pu16Fsw, pr80Dst, pr80Value); … … 14786 14830 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 14787 14831 IEM_MC_ENDIF(); 14788 IEM_MC_USED_FPU();14789 14832 IEM_MC_ADVANCE_RIP(); 14790 14833 … … 14806 14849 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14807 14850 14851 IEM_MC_PREPARE_FPU_USAGE(); 14808 14852 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14809 14853 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_CF) … … 14814 14858 IEM_MC_FPU_STACK_UNDERFLOW(0); 14815 14859 IEM_MC_ENDIF(); 14816 IEM_MC_USED_FPU();14817 14860 IEM_MC_ADVANCE_RIP(); 14818 14861 … … 14834 14877 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14835 14878 14879 IEM_MC_PREPARE_FPU_USAGE(); 14836 14880 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14837 14881 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF) … … 14842 14886 IEM_MC_FPU_STACK_UNDERFLOW(0); 14843 14887 IEM_MC_ENDIF(); 14844 IEM_MC_USED_FPU();14845 14888 IEM_MC_ADVANCE_RIP(); 14846 14889 … … 14862 14905 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14863 14906 14907 IEM_MC_PREPARE_FPU_USAGE(); 14864 14908 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14865 14909 IEM_MC_IF_EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF) … … 14870 14914 IEM_MC_FPU_STACK_UNDERFLOW(0); 14871 14915 IEM_MC_ENDIF(); 14872 IEM_MC_USED_FPU();14873 14916 IEM_MC_ADVANCE_RIP(); 14874 14917 … … 14890 14933 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 14891 14934 14935 IEM_MC_PREPARE_FPU_USAGE(); 14892 14936 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0) 14893 14937 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_PF) … … 14898 14942 IEM_MC_FPU_STACK_UNDERFLOW(0); 14899 14943 IEM_MC_ENDIF(); 14900 IEM_MC_USED_FPU();14901 14944 IEM_MC_ADVANCE_RIP(); 14902 14945 … … 15072 15115 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 15073 15116 15117 IEM_MC_PREPARE_FPU_USAGE(); 15074 15118 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0) 15075 15119 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2); … … 15078 15122 IEM_MC_FPU_STACK_UNDERFLOW(bRm & X86_MODRM_RM_MASK); 15079 15123 IEM_MC_ENDIF(); 15080 IEM_MC_USED_FPU();15081 15124 IEM_MC_ADVANCE_RIP(); 15082 15125 … … 15156 15199 15157 15200 IEM_MC_FETCH_MEM_R64(r64Factor2, pIemCpu->iEffSeg, GCPtrEffSrc); 15201 IEM_MC_PREPARE_FPU_USAGE(); 15158 15202 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Factor1, 0) 15159 15203 IEM_MC_CALL_FPU_AIMPL_3(pfnImpl, pFpuRes, pr80Factor1, pr64Factor2); … … 15162 15206 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(0, pIemCpu->iEffSeg, GCPtrEffSrc); 15163 15207 IEM_MC_ENDIF(); 15164 IEM_MC_USED_FPU();15165 15208 IEM_MC_ADVANCE_RIP(); 15166 15209 … … 15206 15249 IEM_MC_FETCH_MEM_R64(r64Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 15207 15250 15251 IEM_MC_PREPARE_FPU_USAGE(); 15208 15252 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 15209 15253 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r64, pu16Fsw, pr80Value1, pr64Val2); … … 15212 15256 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 15213 15257 IEM_MC_ENDIF(); 15214 IEM_MC_USED_FPU();15215 15258 IEM_MC_ADVANCE_RIP(); 15216 15259 … … 15240 15283 IEM_MC_FETCH_MEM_R64(r64Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 15241 15284 15285 IEM_MC_PREPARE_FPU_USAGE(); 15242 15286 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 15243 15287 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r64, pu16Fsw, pr80Value1, pr64Val2); … … 15246 15290 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 15247 15291 IEM_MC_ENDIF(); 15248 IEM_MC_USED_FPU();15249 15292 IEM_MC_ADVANCE_RIP(); 15250 15293 … … 15343 15386 15344 15387 IEM_MC_FETCH_MEM_R64(r64Val, pIemCpu->iEffSeg, GCPtrEffSrc); 15388 IEM_MC_PREPARE_FPU_USAGE(); 15345 15389 IEM_MC_IF_FPUREG_IS_EMPTY(7) 15346 15390 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r64_to_r80, pFpuRes, pr64Val); … … 15349 15393 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 15350 15394 IEM_MC_ENDIF(); 15351 IEM_MC_USED_FPU();15352 15395 IEM_MC_ADVANCE_RIP(); 15353 15396 … … 15374 15417 15375 15418 IEM_MC_MEM_MAP(pi64Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 15419 IEM_MC_PREPARE_FPU_USAGE(); 15376 15420 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 15377 15421 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i64, pu16Fsw, pi64Dst, pr80Value); … … 15385 15429 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 15386 15430 IEM_MC_ENDIF(); 15387 IEM_MC_USED_FPU();15388 15431 IEM_MC_ADVANCE_RIP(); 15389 15432 … … 15410 15453 15411 15454 IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 15455 IEM_MC_PREPARE_FPU_USAGE(); 15412 15456 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 15413 15457 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value); … … 15421 15465 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 15422 15466 IEM_MC_ENDIF(); 15423 IEM_MC_USED_FPU();15424 15467 IEM_MC_ADVANCE_RIP(); 15425 15468 … … 15448 15491 15449 15492 IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 15493 IEM_MC_PREPARE_FPU_USAGE(); 15450 15494 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 15451 15495 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value); … … 15459 15503 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 15460 15504 IEM_MC_ENDIF(); 15461 IEM_MC_USED_FPU();15462 15505 IEM_MC_ADVANCE_RIP(); 15463 15506 … … 15516 15559 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 15517 15560 15561 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 15518 15562 IEM_MC_FETCH_FSW(u16Tmp); 15519 15563 IEM_MC_STORE_MEM_U16(pIemCpu->iEffSeg, GCPtrEffDst, u16Tmp); … … 15541 15585 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 15542 15586 15587 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 15543 15588 IEM_MC_FPU_STACK_FREE(bRm & X86_MODRM_RM_MASK); 15544 15589 IEM_MC_UPDATE_FPU_OPCODE_IP(); 15545 15590 15546 IEM_MC_USED_FPU();15547 15591 IEM_MC_ADVANCE_RIP(); 15548 15592 IEM_MC_END(); … … 15562 15606 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 15563 15607 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 15608 15609 IEM_MC_PREPARE_FPU_USAGE(); 15564 15610 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 15565 15611 IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value); … … 15568 15614 IEM_MC_FPU_STACK_UNDERFLOW(bRm & X86_MODRM_RM_MASK); 15569 15615 IEM_MC_ENDIF(); 15570 IEM_MC_USED_FPU(); 15616 15571 15617 IEM_MC_ADVANCE_RIP(); 15572 15618 IEM_MC_END(); … … 15708 15754 IEM_MC_FETCH_MEM_I16(i16Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 15709 15755 15756 IEM_MC_PREPARE_FPU_USAGE(); 15710 15757 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 15711 15758 IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pi16Val2); … … 15714 15761 IEM_MC_FPU_STACK_UNDERFLOW(0); 15715 15762 IEM_MC_ENDIF(); 15716 IEM_MC_USED_FPU();15717 15763 IEM_MC_ADVANCE_RIP(); 15718 15764 … … 15758 15804 IEM_MC_FETCH_MEM_I16(i16Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 15759 15805 15806 IEM_MC_PREPARE_FPU_USAGE(); 15760 15807 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 15761 15808 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i16, pu16Fsw, pr80Value1, pi16Val2); … … 15764 15811 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 15765 15812 IEM_MC_ENDIF(); 15766 IEM_MC_USED_FPU();15767 15813 IEM_MC_ADVANCE_RIP(); 15768 15814 … … 15792 15838 IEM_MC_FETCH_MEM_I16(i16Val2, pIemCpu->iEffSeg, GCPtrEffSrc); 15793 15839 15840 IEM_MC_PREPARE_FPU_USAGE(); 15794 15841 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0) 15795 15842 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i16, pu16Fsw, pr80Value1, pi16Val2); … … 15798 15845 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffSrc); 15799 15846 IEM_MC_ENDIF(); 15800 IEM_MC_USED_FPU();15801 15847 IEM_MC_ADVANCE_RIP(); 15802 15848 … … 15890 15936 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 15891 15937 15938 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 15892 15939 IEM_MC_FPU_STACK_FREE(bRm & X86_MODRM_RM_MASK); 15893 15940 IEM_MC_FPU_STACK_INC_TOP(); 15894 15941 IEM_MC_UPDATE_FPU_OPCODE_IP(); 15895 15942 15896 IEM_MC_USED_FPU();15897 15943 IEM_MC_ADVANCE_RIP(); 15898 15944 IEM_MC_END(); … … 15910 15956 IEM_MC_LOCAL(uint16_t, u16Tmp); 15911 15957 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 15958 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 15912 15959 IEM_MC_FETCH_FSW(u16Tmp); 15913 15960 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp); … … 15953 16000 IEM_MC_FETCH_MEM_I16(i16Val, pIemCpu->iEffSeg, GCPtrEffSrc); 15954 16001 16002 IEM_MC_PREPARE_FPU_USAGE(); 15955 16003 IEM_MC_IF_FPUREG_IS_EMPTY(7) 15956 16004 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i16_to_r80, pFpuRes, pi16Val); … … 15959 16007 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 15960 16008 IEM_MC_ENDIF(); 15961 IEM_MC_USED_FPU();15962 16009 IEM_MC_ADVANCE_RIP(); 15963 16010 … … 15984 16031 15985 16032 IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 16033 IEM_MC_PREPARE_FPU_USAGE(); 15986 16034 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 15987 16035 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i16, pu16Fsw, pi16Dst, pr80Value); … … 15995 16043 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 15996 16044 IEM_MC_ENDIF(); 15997 IEM_MC_USED_FPU();15998 16045 IEM_MC_ADVANCE_RIP(); 15999 16046 … … 16020 16067 16021 16068 IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 16069 IEM_MC_PREPARE_FPU_USAGE(); 16022 16070 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 16023 16071 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i16, pu16Fsw, pi16Dst, pr80Value); … … 16031 16079 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 16032 16080 IEM_MC_ENDIF(); 16033 IEM_MC_USED_FPU();16034 16081 IEM_MC_ADVANCE_RIP(); 16035 16082 … … 16056 16103 16057 16104 IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 16105 IEM_MC_PREPARE_FPU_USAGE(); 16058 16106 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 16059 16107 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i16, pu16Fsw, pi16Dst, pr80Value); … … 16067 16115 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 16068 16116 IEM_MC_ENDIF(); 16069 IEM_MC_USED_FPU();16070 16117 IEM_MC_ADVANCE_RIP(); 16071 16118 … … 16098 16145 IEM_MC_FETCH_MEM_I64(i64Val, pIemCpu->iEffSeg, GCPtrEffSrc); 16099 16146 16147 IEM_MC_PREPARE_FPU_USAGE(); 16100 16148 IEM_MC_IF_FPUREG_IS_EMPTY(7) 16101 16149 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i64_to_r80, pFpuRes, pi64Val); … … 16104 16152 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pIemCpu->iEffSeg, GCPtrEffSrc); 16105 16153 IEM_MC_ENDIF(); 16106 IEM_MC_USED_FPU();16107 16154 IEM_MC_ADVANCE_RIP(); 16108 16155 … … 16133 16180 16134 16181 IEM_MC_MEM_MAP(pi64Dst, IEM_ACCESS_DATA_W, pIemCpu->iEffSeg, GCPtrEffDst, 1 /*arg*/); 16182 IEM_MC_PREPARE_FPU_USAGE(); 16135 16183 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) 16136 16184 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i64, pu16Fsw, pi64Dst, pr80Value); … … 16144 16192 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pIemCpu->iEffSeg, GCPtrEffDst); 16145 16193 IEM_MC_ENDIF(); 16146 IEM_MC_USED_FPU();16147 16194 IEM_MC_ADVANCE_RIP(); 16148 16195 -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r60992 r61064 401 401 #define IEM_MC_FETCH_EFLAGS(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint32_t, a_EFlags); } while (0) 402 402 #define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint8_t, a_EFlags); } while (0) 403 #define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); } while (0)404 #define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); } while (0)403 #define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); (void)fFpuRead; } while (0) 404 #define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); (void)fFpuRead; } while (0) 405 405 #define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) do { CHK_TYPE(uint8_t, a_u8Value); } while (0) 406 406 #define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) do { CHK_TYPE(uint16_t, a_u16Value); } while (0) … … 470 470 471 471 472 #define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0)473 #define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0)474 #define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0)475 #define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0)476 #define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); } while (0)477 #define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0)478 #define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); } while (0)479 480 #define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(uint128_t, a_u128Value); } while (0)481 #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0)482 #define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0)483 #define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(uint128_t, a_u128Value); } while (0)484 #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0)485 #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0)486 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t *)((uintptr_t)0); CHK_PTYPE(uint128_t *, a_pu128Dst); } while (0)487 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t const *)((uintptr_t)0); CHK_PTYPE(uint128_t const *, a_pu128Dst); } while (0)488 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0)489 #define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) do { } while (0)472 #define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fFpuRead; } while (0) 473 #define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fFpuRead; } while (0) 474 #define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fFpuWrite; } while (0) 475 #define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fFpuWrite; } while (0) 476 #define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); (void)fFpuWrite; } while (0) 477 #define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fFpuWrite; } while (0) 478 #define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); (void)fFpuWrite; } while (0) 479 480 #define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(uint128_t, a_u128Value); (void)fSseRead; } while (0) 481 #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; } while (0) 482 #define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fSseRead; } while (0) 483 #define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(uint128_t, a_u128Value); (void)fSseWrite; } while (0) 484 #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; } while (0) 485 #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; } while (0) 486 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t *)((uintptr_t)0); CHK_PTYPE(uint128_t *, a_pu128Dst); (void)fSseWrite; } while (0) 487 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t const *)((uintptr_t)0); CHK_PTYPE(uint128_t const *, a_pu128Dst); (void)fSseWrite; } while (0) 488 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fSseWrite; } while (0) 489 #define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) do { (void)fSseWrite; } while (0) 490 490 491 491 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) … … 588 588 589 589 #define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \ 590 do { CHK_CALL_ARG(a0, 0); } while (0)590 do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); } while (0) 591 591 #define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \ 592 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)592 do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) 593 593 #define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 594 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) 595 #define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { } while (0) 596 #define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { } while (0) 597 #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { } while (0) 598 #define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) do { } while (0) 599 #define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) do { } while (0) 600 #define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) do { } while (0) 601 #define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0) 602 #define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0) 603 #define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg) do { } while (0) 604 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0) 605 #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg) do { } while (0) 606 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0) 607 #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() do { } while (0) 608 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() do { } while (0) 609 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() do { } while (0) 610 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW() do { } while (0) 611 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) do { } while (0) 612 #define IEM_MC_UPDATE_FPU_OPCODE_IP() do { } while (0) 613 #define IEM_MC_FPU_STACK_DEC_TOP() do { } while (0) 614 #define IEM_MC_FPU_STACK_INC_TOP() do { } while (0) 615 #define IEM_MC_FPU_STACK_FREE(a_iStReg) do { } while (0) 616 #define IEM_MC_UPDATE_FSW(a_u16FSW) do { } while (0) 617 #define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) do { } while (0) 618 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { } while (0) 619 #define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) do { } while (0) 620 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { } while (0) 621 #define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { } while (0) 622 #define IEM_MC_USED_FPU() do { } while (0) 594 do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) 595 #define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { (void)fFpuWrite; } while (0) 596 #define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { (void)fFpuWrite; } while (0) 597 #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 598 #define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) do { (void)fFpuWrite; } while (0) 599 #define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) do { (void)fFpuWrite; } while (0) 600 #define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) do { (void)fFpuWrite; } while (0) 601 #define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 602 #define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 603 #define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg) do { (void)fFpuWrite; } while (0) 604 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 605 #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg) do { (void)fFpuWrite; } while (0) 606 #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 607 #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() do { (void)fFpuWrite; } while (0) 608 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() do { (void)fFpuWrite; } while (0) 609 #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() do { (void)fFpuWrite; } while (0) 610 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW() do { (void)fFpuWrite; } while (0) 611 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 612 #define IEM_MC_UPDATE_FPU_OPCODE_IP() do { (void)fFpuWrite; } while (0) 613 #define IEM_MC_FPU_STACK_DEC_TOP() do { (void)fFpuWrite; } while (0) 614 #define IEM_MC_FPU_STACK_INC_TOP() do { (void)fFpuWrite; } while (0) 615 #define IEM_MC_FPU_STACK_FREE(a_iStReg) do { (void)fFpuWrite; } while (0) 616 #define IEM_MC_UPDATE_FSW(a_u16FSW) do { (void)fFpuWrite; } while (0) 617 #define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) do { (void)fFpuWrite; } while (0) 618 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 619 #define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) do { (void)fFpuWrite; } while (0) 620 #define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0) 621 #define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { (void)fFpuWrite; } while (0) 622 #define IEM_MC_PREPARE_FPU_USAGE() \ 623 const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1 624 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() const int fFpuRead = 1, fSseRead = 1 625 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() const int fFpuRead = 1, fFpuWrite = 1, fSseRead = 1, fSseWrite = 1 626 #define IEM_MC_PREPARE_SSE_USAGE() const int fSseRead = 1, fSseWrite = 1, fSseHost = 1 627 #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() const int fSseRead = 1 628 #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() const int fSseRead = 1, fSseWrite = 1 623 629 624 630 #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \ 625 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)631 do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) 626 632 #define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 627 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0)633 do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) 628 634 #define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \ 629 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)635 do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) 630 636 #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 631 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0)637 do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) 632 638 633 639 #define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (g_fRandom) { … … 650 656 #define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) { 651 657 #define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (g_fRandom) { 652 #define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) if (g_fRandom ) {653 #define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) if (g_fRandom ) {658 #define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) if (g_fRandom != fFpuRead) { 659 #define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) if (g_fRandom != fFpuRead) { 654 660 #define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \ 655 661 a_pr80Dst = NULL; \ 656 if (g_fRandom ) {662 if (g_fRandom != fFpuRead) { 657 663 #define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(p0, i0, p1, i1) \ 658 664 p0 = NULL; \ 659 665 p1 = NULL; \ 660 if (g_fRandom ) {666 if (g_fRandom != fFpuRead) { 661 667 #define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(p0, i0, i1) \ 662 668 p0 = NULL; \ 663 if (g_fRandom ) {664 #define IEM_MC_IF_FCW_IM() if (g_fRandom ) {669 if (g_fRandom != fFpuRead) { 670 #define IEM_MC_IF_FCW_IM() if (g_fRandom != fFpuRead) { 665 671 #define IEM_MC_ELSE() } else { 666 672 #define IEM_MC_ENDIF() } do {} while (0)
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