- Timestamp:
- May 19, 2016 5:31:32 AM (8 years ago)
- Location:
- trunk
- Files:
-
- 4 edited
-
include/VBox/vmm/apic.h (modified) (2 diffs)
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src/VBox/VMM/VMMAll/APICAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/APIC.cpp (modified) (1 diff)
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src/VBox/VMM/include/APICInternal.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/apic.h
r60804 r61041 34 34 * @{ 35 35 */ 36 37 /** The APIC hardware version we are emulating. */38 #define XAPIC_HARDWARE_VERSION XAPIC_HARDWARE_VERSION_P439 36 40 37 /** Gets the APIC base physical address. */ … … 160 157 161 158 162 /**163 * The xAPIC sparse 256-bit register.164 */165 typedef union XAPIC256BITREG166 {167 /** The sparse-bitmap view. */168 struct169 {170 uint32_t u32Reg;171 uint32_t uReserved0[3];172 } u[8];173 /** The 32-bit view. */174 uint32_t au32[32];175 } XAPIC256BITREG;176 /** Pointer to an xAPIC sparse bitmap register. */177 typedef XAPIC256BITREG *PXAPIC256BITREG;178 /** Pointer to a const xAPIC sparse bitmap register. */179 typedef XAPIC256BITREG const *PCXAPIC256BITREG;180 AssertCompileSize(XAPIC256BITREG, 128);181 182 /**183 * The xAPIC memory layout as per Intel/AMD specs.184 */185 typedef struct XAPICPAGE186 {187 /* 0x00 - Reserved. */188 uint32_t uReserved0[8];189 /* 0x20 - APIC ID. */190 struct191 {192 uint8_t u8Reserved0[3];193 uint8_t u8ApicId;194 uint32_t u32Reserved0[3];195 } id;196 /* 0x30 - APIC version register. */197 union198 {199 struct200 {201 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4202 uint8_t u8Version;203 #else204 # error "Implement Pentium and P6 family APIC architectures"205 #endif206 uint8_t uReserved0;207 uint8_t u8MaxLvtEntry;208 uint8_t fEoiBroadcastSupression : 1;209 uint8_t u7Reserved1 : 7;210 uint32_t u32Reserved0[3];211 } u;212 struct213 {214 uint32_t u32Version;215 uint32_t u32Reserved0[3];216 } all;217 } version;218 /* 0x40 - Reserved. */219 uint32_t uReserved1[16];220 /* 0x80 - Task Priority Register (TPR). */221 struct222 {223 uint8_t u8Tpr;224 uint8_t u8Reserved0[3];225 uint32_t u32Reserved0[3];226 } tpr;227 /* 0x90 - Arbitration Priority Register (APR). */228 struct229 {230 uint8_t u8Apr;231 uint8_t u8Reserved0[3];232 uint32_t u32Reserved0[3];233 } apr;234 /* 0xA0 - Processor Priority Register (PPR). */235 struct236 {237 uint8_t u8Ppr;238 uint8_t u8Reserved0[3];239 uint32_t u32Reserved0[3];240 } ppr;241 /* 0xB0 - End Of Interrupt Register (EOI). */242 struct243 {244 uint32_t u32Eoi;245 uint32_t u32Reserved0[3];246 } eoi;247 /* 0xC0 - Remote Read Register (RRD). */248 struct249 {250 uint32_t u32Rrd;251 uint32_t u32Reserved0[3];252 } rrd;253 /* 0xD0 - Logical Destination Register (LDR). */254 union255 {256 struct257 {258 uint8_t u8Reserved0[3];259 uint8_t u8LogicalApicId;260 uint32_t u32Reserved0[3];261 } u;262 struct263 {264 uint32_t u32Ldr;265 uint32_t u32Reserved0[3];266 } all;267 } ldr;268 /* 0xE0 - Destination Format Register (DFR). */269 union270 {271 struct272 {273 uint32_t u28ReservedMb1 : 28; /* MB1 */274 uint32_t u4Model : 4;275 uint32_t u32Reserved0[3];276 } u;277 struct278 {279 uint32_t u32Dfr;280 uint32_t u32Reserved0[3];281 } all;282 } dfr;283 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */284 union285 {286 struct287 {288 uint32_t u8SpuriousVector : 8;289 uint32_t fApicSoftwareEnable : 1;290 uint32_t u3Reserved0 : 3;291 uint32_t fSupressEoiBroadcast : 1;292 uint32_t u19Reserved1 : 19;293 uint32_t u32Reserved0[3];294 } u;295 struct296 {297 uint32_t u32Svr;298 uint32_t u32Reserved0[3];299 } all;300 } svr;301 /* 0x100 - In-service Register (ISR). */302 XAPIC256BITREG isr;303 /* 0x180 - Trigger Mode Register (TMR). */304 XAPIC256BITREG tmr;305 /* 0x200 - Interrupt Request Register (IRR). */306 XAPIC256BITREG irr;307 /* 0x280 - Error Status Register (ESR). */308 union309 {310 struct311 {312 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4313 uint32_t u4Reserved0 : 4;314 #else315 # error "Implement Pentium and P6 family APIC architectures"316 #endif317 uint32_t fRedirectableIpi : 1;318 uint32_t fSendIllegalVector : 1;319 uint32_t fRcvdIllegalVector : 1;320 uint32_t fIllegalRegAddr : 1;321 uint32_t u24Reserved1 : 24;322 uint32_t u32Reserved0[3];323 } u;324 struct325 {326 uint32_t u32Errors;327 uint32_t u32Reserved0[3];328 } all;329 } esr;330 /* 0x290 - Reserved. */331 uint32_t uReserved2[28];332 /* 0x300 - Interrupt Command Register (ICR) - Low. */333 union334 {335 struct336 {337 uint32_t u8Vector : 8;338 uint32_t u3DeliveryMode : 3;339 uint32_t u1DestMode : 1;340 uint32_t u1DeliveryStatus : 1;341 uint32_t fReserved0 : 1;342 uint32_t u1Level : 1;343 uint32_t u1TriggerMode : 1;344 uint32_t u2Reserved1 : 2;345 uint32_t u2DestShorthand : 2;346 uint32_t u12Reserved2 : 12;347 uint32_t u32Reserved0[3];348 } u;349 struct350 {351 uint32_t u32IcrLo;352 uint32_t u32Reserved0[3];353 } all;354 } icr_lo;355 /* 0x310 - Interrupt Comannd Register (ICR) - High. */356 union357 {358 struct359 {360 uint32_t u24Reserved0 : 24;361 uint32_t u8Dest : 8;362 uint32_t u32Reserved0[3];363 } u;364 struct365 {366 uint32_t u32IcrHi;367 uint32_t u32Reserved0[3];368 } all;369 } icr_hi;370 /* 0x320 - Local Vector Table (LVT) Timer Register. */371 union372 {373 struct374 {375 uint32_t u8Vector : 8;376 uint32_t u4Reserved0 : 4;377 uint32_t u1DeliveryStatus : 1;378 uint32_t u3Reserved1 : 3;379 uint32_t u1Mask : 1;380 uint32_t u2TimerMode : 2;381 uint32_t u13Reserved2 : 13;382 uint32_t u32Reserved0[3];383 } u;384 struct385 {386 uint32_t u32LvtTimer;387 uint32_t u32Reserved0[3];388 } all;389 } lvt_timer;390 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */391 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4392 union393 {394 struct395 {396 uint32_t u8Vector : 8;397 uint32_t u3DeliveryMode : 3;398 uint32_t u1Reserved0 : 1;399 uint32_t u1DeliveryStatus : 1;400 uint32_t u3Reserved1 : 3;401 uint32_t u1Mask : 1;402 uint32_t u15Reserved2 : 15;403 uint32_t u32Reserved0[3];404 } u;405 struct406 {407 uint32_t u32LvtThermal;408 uint32_t u32Reserved0[3];409 } all;410 } lvt_thermal;411 #else412 # error "Implement Pentium and P6 family APIC architectures"413 #endif414 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */415 union416 {417 struct418 {419 uint32_t u8Vector : 8;420 uint32_t u3DeliveryMode : 3;421 uint32_t u1Reserved0 : 1;422 uint32_t u1DeliveryStatus : 1;423 uint32_t u3Reserved1 : 3;424 uint32_t u1Mask : 1;425 uint32_t u15Reserved2 : 15;426 uint32_t u32Reserved0[3];427 } u;428 struct429 {430 uint32_t u32LvtPerf;431 uint32_t u32Reserved0[3];432 } all;433 } lvt_perf;434 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */435 union436 {437 struct438 {439 uint32_t u8Vector : 8;440 uint32_t u3DeliveryMode : 3;441 uint32_t u1Reserved0 : 1;442 uint32_t u1DeliveryStatus : 1;443 uint32_t u1IntrPolarity : 1;444 uint32_t u1RemoteIrr : 1;445 uint32_t u1TriggerMode : 1;446 uint32_t u1Mask : 1;447 uint32_t u15Reserved2 : 15;448 uint32_t u32Reserved0[3];449 } u;450 struct451 {452 uint32_t u32LvtLint0;453 uint32_t u32Reserved0[3];454 } all;455 } lvt_lint0;456 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */457 union458 {459 struct460 {461 uint32_t u8Vector : 8;462 uint32_t u3DeliveryMode : 3;463 uint32_t u1Reserved0 : 1;464 uint32_t u1DeliveryStatus : 1;465 uint32_t u1IntrPolarity : 1;466 uint32_t u1RemoteIrr : 1;467 uint32_t u1TriggerMode : 1;468 uint32_t u1Mask : 1;469 uint32_t u15Reserved2 : 15;470 uint32_t u32Reserved0[3];471 } u;472 struct473 {474 uint32_t u32LvtLint1;475 uint32_t u32Reserved0[3];476 } all;477 } lvt_lint1;478 /* 0x370 - Local Vector Table (LVT) Error Register. */479 union480 {481 struct482 {483 uint32_t u8Vector : 8;484 uint32_t u4Reserved0 : 4;485 uint32_t u1DeliveryStatus : 1;486 uint32_t u3Reserved1 : 3;487 uint32_t u1Mask : 1;488 uint32_t u15Reserved2 : 15;489 uint32_t u32Reserved0[3];490 } u;491 struct492 {493 uint32_t u32LvtError;494 uint32_t u32Reserved0[3];495 } all;496 } lvt_error;497 /* 0x380 - Timer Initial Counter Register. */498 struct499 {500 uint32_t u32InitialCount;501 uint32_t u32Reserved0[3];502 } timer_icr;503 /* 0x390 - Timer Current Counter Register. */504 struct505 {506 uint32_t u32CurrentCount;507 uint32_t u32Reserved0[3];508 } timer_ccr;509 /* 0x3A0 - Reserved. */510 uint32_t u32Reserved3[16];511 /* 0x3E0 - Timer Divide Configuration Register. */512 union513 {514 struct515 {516 uint32_t u2DivideValue0 : 2;517 uint32_t u1Reserved0 : 1;518 uint32_t u1DivideValue1 : 1;519 uint32_t u28Reserved1 : 28;520 uint32_t u32Reserved0[3];521 } u;522 struct523 {524 uint32_t u32DivideValue;525 uint32_t u32Reserved0[3];526 } all;527 } timer_dcr;528 /* 0x3F0 - Reserved. */529 uint8_t u8Reserved0[3088];530 } XAPICPAGE;531 /** Pointer to a XAPICPAGE struct. */532 typedef XAPICPAGE *PXAPICPAGE;533 /** Pointer to a const XAPICPAGE struct. */534 typedef const XAPICPAGE *PCXAPICPAGE;535 AssertCompileSize(XAPICPAGE, 4096);536 AssertCompileMemberOffset(XAPICPAGE, id, XAPIC_OFF_ID);537 AssertCompileMemberOffset(XAPICPAGE, version, XAPIC_OFF_VERSION);538 AssertCompileMemberOffset(XAPICPAGE, tpr, XAPIC_OFF_TPR);539 AssertCompileMemberOffset(XAPICPAGE, apr, XAPIC_OFF_APR);540 AssertCompileMemberOffset(XAPICPAGE, ppr, XAPIC_OFF_PPR);541 AssertCompileMemberOffset(XAPICPAGE, eoi, XAPIC_OFF_EOI);542 AssertCompileMemberOffset(XAPICPAGE, rrd, XAPIC_OFF_RRD);543 AssertCompileMemberOffset(XAPICPAGE, ldr, XAPIC_OFF_LDR);544 AssertCompileMemberOffset(XAPICPAGE, dfr, XAPIC_OFF_DFR);545 AssertCompileMemberOffset(XAPICPAGE, svr, XAPIC_OFF_SVR);546 AssertCompileMemberOffset(XAPICPAGE, isr, XAPIC_OFF_ISR0);547 AssertCompileMemberOffset(XAPICPAGE, tmr, XAPIC_OFF_TMR0);548 AssertCompileMemberOffset(XAPICPAGE, irr, XAPIC_OFF_IRR0);549 AssertCompileMemberOffset(XAPICPAGE, esr, XAPIC_OFF_ESR);550 AssertCompileMemberOffset(XAPICPAGE, icr_lo, XAPIC_OFF_ICR_LO);551 AssertCompileMemberOffset(XAPICPAGE, icr_hi, XAPIC_OFF_ICR_HI);552 AssertCompileMemberOffset(XAPICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER);553 AssertCompileMemberOffset(XAPICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL);554 AssertCompileMemberOffset(XAPICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF);555 AssertCompileMemberOffset(XAPICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0);556 AssertCompileMemberOffset(XAPICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1);557 AssertCompileMemberOffset(XAPICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR);558 AssertCompileMemberOffset(XAPICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR);559 AssertCompileMemberOffset(XAPICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR);560 AssertCompileMemberOffset(XAPICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR);561 562 /**563 * The x2APIC memory layout as per Intel/AMD specs.564 */565 typedef struct X2APICPAGE566 {567 /* 0x00 - Reserved. */568 uint32_t uReserved0[8];569 /* 0x20 - APIC ID. */570 struct571 {572 uint32_t u32ApicId;573 uint32_t u32Reserved0[3];574 } id;575 /* 0x30 - APIC version register. */576 union577 {578 struct579 {580 uint8_t u8Version;581 uint8_t u8Reserved0;582 uint8_t u8MaxLvtEntry;583 uint8_t fEoiBroadcastSupression : 1;584 uint8_t u7Reserved1 : 7;585 uint32_t u32Reserved0[3];586 } u;587 struct588 {589 uint32_t u32Version;590 uint32_t u32Reserved2[3];591 } all;592 } version;593 /* 0x40 - Reserved. */594 uint32_t uReserved1[16];595 /* 0x80 - Task Priority Register (TPR). */596 struct597 {598 uint8_t u8Tpr;599 uint8_t u8Reserved0[3];600 uint32_t u32Reserved0[3];601 } tpr;602 /* 0x90 - Reserved. */603 uint32_t uReserved2[4];604 /* 0xA0 - Processor Priority Register (PPR). */605 struct606 {607 uint8_t u8Ppr;608 uint8_t u8Reserved0[3];609 uint32_t u32Reserved0[3];610 } ppr;611 /* 0xB0 - End Of Interrupt Register (EOI). */612 struct613 {614 uint32_t u32Eoi;615 uint32_t u32Reserved0[3];616 } eoi;617 /* 0xC0 - Remote Read Register (RRD). */618 struct619 {620 uint32_t u32Rrd;621 uint32_t u32Reserved0[3];622 } rrd;623 /* 0xD0 - Logical Destination Register (LDR). */624 struct625 {626 uint32_t u32LogicalApicId;627 uint32_t u32Reserved1[3];628 } ldr;629 /* 0xE0 - Reserved. */630 uint32_t uReserved3[4];631 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */632 union633 {634 struct635 {636 uint32_t u8SpuriousVector : 8;637 uint32_t fApicSoftwareEnable : 1;638 uint32_t u3Reserved0 : 3;639 uint32_t fSupressEoiBroadcast : 1;640 uint32_t u19Reserved1 : 19;641 uint32_t u32Reserved0[3];642 } u;643 struct644 {645 uint32_t u32Svr;646 uint32_t uReserved0[3];647 } all;648 } svr;649 /* 0x100 - In-service Register (ISR). */650 XAPIC256BITREG isr;651 /* 0x180 - Trigger Mode Register (TMR). */652 XAPIC256BITREG tmr;653 /* 0x200 - Interrupt Request Register (IRR). */654 XAPIC256BITREG irr;655 /* 0x280 - Error Status Register (ESR). */656 union657 {658 struct659 {660 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4661 uint32_t u4Reserved0 : 4;662 #else663 # error "Implement Pentium and P6 family APIC architectures"664 #endif665 uint32_t fRedirectableIpi : 1;666 uint32_t fSendIllegalVector : 1;667 uint32_t fRcvdIllegalVector : 1;668 uint32_t fIllegalRegAddr : 1;669 uint32_t u24Reserved1 : 24;670 uint32_t uReserved0[3];671 } u;672 struct673 {674 uint32_t u32Errors;675 uint32_t u32Reserved0[3];676 } all;677 } esr;678 /* 0x290 - Reserved. */679 uint32_t uReserved4[28];680 /* 0x300 - Interrupt Command Register (ICR) - Low. */681 union682 {683 struct684 {685 uint32_t u8Vector : 8;686 uint32_t u3DeliveryMode : 3;687 uint32_t u1DestMode : 1;688 uint32_t u2Reserved0 : 2;689 uint32_t u1Level : 1;690 uint32_t u1TriggerMode : 1;691 uint32_t u2Reserved1 : 2;692 uint32_t u2DestShorthand : 2;693 uint32_t u12Reserved2 : 12;694 uint32_t u32Reserved0[3];695 } u;696 struct697 {698 uint32_t u32IcrLo;699 uint32_t u32Reserved3[3];700 } all;701 } icr_lo;702 /* 0x310 - Interrupt Comannd Register (ICR) - High. */703 struct704 {705 uint32_t u32IcrHi;706 uint32_t uReserved1[3];707 } icr_hi;708 /* 0x320 - Local Vector Table (LVT) Timer Register. */709 union710 {711 struct712 {713 uint32_t u8Vector : 8;714 uint32_t u4Reserved0 : 4;715 uint32_t u1DeliveryStatus : 1;716 uint32_t u3Reserved1 : 3;717 uint32_t u1Mask : 1;718 uint32_t u2TimerMode : 2;719 uint32_t u13Reserved2 : 13;720 uint32_t u32Reserved0[3];721 } u;722 struct723 {724 uint32_t u32LvtTimer;725 uint32_t u32Reserved0[3];726 } all;727 } lvt_timer;728 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */729 union730 {731 struct732 {733 uint32_t u8Vector : 8;734 uint32_t u3DeliveryMode : 3;735 uint32_t u1Reserved0 : 1;736 uint32_t u1DeliveryStatus : 1;737 uint32_t u3Reserved1 : 3;738 uint32_t u1Mask : 1;739 uint32_t u15Reserved2 : 15;740 uint32_t u32Reserved0[3];741 } u;742 struct743 {744 uint32_t u32LvtThermal;745 uint32_t uReserved0[3];746 } all;747 } lvt_thermal;748 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */749 union750 {751 struct752 {753 uint32_t u8Vector : 8;754 uint32_t u3DeliveryMode : 3;755 uint32_t u1Reserved0 : 1;756 uint32_t u1DeliveryStatus : 1;757 uint32_t u3Reserved1 : 3;758 uint32_t u1Mask : 1;759 uint32_t u15Reserved2 : 15;760 uint32_t u32Reserved0[3];761 } u;762 struct763 {764 uint32_t u32LvtPerf;765 uint32_t u32Reserved0[3];766 } all;767 } lvt_perf;768 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */769 union770 {771 struct772 {773 uint32_t u8Vector : 8;774 uint32_t u3DeliveryMode : 3;775 uint32_t u1Reserved0 : 1;776 uint32_t u1DeliveryStatus : 1;777 uint32_t u1IntrPolarity : 1;778 uint32_t u1RemoteIrr : 1;779 uint32_t u1TriggerMode : 1;780 uint32_t u1Mask : 1;781 uint32_t u15Reserved2 : 15;782 uint32_t u32Reserved0[3];783 } u;784 struct785 {786 uint32_t u32LvtLint0;787 uint32_t u32Reserved0[3];788 } all;789 } lvt_lint0;790 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */791 union792 {793 struct794 {795 uint32_t u8Vector : 8;796 uint32_t u3DeliveryMode : 3;797 uint32_t u1Reserved0 : 1;798 uint32_t u1DeliveryStatus : 1;799 uint32_t u1IntrPolarity : 1;800 uint32_t u1RemoteIrr : 1;801 uint32_t u1TriggerMode : 1;802 uint32_t u1Mask : 1;803 uint32_t u15Reserved2 : 15;804 uint32_t u32Reserved0[3];805 } u;806 struct807 {808 uint32_t u32LvtLint1;809 uint32_t u32Reserved0[3];810 } all;811 } lvt_lint1;812 /* 0x370 - Local Vector Table (LVT) Error Register. */813 union814 {815 struct816 {817 uint32_t u8Vector : 8;818 uint32_t u4Reserved0 : 4;819 uint32_t u1DeliveryStatus : 1;820 uint32_t u3Reserved1 : 3;821 uint32_t u1Mask : 1;822 uint32_t u15Reserved2 : 15;823 uint32_t u32Reserved0[3];824 } u;825 struct826 {827 uint32_t u32LvtError;828 uint32_t u32Reserved0[3];829 } all;830 } lvt_error;831 /* 0x380 - Timer Initial Counter Register. */832 struct833 {834 uint32_t u32InitialCount;835 uint32_t u32Reserved0[3];836 } timer_icr;837 /* 0x390 - Timer Current Counter Register. */838 struct839 {840 uint32_t u32CurrentCount;841 uint32_t u32Reserved0[3];842 } timer_ccr;843 /* 0x3A0 - Reserved. */844 uint32_t uReserved5[16];845 /* 0x3E0 - Timer Divide Configuration Register. */846 union847 {848 struct849 {850 uint32_t u2DivideValue0 : 2;851 uint32_t u1Reserved0 : 1;852 uint32_t u1DivideValue1 : 1;853 uint32_t u28Reserved1 : 28;854 uint32_t u32Reserved0[3];855 } u;856 struct857 {858 uint32_t u32DivideValue;859 uint32_t u32Reserved0[3];860 } all;861 } timer_dcr;862 /* 0x3F0 - Self IPI Register. */863 struct864 {865 uint32_t u8Vector : 8;866 uint32_t u24Reserved0 : 24;867 uint32_t u32Reserved0[3];868 } self_ipi;869 /* 0x400 - Reserved. */870 uint8_t u8Reserved0[3072];871 } X2APICPAGE;872 /** Pointer to a X2APICPAGE struct. */873 typedef X2APICPAGE *PX2APICPAGE;874 /** Pointer to a const X2APICPAGE struct. */875 typedef const X2APICPAGE *PCX2APICPAGE;876 AssertCompileSize(X2APICPAGE, 4096);877 AssertCompileSize(X2APICPAGE, sizeof(XAPICPAGE));878 AssertCompileMemberOffset(X2APICPAGE, id, XAPIC_OFF_ID);879 AssertCompileMemberOffset(X2APICPAGE, version, XAPIC_OFF_VERSION);880 AssertCompileMemberOffset(X2APICPAGE, tpr, XAPIC_OFF_TPR);881 AssertCompileMemberOffset(X2APICPAGE, ppr, XAPIC_OFF_PPR);882 AssertCompileMemberOffset(X2APICPAGE, eoi, XAPIC_OFF_EOI);883 AssertCompileMemberOffset(X2APICPAGE, rrd, XAPIC_OFF_RRD);884 AssertCompileMemberOffset(X2APICPAGE, ldr, XAPIC_OFF_LDR);885 AssertCompileMemberOffset(X2APICPAGE, svr, XAPIC_OFF_SVR);886 AssertCompileMemberOffset(X2APICPAGE, isr, XAPIC_OFF_ISR0);887 AssertCompileMemberOffset(X2APICPAGE, tmr, XAPIC_OFF_TMR0);888 AssertCompileMemberOffset(X2APICPAGE, irr, XAPIC_OFF_IRR0);889 AssertCompileMemberOffset(X2APICPAGE, esr, XAPIC_OFF_ESR);890 AssertCompileMemberOffset(X2APICPAGE, icr_lo, XAPIC_OFF_ICR_LO);891 AssertCompileMemberOffset(X2APICPAGE, icr_hi, XAPIC_OFF_ICR_HI);892 AssertCompileMemberOffset(X2APICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER);893 AssertCompileMemberOffset(X2APICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL);894 AssertCompileMemberOffset(X2APICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF);895 AssertCompileMemberOffset(X2APICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0);896 AssertCompileMemberOffset(X2APICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1);897 AssertCompileMemberOffset(X2APICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR);898 AssertCompileMemberOffset(X2APICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR);899 AssertCompileMemberOffset(X2APICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR);900 AssertCompileMemberOffset(X2APICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR);901 AssertCompileMemberOffset(X2APICPAGE, self_ipi, X2APIC_OFF_SELF_IPI);902 903 159 RT_C_DECLS_BEGIN 904 160 -
trunk/src/VBox/VMM/VMMAll/APICAll.cpp
r60916 r61041 46 46 static const uint32_t g_au32LvtExtValidMask[] = 47 47 { 48 XAPIC_LVT_CMCI 48 XAPIC_LVT_CMCI_VALID 49 49 }; 50 50 #endif -
trunk/src/VBox/VMM/VMMR3/APIC.cpp
r61029 r61041 904 904 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue); 905 905 SSMR3GetU32(pSSM, &u32TimerShift); 906 /* Old implementation may have left the timer shift uninitialized until 907 * the timer configuration register was written. Unfortunately zero is 908 * also a valid timer shift value, so we're just going to ignore it 909 * completely. The shift count can always be derived from the DCR. 906 /* 907 * Old implementation may have left the timer shift uninitialized until 908 * the timer configuration register was written. Unfortunately zero is 909 * also a valid timer shift value, so we're just going to ignore it 910 * completely. The shift count can always be derived from the DCR. 911 * See @bugref{8245#c98}. 910 912 */ 911 913 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage); -
trunk/src/VBox/VMM/include/APICInternal.h
r60916 r61041 29 29 */ 30 30 31 /** The APIC hardware version we are emulating. */ 32 #define XAPIC_HARDWARE_VERSION XAPIC_HARDWARE_VERSION_P4 33 31 34 #define VMCPU_TO_XAPICPAGE(a_pVCpu) ((PXAPICPAGE)(CTX_SUFF((a_pVCpu)->apic.s.pvApicPage))) 32 35 #define VMCPU_TO_CXAPICPAGE(a_pVCpu) ((PCXAPICPAGE)(CTX_SUFF((a_pVCpu)->apic.s.pvApicPage))) … … 41 44 #define APICCPU_TO_XAPICPAGE(a_ApicCpu) ((PXAPICPAGE)(CTX_SUFF((a_ApicCpu)->pvApicPage))) 42 45 #define APICCPU_TO_CXAPICPAGE(a_ApicCpu) ((PCXAPICPAGE)(CTX_SUFF((a_ApicCpu)->pvApicPage))) 43 44 46 45 47 /** Whether the APIC is in X2APIC mode or not. */ … … 78 80 /** The APIC hardware version number for Pentium 6. */ 79 81 #define XAPIC_HARDWARE_VERSION_P6 UINT8_C(0x10) 82 83 /** 84 * The xAPIC sparse 256-bit register. 85 */ 86 typedef union XAPIC256BITREG 87 { 88 /** The sparse-bitmap view. */ 89 struct 90 { 91 uint32_t u32Reg; 92 uint32_t uReserved0[3]; 93 } u[8]; 94 /** The 32-bit view. */ 95 uint32_t au32[32]; 96 } XAPIC256BITREG; 97 /** Pointer to an xAPIC sparse bitmap register. */ 98 typedef XAPIC256BITREG *PXAPIC256BITREG; 99 /** Pointer to a const xAPIC sparse bitmap register. */ 100 typedef XAPIC256BITREG const *PCXAPIC256BITREG; 101 AssertCompileSize(XAPIC256BITREG, 128); 102 103 /** 104 * The xAPIC memory layout as per Intel/AMD specs. 105 */ 106 typedef struct XAPICPAGE 107 { 108 /* 0x00 - Reserved. */ 109 uint32_t uReserved0[8]; 110 /* 0x20 - APIC ID. */ 111 struct 112 { 113 uint8_t u8Reserved0[3]; 114 uint8_t u8ApicId; 115 uint32_t u32Reserved0[3]; 116 } id; 117 /* 0x30 - APIC version register. */ 118 union 119 { 120 struct 121 { 122 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 123 uint8_t u8Version; 124 #else 125 # error "Implement Pentium and P6 family APIC architectures" 126 #endif 127 uint8_t uReserved0; 128 uint8_t u8MaxLvtEntry; 129 uint8_t fEoiBroadcastSupression : 1; 130 uint8_t u7Reserved1 : 7; 131 uint32_t u32Reserved0[3]; 132 } u; 133 struct 134 { 135 uint32_t u32Version; 136 uint32_t u32Reserved0[3]; 137 } all; 138 } version; 139 /* 0x40 - Reserved. */ 140 uint32_t uReserved1[16]; 141 /* 0x80 - Task Priority Register (TPR). */ 142 struct 143 { 144 uint8_t u8Tpr; 145 uint8_t u8Reserved0[3]; 146 uint32_t u32Reserved0[3]; 147 } tpr; 148 /* 0x90 - Arbitration Priority Register (APR). */ 149 struct 150 { 151 uint8_t u8Apr; 152 uint8_t u8Reserved0[3]; 153 uint32_t u32Reserved0[3]; 154 } apr; 155 /* 0xA0 - Processor Priority Register (PPR). */ 156 struct 157 { 158 uint8_t u8Ppr; 159 uint8_t u8Reserved0[3]; 160 uint32_t u32Reserved0[3]; 161 } ppr; 162 /* 0xB0 - End Of Interrupt Register (EOI). */ 163 struct 164 { 165 uint32_t u32Eoi; 166 uint32_t u32Reserved0[3]; 167 } eoi; 168 /* 0xC0 - Remote Read Register (RRD). */ 169 struct 170 { 171 uint32_t u32Rrd; 172 uint32_t u32Reserved0[3]; 173 } rrd; 174 /* 0xD0 - Logical Destination Register (LDR). */ 175 union 176 { 177 struct 178 { 179 uint8_t u8Reserved0[3]; 180 uint8_t u8LogicalApicId; 181 uint32_t u32Reserved0[3]; 182 } u; 183 struct 184 { 185 uint32_t u32Ldr; 186 uint32_t u32Reserved0[3]; 187 } all; 188 } ldr; 189 /* 0xE0 - Destination Format Register (DFR). */ 190 union 191 { 192 struct 193 { 194 uint32_t u28ReservedMb1 : 28; /* MB1 */ 195 uint32_t u4Model : 4; 196 uint32_t u32Reserved0[3]; 197 } u; 198 struct 199 { 200 uint32_t u32Dfr; 201 uint32_t u32Reserved0[3]; 202 } all; 203 } dfr; 204 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */ 205 union 206 { 207 struct 208 { 209 uint32_t u8SpuriousVector : 8; 210 uint32_t fApicSoftwareEnable : 1; 211 uint32_t u3Reserved0 : 3; 212 uint32_t fSupressEoiBroadcast : 1; 213 uint32_t u19Reserved1 : 19; 214 uint32_t u32Reserved0[3]; 215 } u; 216 struct 217 { 218 uint32_t u32Svr; 219 uint32_t u32Reserved0[3]; 220 } all; 221 } svr; 222 /* 0x100 - In-service Register (ISR). */ 223 XAPIC256BITREG isr; 224 /* 0x180 - Trigger Mode Register (TMR). */ 225 XAPIC256BITREG tmr; 226 /* 0x200 - Interrupt Request Register (IRR). */ 227 XAPIC256BITREG irr; 228 /* 0x280 - Error Status Register (ESR). */ 229 union 230 { 231 struct 232 { 233 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 234 uint32_t u4Reserved0 : 4; 235 #else 236 # error "Implement Pentium and P6 family APIC architectures" 237 #endif 238 uint32_t fRedirectableIpi : 1; 239 uint32_t fSendIllegalVector : 1; 240 uint32_t fRcvdIllegalVector : 1; 241 uint32_t fIllegalRegAddr : 1; 242 uint32_t u24Reserved1 : 24; 243 uint32_t u32Reserved0[3]; 244 } u; 245 struct 246 { 247 uint32_t u32Errors; 248 uint32_t u32Reserved0[3]; 249 } all; 250 } esr; 251 /* 0x290 - Reserved. */ 252 uint32_t uReserved2[28]; 253 /* 0x300 - Interrupt Command Register (ICR) - Low. */ 254 union 255 { 256 struct 257 { 258 uint32_t u8Vector : 8; 259 uint32_t u3DeliveryMode : 3; 260 uint32_t u1DestMode : 1; 261 uint32_t u1DeliveryStatus : 1; 262 uint32_t fReserved0 : 1; 263 uint32_t u1Level : 1; 264 uint32_t u1TriggerMode : 1; 265 uint32_t u2Reserved1 : 2; 266 uint32_t u2DestShorthand : 2; 267 uint32_t u12Reserved2 : 12; 268 uint32_t u32Reserved0[3]; 269 } u; 270 struct 271 { 272 uint32_t u32IcrLo; 273 uint32_t u32Reserved0[3]; 274 } all; 275 } icr_lo; 276 /* 0x310 - Interrupt Comannd Register (ICR) - High. */ 277 union 278 { 279 struct 280 { 281 uint32_t u24Reserved0 : 24; 282 uint32_t u8Dest : 8; 283 uint32_t u32Reserved0[3]; 284 } u; 285 struct 286 { 287 uint32_t u32IcrHi; 288 uint32_t u32Reserved0[3]; 289 } all; 290 } icr_hi; 291 /* 0x320 - Local Vector Table (LVT) Timer Register. */ 292 union 293 { 294 struct 295 { 296 uint32_t u8Vector : 8; 297 uint32_t u4Reserved0 : 4; 298 uint32_t u1DeliveryStatus : 1; 299 uint32_t u3Reserved1 : 3; 300 uint32_t u1Mask : 1; 301 uint32_t u2TimerMode : 2; 302 uint32_t u13Reserved2 : 13; 303 uint32_t u32Reserved0[3]; 304 } u; 305 struct 306 { 307 uint32_t u32LvtTimer; 308 uint32_t u32Reserved0[3]; 309 } all; 310 } lvt_timer; 311 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */ 312 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 313 union 314 { 315 struct 316 { 317 uint32_t u8Vector : 8; 318 uint32_t u3DeliveryMode : 3; 319 uint32_t u1Reserved0 : 1; 320 uint32_t u1DeliveryStatus : 1; 321 uint32_t u3Reserved1 : 3; 322 uint32_t u1Mask : 1; 323 uint32_t u15Reserved2 : 15; 324 uint32_t u32Reserved0[3]; 325 } u; 326 struct 327 { 328 uint32_t u32LvtThermal; 329 uint32_t u32Reserved0[3]; 330 } all; 331 } lvt_thermal; 332 #else 333 # error "Implement Pentium and P6 family APIC architectures" 334 #endif 335 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */ 336 union 337 { 338 struct 339 { 340 uint32_t u8Vector : 8; 341 uint32_t u3DeliveryMode : 3; 342 uint32_t u1Reserved0 : 1; 343 uint32_t u1DeliveryStatus : 1; 344 uint32_t u3Reserved1 : 3; 345 uint32_t u1Mask : 1; 346 uint32_t u15Reserved2 : 15; 347 uint32_t u32Reserved0[3]; 348 } u; 349 struct 350 { 351 uint32_t u32LvtPerf; 352 uint32_t u32Reserved0[3]; 353 } all; 354 } lvt_perf; 355 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */ 356 union 357 { 358 struct 359 { 360 uint32_t u8Vector : 8; 361 uint32_t u3DeliveryMode : 3; 362 uint32_t u1Reserved0 : 1; 363 uint32_t u1DeliveryStatus : 1; 364 uint32_t u1IntrPolarity : 1; 365 uint32_t u1RemoteIrr : 1; 366 uint32_t u1TriggerMode : 1; 367 uint32_t u1Mask : 1; 368 uint32_t u15Reserved2 : 15; 369 uint32_t u32Reserved0[3]; 370 } u; 371 struct 372 { 373 uint32_t u32LvtLint0; 374 uint32_t u32Reserved0[3]; 375 } all; 376 } lvt_lint0; 377 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */ 378 union 379 { 380 struct 381 { 382 uint32_t u8Vector : 8; 383 uint32_t u3DeliveryMode : 3; 384 uint32_t u1Reserved0 : 1; 385 uint32_t u1DeliveryStatus : 1; 386 uint32_t u1IntrPolarity : 1; 387 uint32_t u1RemoteIrr : 1; 388 uint32_t u1TriggerMode : 1; 389 uint32_t u1Mask : 1; 390 uint32_t u15Reserved2 : 15; 391 uint32_t u32Reserved0[3]; 392 } u; 393 struct 394 { 395 uint32_t u32LvtLint1; 396 uint32_t u32Reserved0[3]; 397 } all; 398 } lvt_lint1; 399 /* 0x370 - Local Vector Table (LVT) Error Register. */ 400 union 401 { 402 struct 403 { 404 uint32_t u8Vector : 8; 405 uint32_t u4Reserved0 : 4; 406 uint32_t u1DeliveryStatus : 1; 407 uint32_t u3Reserved1 : 3; 408 uint32_t u1Mask : 1; 409 uint32_t u15Reserved2 : 15; 410 uint32_t u32Reserved0[3]; 411 } u; 412 struct 413 { 414 uint32_t u32LvtError; 415 uint32_t u32Reserved0[3]; 416 } all; 417 } lvt_error; 418 /* 0x380 - Timer Initial Counter Register. */ 419 struct 420 { 421 uint32_t u32InitialCount; 422 uint32_t u32Reserved0[3]; 423 } timer_icr; 424 /* 0x390 - Timer Current Counter Register. */ 425 struct 426 { 427 uint32_t u32CurrentCount; 428 uint32_t u32Reserved0[3]; 429 } timer_ccr; 430 /* 0x3A0 - Reserved. */ 431 uint32_t u32Reserved3[16]; 432 /* 0x3E0 - Timer Divide Configuration Register. */ 433 union 434 { 435 struct 436 { 437 uint32_t u2DivideValue0 : 2; 438 uint32_t u1Reserved0 : 1; 439 uint32_t u1DivideValue1 : 1; 440 uint32_t u28Reserved1 : 28; 441 uint32_t u32Reserved0[3]; 442 } u; 443 struct 444 { 445 uint32_t u32DivideValue; 446 uint32_t u32Reserved0[3]; 447 } all; 448 } timer_dcr; 449 /* 0x3F0 - Reserved. */ 450 uint8_t u8Reserved0[3088]; 451 } XAPICPAGE; 452 /** Pointer to a XAPICPAGE struct. */ 453 typedef XAPICPAGE *PXAPICPAGE; 454 /** Pointer to a const XAPICPAGE struct. */ 455 typedef const XAPICPAGE *PCXAPICPAGE; 456 AssertCompileSize(XAPICPAGE, 4096); 457 AssertCompileMemberOffset(XAPICPAGE, id, XAPIC_OFF_ID); 458 AssertCompileMemberOffset(XAPICPAGE, version, XAPIC_OFF_VERSION); 459 AssertCompileMemberOffset(XAPICPAGE, tpr, XAPIC_OFF_TPR); 460 AssertCompileMemberOffset(XAPICPAGE, apr, XAPIC_OFF_APR); 461 AssertCompileMemberOffset(XAPICPAGE, ppr, XAPIC_OFF_PPR); 462 AssertCompileMemberOffset(XAPICPAGE, eoi, XAPIC_OFF_EOI); 463 AssertCompileMemberOffset(XAPICPAGE, rrd, XAPIC_OFF_RRD); 464 AssertCompileMemberOffset(XAPICPAGE, ldr, XAPIC_OFF_LDR); 465 AssertCompileMemberOffset(XAPICPAGE, dfr, XAPIC_OFF_DFR); 466 AssertCompileMemberOffset(XAPICPAGE, svr, XAPIC_OFF_SVR); 467 AssertCompileMemberOffset(XAPICPAGE, isr, XAPIC_OFF_ISR0); 468 AssertCompileMemberOffset(XAPICPAGE, tmr, XAPIC_OFF_TMR0); 469 AssertCompileMemberOffset(XAPICPAGE, irr, XAPIC_OFF_IRR0); 470 AssertCompileMemberOffset(XAPICPAGE, esr, XAPIC_OFF_ESR); 471 AssertCompileMemberOffset(XAPICPAGE, icr_lo, XAPIC_OFF_ICR_LO); 472 AssertCompileMemberOffset(XAPICPAGE, icr_hi, XAPIC_OFF_ICR_HI); 473 AssertCompileMemberOffset(XAPICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER); 474 AssertCompileMemberOffset(XAPICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL); 475 AssertCompileMemberOffset(XAPICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF); 476 AssertCompileMemberOffset(XAPICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0); 477 AssertCompileMemberOffset(XAPICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1); 478 AssertCompileMemberOffset(XAPICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR); 479 AssertCompileMemberOffset(XAPICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR); 480 AssertCompileMemberOffset(XAPICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR); 481 AssertCompileMemberOffset(XAPICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR); 482 483 /** 484 * The x2APIC memory layout as per Intel/AMD specs. 485 */ 486 typedef struct X2APICPAGE 487 { 488 /* 0x00 - Reserved. */ 489 uint32_t uReserved0[8]; 490 /* 0x20 - APIC ID. */ 491 struct 492 { 493 uint32_t u32ApicId; 494 uint32_t u32Reserved0[3]; 495 } id; 496 /* 0x30 - APIC version register. */ 497 union 498 { 499 struct 500 { 501 uint8_t u8Version; 502 uint8_t u8Reserved0; 503 uint8_t u8MaxLvtEntry; 504 uint8_t fEoiBroadcastSupression : 1; 505 uint8_t u7Reserved1 : 7; 506 uint32_t u32Reserved0[3]; 507 } u; 508 struct 509 { 510 uint32_t u32Version; 511 uint32_t u32Reserved2[3]; 512 } all; 513 } version; 514 /* 0x40 - Reserved. */ 515 uint32_t uReserved1[16]; 516 /* 0x80 - Task Priority Register (TPR). */ 517 struct 518 { 519 uint8_t u8Tpr; 520 uint8_t u8Reserved0[3]; 521 uint32_t u32Reserved0[3]; 522 } tpr; 523 /* 0x90 - Reserved. */ 524 uint32_t uReserved2[4]; 525 /* 0xA0 - Processor Priority Register (PPR). */ 526 struct 527 { 528 uint8_t u8Ppr; 529 uint8_t u8Reserved0[3]; 530 uint32_t u32Reserved0[3]; 531 } ppr; 532 /* 0xB0 - End Of Interrupt Register (EOI). */ 533 struct 534 { 535 uint32_t u32Eoi; 536 uint32_t u32Reserved0[3]; 537 } eoi; 538 /* 0xC0 - Remote Read Register (RRD). */ 539 struct 540 { 541 uint32_t u32Rrd; 542 uint32_t u32Reserved0[3]; 543 } rrd; 544 /* 0xD0 - Logical Destination Register (LDR). */ 545 struct 546 { 547 uint32_t u32LogicalApicId; 548 uint32_t u32Reserved1[3]; 549 } ldr; 550 /* 0xE0 - Reserved. */ 551 uint32_t uReserved3[4]; 552 /* 0xF0 - Spurious-Interrupt Vector Register (SVR). */ 553 union 554 { 555 struct 556 { 557 uint32_t u8SpuriousVector : 8; 558 uint32_t fApicSoftwareEnable : 1; 559 uint32_t u3Reserved0 : 3; 560 uint32_t fSupressEoiBroadcast : 1; 561 uint32_t u19Reserved1 : 19; 562 uint32_t u32Reserved0[3]; 563 } u; 564 struct 565 { 566 uint32_t u32Svr; 567 uint32_t uReserved0[3]; 568 } all; 569 } svr; 570 /* 0x100 - In-service Register (ISR). */ 571 XAPIC256BITREG isr; 572 /* 0x180 - Trigger Mode Register (TMR). */ 573 XAPIC256BITREG tmr; 574 /* 0x200 - Interrupt Request Register (IRR). */ 575 XAPIC256BITREG irr; 576 /* 0x280 - Error Status Register (ESR). */ 577 union 578 { 579 struct 580 { 581 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 582 uint32_t u4Reserved0 : 4; 583 #else 584 # error "Implement Pentium and P6 family APIC architectures" 585 #endif 586 uint32_t fRedirectableIpi : 1; 587 uint32_t fSendIllegalVector : 1; 588 uint32_t fRcvdIllegalVector : 1; 589 uint32_t fIllegalRegAddr : 1; 590 uint32_t u24Reserved1 : 24; 591 uint32_t uReserved0[3]; 592 } u; 593 struct 594 { 595 uint32_t u32Errors; 596 uint32_t u32Reserved0[3]; 597 } all; 598 } esr; 599 /* 0x290 - Reserved. */ 600 uint32_t uReserved4[28]; 601 /* 0x300 - Interrupt Command Register (ICR) - Low. */ 602 union 603 { 604 struct 605 { 606 uint32_t u8Vector : 8; 607 uint32_t u3DeliveryMode : 3; 608 uint32_t u1DestMode : 1; 609 uint32_t u2Reserved0 : 2; 610 uint32_t u1Level : 1; 611 uint32_t u1TriggerMode : 1; 612 uint32_t u2Reserved1 : 2; 613 uint32_t u2DestShorthand : 2; 614 uint32_t u12Reserved2 : 12; 615 uint32_t u32Reserved0[3]; 616 } u; 617 struct 618 { 619 uint32_t u32IcrLo; 620 uint32_t u32Reserved3[3]; 621 } all; 622 } icr_lo; 623 /* 0x310 - Interrupt Comannd Register (ICR) - High. */ 624 struct 625 { 626 uint32_t u32IcrHi; 627 uint32_t uReserved1[3]; 628 } icr_hi; 629 /* 0x320 - Local Vector Table (LVT) Timer Register. */ 630 union 631 { 632 struct 633 { 634 uint32_t u8Vector : 8; 635 uint32_t u4Reserved0 : 4; 636 uint32_t u1DeliveryStatus : 1; 637 uint32_t u3Reserved1 : 3; 638 uint32_t u1Mask : 1; 639 uint32_t u2TimerMode : 2; 640 uint32_t u13Reserved2 : 13; 641 uint32_t u32Reserved0[3]; 642 } u; 643 struct 644 { 645 uint32_t u32LvtTimer; 646 uint32_t u32Reserved0[3]; 647 } all; 648 } lvt_timer; 649 /* 0x330 - Local Vector Table (LVT) Thermal Sensor Register. */ 650 union 651 { 652 struct 653 { 654 uint32_t u8Vector : 8; 655 uint32_t u3DeliveryMode : 3; 656 uint32_t u1Reserved0 : 1; 657 uint32_t u1DeliveryStatus : 1; 658 uint32_t u3Reserved1 : 3; 659 uint32_t u1Mask : 1; 660 uint32_t u15Reserved2 : 15; 661 uint32_t u32Reserved0[3]; 662 } u; 663 struct 664 { 665 uint32_t u32LvtThermal; 666 uint32_t uReserved0[3]; 667 } all; 668 } lvt_thermal; 669 /* 0x340 - Local Vector Table (LVT) Performance Monitor Counter (PMC) Register. */ 670 union 671 { 672 struct 673 { 674 uint32_t u8Vector : 8; 675 uint32_t u3DeliveryMode : 3; 676 uint32_t u1Reserved0 : 1; 677 uint32_t u1DeliveryStatus : 1; 678 uint32_t u3Reserved1 : 3; 679 uint32_t u1Mask : 1; 680 uint32_t u15Reserved2 : 15; 681 uint32_t u32Reserved0[3]; 682 } u; 683 struct 684 { 685 uint32_t u32LvtPerf; 686 uint32_t u32Reserved0[3]; 687 } all; 688 } lvt_perf; 689 /* 0x350 - Local Vector Table (LVT) LINT0 Register. */ 690 union 691 { 692 struct 693 { 694 uint32_t u8Vector : 8; 695 uint32_t u3DeliveryMode : 3; 696 uint32_t u1Reserved0 : 1; 697 uint32_t u1DeliveryStatus : 1; 698 uint32_t u1IntrPolarity : 1; 699 uint32_t u1RemoteIrr : 1; 700 uint32_t u1TriggerMode : 1; 701 uint32_t u1Mask : 1; 702 uint32_t u15Reserved2 : 15; 703 uint32_t u32Reserved0[3]; 704 } u; 705 struct 706 { 707 uint32_t u32LvtLint0; 708 uint32_t u32Reserved0[3]; 709 } all; 710 } lvt_lint0; 711 /* 0x360 - Local Vector Table (LVT) LINT1 Register. */ 712 union 713 { 714 struct 715 { 716 uint32_t u8Vector : 8; 717 uint32_t u3DeliveryMode : 3; 718 uint32_t u1Reserved0 : 1; 719 uint32_t u1DeliveryStatus : 1; 720 uint32_t u1IntrPolarity : 1; 721 uint32_t u1RemoteIrr : 1; 722 uint32_t u1TriggerMode : 1; 723 uint32_t u1Mask : 1; 724 uint32_t u15Reserved2 : 15; 725 uint32_t u32Reserved0[3]; 726 } u; 727 struct 728 { 729 uint32_t u32LvtLint1; 730 uint32_t u32Reserved0[3]; 731 } all; 732 } lvt_lint1; 733 /* 0x370 - Local Vector Table (LVT) Error Register. */ 734 union 735 { 736 struct 737 { 738 uint32_t u8Vector : 8; 739 uint32_t u4Reserved0 : 4; 740 uint32_t u1DeliveryStatus : 1; 741 uint32_t u3Reserved1 : 3; 742 uint32_t u1Mask : 1; 743 uint32_t u15Reserved2 : 15; 744 uint32_t u32Reserved0[3]; 745 } u; 746 struct 747 { 748 uint32_t u32LvtError; 749 uint32_t u32Reserved0[3]; 750 } all; 751 } lvt_error; 752 /* 0x380 - Timer Initial Counter Register. */ 753 struct 754 { 755 uint32_t u32InitialCount; 756 uint32_t u32Reserved0[3]; 757 } timer_icr; 758 /* 0x390 - Timer Current Counter Register. */ 759 struct 760 { 761 uint32_t u32CurrentCount; 762 uint32_t u32Reserved0[3]; 763 } timer_ccr; 764 /* 0x3A0 - Reserved. */ 765 uint32_t uReserved5[16]; 766 /* 0x3E0 - Timer Divide Configuration Register. */ 767 union 768 { 769 struct 770 { 771 uint32_t u2DivideValue0 : 2; 772 uint32_t u1Reserved0 : 1; 773 uint32_t u1DivideValue1 : 1; 774 uint32_t u28Reserved1 : 28; 775 uint32_t u32Reserved0[3]; 776 } u; 777 struct 778 { 779 uint32_t u32DivideValue; 780 uint32_t u32Reserved0[3]; 781 } all; 782 } timer_dcr; 783 /* 0x3F0 - Self IPI Register. */ 784 struct 785 { 786 uint32_t u8Vector : 8; 787 uint32_t u24Reserved0 : 24; 788 uint32_t u32Reserved0[3]; 789 } self_ipi; 790 /* 0x400 - Reserved. */ 791 uint8_t u8Reserved0[3072]; 792 } X2APICPAGE; 793 /** Pointer to a X2APICPAGE struct. */ 794 typedef X2APICPAGE *PX2APICPAGE; 795 /** Pointer to a const X2APICPAGE struct. */ 796 typedef const X2APICPAGE *PCX2APICPAGE; 797 AssertCompileSize(X2APICPAGE, 4096); 798 AssertCompileSize(X2APICPAGE, sizeof(XAPICPAGE)); 799 AssertCompileMemberOffset(X2APICPAGE, id, XAPIC_OFF_ID); 800 AssertCompileMemberOffset(X2APICPAGE, version, XAPIC_OFF_VERSION); 801 AssertCompileMemberOffset(X2APICPAGE, tpr, XAPIC_OFF_TPR); 802 AssertCompileMemberOffset(X2APICPAGE, ppr, XAPIC_OFF_PPR); 803 AssertCompileMemberOffset(X2APICPAGE, eoi, XAPIC_OFF_EOI); 804 AssertCompileMemberOffset(X2APICPAGE, rrd, XAPIC_OFF_RRD); 805 AssertCompileMemberOffset(X2APICPAGE, ldr, XAPIC_OFF_LDR); 806 AssertCompileMemberOffset(X2APICPAGE, svr, XAPIC_OFF_SVR); 807 AssertCompileMemberOffset(X2APICPAGE, isr, XAPIC_OFF_ISR0); 808 AssertCompileMemberOffset(X2APICPAGE, tmr, XAPIC_OFF_TMR0); 809 AssertCompileMemberOffset(X2APICPAGE, irr, XAPIC_OFF_IRR0); 810 AssertCompileMemberOffset(X2APICPAGE, esr, XAPIC_OFF_ESR); 811 AssertCompileMemberOffset(X2APICPAGE, icr_lo, XAPIC_OFF_ICR_LO); 812 AssertCompileMemberOffset(X2APICPAGE, icr_hi, XAPIC_OFF_ICR_HI); 813 AssertCompileMemberOffset(X2APICPAGE, lvt_timer, XAPIC_OFF_LVT_TIMER); 814 AssertCompileMemberOffset(X2APICPAGE, lvt_thermal, XAPIC_OFF_LVT_THERMAL); 815 AssertCompileMemberOffset(X2APICPAGE, lvt_perf, XAPIC_OFF_LVT_PERF); 816 AssertCompileMemberOffset(X2APICPAGE, lvt_lint0, XAPIC_OFF_LVT_LINT0); 817 AssertCompileMemberOffset(X2APICPAGE, lvt_lint1, XAPIC_OFF_LVT_LINT1); 818 AssertCompileMemberOffset(X2APICPAGE, lvt_error, XAPIC_OFF_LVT_ERROR); 819 AssertCompileMemberOffset(X2APICPAGE, timer_icr, XAPIC_OFF_TIMER_ICR); 820 AssertCompileMemberOffset(X2APICPAGE, timer_ccr, XAPIC_OFF_TIMER_CCR); 821 AssertCompileMemberOffset(X2APICPAGE, timer_dcr, XAPIC_OFF_TIMER_DCR); 822 AssertCompileMemberOffset(X2APICPAGE, self_ipi, X2APIC_OFF_SELF_IPI); 80 823 81 824 /** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */
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