Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c	(revision 60728)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c	(revision 60729)
@@ -2204,5 +2204,6 @@
         bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
         if (Bs3MemCmp(pbBufSave, pbExpected, cbIdtr * 2) != 0)
-            Bs3TestFailedF("Mismatch (#1): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr*2, pbExpected, cbIdtr*2, pbBufSave);
+            Bs3TestFailedF("Mismatch (%s, #1): expected %.*Rhxs, got %.*Rhxs\n",
+                           pWorker->pszDesc, cbIdtr*2, pbExpected, cbIdtr*2, pbBufSave);
     }
     g_usBs3TestStep++;
@@ -2234,5 +2235,6 @@
         bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
         if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-            Bs3TestFailedF("Mismatch (#2): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+            Bs3TestFailedF("Mismatch (%s, #2): expected %.*Rhxs, got %.*Rhxs\n",
+                           pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
     }
     g_usBs3TestStep++;
@@ -2259,6 +2261,7 @@
                     || Bs3MemCmp(&pbBufSave[2], &s_aValues64[i].u64Base, 8) != 0
                     || !ASMMemIsAllU8(&pbBufSave[10], cbIdtr, bFiller2))
-                    Bs3TestFailedF("Mismatch (#2): expected %04RX16:%016RX64, fillers %#x %#x, got %.*Rhxs\n",
-                                   s_aValues64[i].cbLimit, s_aValues64[i].u64Base, bFiller1, bFiller2, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s, #2): expected %04RX16:%016RX64, fillers %#x %#x, got %.*Rhxs\n",
+                                   pWorker->pszDesc, s_aValues64[i].cbLimit, s_aValues64[i].u64Base,
+                                   bFiller1, bFiller2, cbIdtr*2, pbBufSave);
             }
             g_usBs3TestStep++;
@@ -2284,7 +2287,7 @@
                         && pbBufSave[2+3] != bTop16BitBase)
                     || !ASMMemIsAllU8(&pbBufSave[8], cbIdtr, bFiller2))
-                    Bs3TestFailedF("Mismatch (#3): loaded %04RX16:%08RX32, fillers %#x %#x%s, %s, got %.*Rhxs\n",
-                                   s_aValues32[i].cbLimit, s_aValues32[i].u32Base, bFiller1, bFiller2, f286 ? ", 286" : "",
-                                   pWorker->pszDesc, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s,#3): loaded %04RX16:%08RX32, fillers %#x %#x%s, got %.*Rhxs\n",
+                                   pWorker->pszDesc, s_aValues32[i].cbLimit, s_aValues32[i].u32Base, bFiller1, bFiller2,
+                                   f286 ? ", 286" : "", cbIdtr*2, pbBufSave);
             }
             g_usBs3TestStep++;
@@ -2310,5 +2313,6 @@
             bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
             if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                Bs3TestFailedF("Mismatch (#4): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                Bs3TestFailedF("Mismatch (%s, #4): expected %.*Rhxs, got %.*Rhxs\n",
+                               pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
         }
         g_usBs3TestStep++;
@@ -2355,6 +2359,6 @@
                     bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                     if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                        Bs3TestFailedF("Mismatch (#5): expected %.*Rhxs, got %.*Rhxs\n",
-                                       cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                        Bs3TestFailedF("Mismatch (%s, #5): expected %.*Rhxs, got %.*Rhxs\n",
+                                       pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
                 }
                 else if (pWorker->fSs)
@@ -2405,6 +2409,6 @@
                     bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                     if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                        Bs3TestFailedF("Mismatch (#6): expected %.*Rhxs, got %.*Rhxs\n",
-                                       cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                        Bs3TestFailedF("Mismatch (%s, #6): expected %.*Rhxs, got %.*Rhxs\n",
+                                       pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
                 }
                 else if (pWorker->fSs)
@@ -2467,6 +2471,6 @@
                 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr*2) != 0)
-                    Bs3TestFailedF("Mismatch (#7): expected %.*Rhxs, got %.*Rhxs\n",
-                                   cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s, #7): expected %.*Rhxs, got %.*Rhxs\n",
+                                   pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
             }
             else
@@ -2516,6 +2520,6 @@
                 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr*2) != 0)
-                    Bs3TestFailedF("Mismatch (#8): expected %.*Rhxs, got %.*Rhxs\n",
-                                   cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s, #8): expected %.*Rhxs, got %.*Rhxs\n",
+                                   pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
             }
             else
@@ -2542,9 +2546,14 @@
          * This is kind of interesting here since it the instruction seems to
          * actually be doing two separate read, just like it's S[IG]DT counterpart.
+         *
+         * Note! My 486DX4 does a DWORD limit read when the operand size is 32-bit,
+         *       that's what f486Weirdness deals with.
          */
         if (   !BS3_MODE_IS_RM_OR_V86(bTestMode)
             && !BS3_MODE_IS_64BIT_CODE(bTestMode))
         {
-            uint16_t cbLimit;
+            bool const f486Weirdness = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) == BS3CPU_80486
+                                    && BS3_MODE_IS_32BIT_CODE(bTestMode) == !(pWorker->fFlags & BS3CB2SIDTSGDT_F_OPSIZE);
+            uint16_t   cbLimit;
 
             Bs3GdteTestPage00 = Bs3Gdte_DATA16;
@@ -2580,6 +2589,6 @@
                             bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                             if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                                Bs3TestFailedF("Mismatch (#9): expected %.*Rhxs, got %.*Rhxs\n",
-                                               cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                                Bs3TestFailedF("Mismatch (%s, #9): expected %.*Rhxs, got %.*Rhxs\n",
+                                               pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
                         }
                         else
@@ -2587,5 +2596,7 @@
                     }
                     /* No #GP/#SS on limit, but instead #PF? */
-                    else if (off < cbLimit && off >= 0xfff)
+                    else if (  !f486Weirdness
+                             ? off     < cbLimit && off >= 0xfff
+                             : off + 2 < cbLimit && off >= 0xffd)
                         bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE));
                     /* #GP/#SS on limit or base. */
@@ -2637,6 +2648,6 @@
                         bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                         if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                            Bs3TestFailedF("Mismatch (#10): expected %.*Rhxs, got %.*Rhxs\n",
-                                           cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                            Bs3TestFailedF("Mismatch (%s, #10): expected %.*Rhxs, got %.*Rhxs\n",
+                                           pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
                     }
                     else if (cbLimit < off && off < X86_PAGE_SIZE)
@@ -2680,6 +2691,6 @@
                 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                    Bs3TestFailedF("Mismatch (#18): expected %.*Rhxs, got %.*Rhxs\n",
-                                   cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s, #11): expected %.*Rhxs, got %.*Rhxs\n",
+                                   pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
             }
         }
@@ -2699,6 +2710,6 @@
                 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected);
                 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0)
-                    Bs3TestFailedF("Mismatch (#19): expected %.*Rhxs, got %.*Rhxs\n",
-                                   cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
+                    Bs3TestFailedF("Mismatch (%s, #19): expected %.*Rhxs, got %.*Rhxs\n",
+                                   pWorker->pszDesc, cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave);
             }
         }
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2.c
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2.c	(revision 60728)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2.c	(revision 60729)
@@ -54,5 +54,5 @@
     //BS3TESTMODEENTRY_CMN("iret", bs3CpuBasic2_iret),
 //    BS3TESTMODEENTRY_MODE("iret", bs3CpuBasic2_iret),
-#if 0
+#if 1
     BS3TESTMODEENTRY_MODE("raise xcpt #1", bs3CpuBasic2_RaiseXcpt1),
     BS3TESTMODEENTRY_MODE("sidt", bs3CpuBasic2_sidt),