Changeset 60728 in vbox
- Timestamp:
- Apr 28, 2016 12:14:54 AM (8 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 4 edited
-
bs3-cpu-basic-2-template.c (modified) (32 diffs)
-
bs3-cpu-basic-2-template.mac (modified) (2 diffs)
-
bs3-cpu-basic-2.c (modified) (1 diff)
-
bs3kit/bs3-rm-InitAll.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c
r60724 r60728 48 48 /** Indicating that we've got operand size prefix and that it matters. */ 49 49 # define BS3CB2SIDTSGDT_F_OPSIZE UINT8_C(0x01) 50 /** Worker requires 386 or later. */ 51 # define BS3CB2SIDTSGDT_F_386PLUS UINT8_C(0x02) 50 52 #endif 51 53 … … 92 94 typedef struct BS3CB2SIDTSGDT 93 95 { 96 const char *pszDesc; 94 97 FPFNBS3FAR fpfnWorker; 95 98 uint8_t cbInstr; … … 146 149 extern FNBS3FAR bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64; 147 150 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c16; 151 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2_c16; 148 152 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c32; 149 153 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c64; … … 151 155 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2_c32; 152 156 extern FNBS3FAR bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64; 157 158 extern FNBS3FAR bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c16; 159 extern FNBS3FAR bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c32; 160 extern FNBS3FAR bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c64; 161 extern FNBS3FAR bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c16; 162 extern FNBS3FAR bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c32; 163 extern FNBS3FAR bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2_c64; 164 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c16; 165 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c32; 166 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c64; 167 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c16; 168 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c32; 169 extern FNBS3FAR bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2_c64; 153 170 154 171 #endif … … 170 187 static BS3CB2SIDTSGDT const g_aSidtWorkers[] = 171 188 { 172 { bs3CpuBasic2_sidt_bx_ud2_c16, 3, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},173 { bs3CpuBasic2_sidt_ss_bx_ud2_c16, 4, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},174 { bs3CpuBasic2_sidt_opsize_bx_ud2_c16, 4, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},175 { bs3CpuBasic2_sidt_opsize_ss_bx_ud2_c16, 5, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},176 { bs3CpuBasic2_sidt_bx_ud2_c32, 3, false, BS3_MODE_CODE_32},177 { bs3CpuBasic2_sidt_ss_bx_ud2_c32, 4, true, BS3_MODE_CODE_32},178 { bs3CpuBasic2_sidt_opsize_bx_ud2_c32, 4, false, BS3_MODE_CODE_32},179 { bs3CpuBasic2_sidt_opsize_ss_bx_ud2_c32, 5, true, BS3_MODE_CODE_32},180 { bs3CpuBasic2_sidt_bx_ud2_c64, 3, false, BS3_MODE_CODE_64},181 { bs3CpuBasic2_sidt_rexw_bx_ud2_c64, 4, false, BS3_MODE_CODE_64},182 { bs3CpuBasic2_sidt_opsize_bx_ud2_c64, 4, false, BS3_MODE_CODE_64},183 { bs3CpuBasic2_sidt_opsize_rexw_bx_ud2_c64, 5, false, BS3_MODE_CODE_64},189 { "", bs3CpuBasic2_sidt_bx_ud2_c16, 3, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 190 { "", bs3CpuBasic2_sidt_ss_bx_ud2_c16, 4, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 191 { "", bs3CpuBasic2_sidt_opsize_bx_ud2_c16, 4, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_386PLUS }, 192 { "", bs3CpuBasic2_sidt_opsize_ss_bx_ud2_c16, 5, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_386PLUS }, 193 { "", bs3CpuBasic2_sidt_bx_ud2_c32, 3, false, BS3_MODE_CODE_32, 0 }, 194 { "", bs3CpuBasic2_sidt_ss_bx_ud2_c32, 4, true, BS3_MODE_CODE_32, 0 }, 195 { "", bs3CpuBasic2_sidt_opsize_bx_ud2_c32, 4, false, BS3_MODE_CODE_32, 0 }, 196 { "", bs3CpuBasic2_sidt_opsize_ss_bx_ud2_c32, 5, true, BS3_MODE_CODE_32, 0 }, 197 { "", bs3CpuBasic2_sidt_bx_ud2_c64, 3, false, BS3_MODE_CODE_64, 0 }, 198 { "", bs3CpuBasic2_sidt_rexw_bx_ud2_c64, 4, false, BS3_MODE_CODE_64, 0 }, 199 { "", bs3CpuBasic2_sidt_opsize_bx_ud2_c64, 4, false, BS3_MODE_CODE_64, 0 }, 200 { "", bs3CpuBasic2_sidt_opsize_rexw_bx_ud2_c64, 5, false, BS3_MODE_CODE_64, 0 }, 184 201 }; 185 202 … … 187 204 static BS3CB2SIDTSGDT const g_aSgdtWorkers[] = 188 205 { 189 { bs3CpuBasic2_sgdt_bx_ud2_c16, 3, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},190 { bs3CpuBasic2_sgdt_ss_bx_ud2_c16, 4, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},191 { bs3CpuBasic2_sgdt_opsize_bx_ud2_c16, 4, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},192 { bs3CpuBasic2_sgdt_opsize_ss_bx_ud2_c16, 5, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86},193 { bs3CpuBasic2_sgdt_bx_ud2_c32, 3, false, BS3_MODE_CODE_32},194 { bs3CpuBasic2_sgdt_ss_bx_ud2_c32, 4, true, BS3_MODE_CODE_32},195 { bs3CpuBasic2_sgdt_opsize_bx_ud2_c32, 4, false, BS3_MODE_CODE_32},196 { bs3CpuBasic2_sgdt_opsize_ss_bx_ud2_c32, 5, true, BS3_MODE_CODE_32},197 { bs3CpuBasic2_sgdt_bx_ud2_c64, 3, false, BS3_MODE_CODE_64},198 { bs3CpuBasic2_sgdt_rexw_bx_ud2_c64, 4, false, BS3_MODE_CODE_64},199 { bs3CpuBasic2_sgdt_opsize_bx_ud2_c64, 4, false, BS3_MODE_CODE_64},200 { bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2_c64, 5, false, BS3_MODE_CODE_64},206 { "", bs3CpuBasic2_sgdt_bx_ud2_c16, 3, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 207 { "", bs3CpuBasic2_sgdt_ss_bx_ud2_c16, 4, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 208 { "", bs3CpuBasic2_sgdt_opsize_bx_ud2_c16, 4, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_386PLUS }, 209 { "", bs3CpuBasic2_sgdt_opsize_ss_bx_ud2_c16, 5, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_386PLUS }, 210 { "", bs3CpuBasic2_sgdt_bx_ud2_c32, 3, false, BS3_MODE_CODE_32, 0 }, 211 { "", bs3CpuBasic2_sgdt_ss_bx_ud2_c32, 4, true, BS3_MODE_CODE_32, 0 }, 212 { "", bs3CpuBasic2_sgdt_opsize_bx_ud2_c32, 4, false, BS3_MODE_CODE_32, 0 }, 213 { "", bs3CpuBasic2_sgdt_opsize_ss_bx_ud2_c32, 5, true, BS3_MODE_CODE_32, 0 }, 214 { "", bs3CpuBasic2_sgdt_bx_ud2_c64, 3, false, BS3_MODE_CODE_64, 0 }, 215 { "", bs3CpuBasic2_sgdt_rexw_bx_ud2_c64, 4, false, BS3_MODE_CODE_64, 0 }, 216 { "", bs3CpuBasic2_sgdt_opsize_bx_ud2_c64, 4, false, BS3_MODE_CODE_64, 0 }, 217 { "", bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2_c64, 5, false, BS3_MODE_CODE_64, 0 }, 201 218 }; 202 219 … … 204 221 static BS3CB2SIDTSGDT const g_aLidtWorkers[] = 205 222 { 206 { bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c16, 11, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 207 { bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2_c16, 12, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 208 { bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c16, 12, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 209 { bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2_c16, 13, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 210 { bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c32, 11, false, BS3_MODE_CODE_32, 0 }, 211 { bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2_c32, 12, true, BS3_MODE_CODE_32, 0 }, 212 { bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c32, 12, false, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 213 { bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2_c32, 13, true, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 214 { bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c64, 9, false, BS3_MODE_CODE_64, 0 }, 215 { bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 216 { bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 217 { bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64, 11, false, BS3_MODE_CODE_64, 0 }, 223 { "lidt [bx]", bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c16, 11, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 224 { "lidt [ss:bx]", bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2_c16, 12, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 225 { "o32 lidt [bx]", bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c16, 12, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_OPSIZE | BS3CB2SIDTSGDT_F_386PLUS }, 226 { "o32 lidt [bx]; sidt32", bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2_c16, 27, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_OPSIZE | BS3CB2SIDTSGDT_F_386PLUS }, 227 { "o32 lidt [ss:bx]", bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2_c16, 13, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_OPSIZE | BS3CB2SIDTSGDT_F_386PLUS }, 228 { "lidt [ebx]", bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c32, 11, false, BS3_MODE_CODE_32, 0 }, 229 { "lidt [ss:ebx]", bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2_c32, 12, true, BS3_MODE_CODE_32, 0 }, 230 { "o16 lidt [ebx]", bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c32, 12, false, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 231 { "o16 lidt [ss:ebx]", bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2_c32, 13, true, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 232 { "lidt [rbx]", bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2_c64, 9, false, BS3_MODE_CODE_64, 0 }, 233 { "o64 lidt [rbx]", bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 234 { "o32 lidt [rbx]", bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 235 { "o32 o64 lidt [rbx]", bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2_c64, 11, false, BS3_MODE_CODE_64, 0 }, 236 }; 237 238 /** LGDT test workers. */ 239 static BS3CB2SIDTSGDT const g_aLgdtWorkers[] = 240 { 241 { "lgdt [bx]", bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c16, 11, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 242 { "lgdt [ss:bx]", bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c16, 12, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, 0 }, 243 { "o32 lgdt [bx]", bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c16, 12, false, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_OPSIZE | BS3CB2SIDTSGDT_F_386PLUS }, 244 { "o32 lgdt [ss:bx]", bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c16, 13, true, BS3_MODE_CODE_16 | BS3_MODE_CODE_V86, BS3CB2SIDTSGDT_F_OPSIZE | BS3CB2SIDTSGDT_F_386PLUS }, 245 { "lgdt [ebx]", bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c32, 11, false, BS3_MODE_CODE_32, 0 }, 246 { "lgdt [ss:ebx]", bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c32, 12, true, BS3_MODE_CODE_32, 0 }, 247 { "o16 lgdt [ebx]", bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c32, 12, false, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 248 { "o16 lgdt [ss:ebx]", bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2_c32, 13, true, BS3_MODE_CODE_32, BS3CB2SIDTSGDT_F_OPSIZE }, 249 { "lgdt [rbx]", bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2_c64, 9, false, BS3_MODE_CODE_64, 0 }, 250 { "o64 lgdt [rbx]", bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 251 { "o32 lgdt [rbx]", bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2_c64, 10, false, BS3_MODE_CODE_64, 0 }, 252 { "o32 o64 lgdt [rbx]", bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2_c64, 11, false, BS3_MODE_CODE_64, 0 }, 218 253 }; 219 254 … … 2026 2061 uint8_t const *pbRestore, size_t cbRestore, uint8_t const *pbExpected) 2027 2062 { 2063 static const struct 2064 { 2065 bool fGP; 2066 uint16_t cbLimit; 2067 uint64_t u64Base; 2068 } s_aValues64[] = 2069 { 2070 { false, 0x0000, UINT64_C(0x0000000000000000) }, 2071 { false, 0x0001, UINT64_C(0x0000000000000001) }, 2072 { false, 0x0002, UINT64_C(0x0000000000000010) }, 2073 { false, 0x0003, UINT64_C(0x0000000000000123) }, 2074 { false, 0x0004, UINT64_C(0x0000000000001234) }, 2075 { false, 0x0005, UINT64_C(0x0000000000012345) }, 2076 { false, 0x0006, UINT64_C(0x0000000000123456) }, 2077 { false, 0x0007, UINT64_C(0x0000000001234567) }, 2078 { false, 0x0008, UINT64_C(0x0000000012345678) }, 2079 { false, 0x0009, UINT64_C(0x0000000123456789) }, 2080 { false, 0x000a, UINT64_C(0x000000123456789a) }, 2081 { false, 0x000b, UINT64_C(0x00000123456789ab) }, 2082 { false, 0x000c, UINT64_C(0x0000123456789abc) }, 2083 { false, 0x001c, UINT64_C(0x00007ffffeefefef) }, 2084 { false, 0xffff, UINT64_C(0x00007fffffffffff) }, 2085 { true, 0xf3f1, UINT64_C(0x0000800000000000) }, 2086 { true, 0x0000, UINT64_C(0x0000800000000000) }, 2087 { true, 0x0000, UINT64_C(0x0000800000000333) }, 2088 { true, 0x00f0, UINT64_C(0x0001000000000000) }, 2089 { true, 0x0ff0, UINT64_C(0x0012000000000000) }, 2090 { true, 0x0eff, UINT64_C(0x0123000000000000) }, 2091 { true, 0xe0fe, UINT64_C(0x1234000000000000) }, 2092 { true, 0x00ad, UINT64_C(0xffff300000000000) }, 2093 { true, 0x0000, UINT64_C(0xffff7fffffffffff) }, 2094 { true, 0x00f0, UINT64_C(0xffff7fffffffffff) }, 2095 { false, 0x5678, UINT64_C(0xffff800000000000) }, 2096 { false, 0x2969, UINT64_C(0xffffffffffeefefe) }, 2097 { false, 0x1221, UINT64_C(0xffffffffffffffff) }, 2098 { false, 0x1221, UINT64_C(0xffffffffffffffff) }, 2099 }; 2100 static const struct 2101 { 2102 uint16_t cbLimit; 2103 uint32_t u32Base; 2104 } s_aValues32[] = 2105 { 2106 { 0xdfdf, UINT32_C(0xefefefef) }, 2107 { 0x0000, UINT32_C(0x00000000) }, 2108 { 0x0001, UINT32_C(0x00000001) }, 2109 { 0x0002, UINT32_C(0x00000012) }, 2110 { 0x0003, UINT32_C(0x00000123) }, 2111 { 0x0004, UINT32_C(0x00001234) }, 2112 { 0x0005, UINT32_C(0x00012345) }, 2113 { 0x0006, UINT32_C(0x00123456) }, 2114 { 0x0007, UINT32_C(0x01234567) }, 2115 { 0x0008, UINT32_C(0x12345678) }, 2116 { 0x0009, UINT32_C(0x80204060) }, 2117 { 0x000a, UINT32_C(0xddeeffaa) }, 2118 { 0x000b, UINT32_C(0xfdecdbca) }, 2119 { 0x000c, UINT32_C(0x6098456b) }, 2120 { 0x000d, UINT32_C(0x98506099) }, 2121 { 0x000e, UINT32_C(0x206950bc) }, 2122 { 0x000f, UINT32_C(0x9740395d) }, 2123 { 0x0334, UINT32_C(0x64a9455e) }, 2124 { 0xb423, UINT32_C(0xd20b6eff) }, 2125 { 0x4955, UINT32_C(0x85296d46) }, 2126 { 0xffff, UINT32_C(0x07000039) }, 2127 { 0xefe1, UINT32_C(0x0007fe00) }, 2128 }; 2129 2028 2130 BS3TRAPFRAME TrapCtx; 2029 2131 BS3REGCTX Ctx; … … 2037 2139 uint8_t BS3_FAR *pbBufRestore; /* Correctly aligned pointer into abBufRestore. */ 2038 2140 uint8_t const cbIdtr = BS3_MODE_IS_64BIT_CODE(bTestMode) ? 2+8 : 2+4; 2039 uint8_t const cbBaseLoaded = BS3_MODE_IS_16BIT_CODE(bTestMode) || (pWorker->fFlags & BS3CB2SIDTSGDT_F_OPSIZE) 2040 ? 3 : cbIdtr - 2; 2141 uint8_t const cbBaseLoaded = BS3_MODE_IS_64BIT_CODE(bTestMode) ? 8 2142 : BS3_MODE_IS_16BIT_CODE(bTestMode) == !(pWorker->fFlags & BS3CB2SIDTSGDT_F_OPSIZE) 2143 ? 3 : 4; 2041 2144 bool const f286 = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) == BS3CPU_80286; 2042 2145 uint8_t const bTop16BitBase = f286 ? 0xff : 0x00; 2043 2146 uint8_t bFiller1; /* For filling abBufLoad. */ 2044 2147 uint8_t bFiller2; /* For filling abBufSave and expectations. */ 2045 // int off; 2046 // int off2; 2047 // unsigned cb; 2048 // uint8_t BS3_FAR *pbTest; 2148 int off; 2149 uint8_t BS3_FAR *pbTest; 2049 2150 unsigned i; 2050 2151 … … 2069 2170 if (BS3_MODE_IS_16BIT_SYS(bTestMode)) 2070 2171 g_uBs3TrapEipHint = Ctx.rip.u32; 2172 Ctx.rflags.u16 &= ~X86_EFL_IF; 2071 2173 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, abBufLoad); 2072 2174 … … 2093 2195 */ 2094 2196 Bs3MemZero(abBufLoad, sizeof(abBufLoad)); 2095 Bs3MemCpy(abBufLoad, pbBufRestore, cb Restore);2197 Bs3MemCpy(abBufLoad, pbBufRestore, cbIdtr); 2096 2198 Bs3MemZero(abBufSave, sizeof(abBufSave)); 2097 2199 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); … … 2123 2225 /* Again with a buffer filled with a byte not occuring in the previous result. */ 2124 2226 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2125 Bs3MemCpy(abBufLoad, pbBufRestore, cb Restore);2227 Bs3MemCpy(abBufLoad, pbBufRestore, cbIdtr); 2126 2228 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2127 2229 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); … … 2142 2244 if (BS3_MODE_IS_64BIT_CODE(bTestMode)) 2143 2245 { 2144 static const struct 2145 { 2146 bool fGP; 2147 uint16_t cbLimit; 2148 uint64_t u64Base; 2149 } s_aValues[] = 2150 { 2151 { false, 0x0000, UINT64_C(0x0000000000000000) }, 2152 { false, 0x0001, UINT64_C(0x0000000000000001) }, 2153 { false, 0x0002, UINT64_C(0x0000000000000010) }, 2154 { false, 0x0003, UINT64_C(0x0000000000000123) }, 2155 { false, 0x0004, UINT64_C(0x0000000000001234) }, 2156 { false, 0x0005, UINT64_C(0x0000000000012345) }, 2157 { false, 0x0006, UINT64_C(0x0000000000123456) }, 2158 { false, 0x0007, UINT64_C(0x0000000001234567) }, 2159 { false, 0x0008, UINT64_C(0x0000000012345678) }, 2160 { false, 0x0009, UINT64_C(0x0000000123456789) }, 2161 { false, 0x000a, UINT64_C(0x000000123456789a) }, 2162 { false, 0x000b, UINT64_C(0x00000123456789ab) }, 2163 { false, 0x000c, UINT64_C(0x0000123456789abc) }, 2164 { false, 0x001c, UINT64_C(0x00007ffffeefefef) }, 2165 { false, 0xffff, UINT64_C(0x00007fffffffffff) }, 2166 { true, 0xf3f1, UINT64_C(0x0000800000000000) }, 2167 { true, 0x0000, UINT64_C(0x0000800000000000) }, 2168 { true, 0x0000, UINT64_C(0x0000800000000333) }, 2169 { true, 0x00f0, UINT64_C(0x0001000000000000) }, 2170 { true, 0x0ff0, UINT64_C(0x0012000000000000) }, 2171 { true, 0x0eff, UINT64_C(0x0123000000000000) }, 2172 { true, 0xe0fe, UINT64_C(0x1234000000000000) }, 2173 { true, 0x00ad, UINT64_C(0xffff300000000000) }, 2174 { true, 0x0000, UINT64_C(0xffff7fffffffffff) }, 2175 { true, 0x00f0, UINT64_C(0xffff7fffffffffff) }, 2176 { false, 0x5678, UINT64_C(0xffff800000000000) }, 2177 { false, 0x2969, UINT64_C(0xffffffffffeefefe) }, 2178 { false, 0x1221, UINT64_C(0xffffffffffffffff) }, 2179 { false, 0x1221, UINT64_C(0xffffffffffffffff) }, 2180 }; 2181 for (i = 0; i < RT_ELEMENTS(s_aValues); i++) 2182 { 2183 Bs3MemSet(abBufSave, bFiller1, sizeof(abBufSave)); 2184 Bs3MemCpy(&abBufLoad[0], &s_aValues[i].cbLimit, 2); 2185 Bs3MemCpy(&abBufLoad[2], &s_aValues[i].u64Base, 8); 2246 for (i = 0; i < RT_ELEMENTS(s_aValues64); i++) 2247 { 2248 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2249 Bs3MemCpy(&abBufLoad[0], &s_aValues64[i].cbLimit, 2); 2250 Bs3MemCpy(&abBufLoad[2], &s_aValues64[i].u64Base, 8); 2186 2251 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2187 2252 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2188 if (bRing != 0 || s_aValues [i].fGP)2253 if (bRing != 0 || s_aValues64[i].fGP) 2189 2254 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2190 2255 else 2191 2256 { 2192 2257 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2193 if ( Bs3MemCmp(&pbBufSave[0], &s_aValues [i].cbLimit, 2) != 02194 || Bs3MemCmp(&pbBufSave[2], &s_aValues [i].u64Base, 8) != 02258 if ( Bs3MemCmp(&pbBufSave[0], &s_aValues64[i].cbLimit, 2) != 0 2259 || Bs3MemCmp(&pbBufSave[2], &s_aValues64[i].u64Base, 8) != 0 2195 2260 || !ASMMemIsAllU8(&pbBufSave[10], cbIdtr, bFiller2)) 2196 2261 Bs3TestFailedF("Mismatch (#2): expected %04RX16:%016RX64, fillers %#x %#x, got %.*Rhxs\n", 2197 s_aValues [i].cbLimit, s_aValues[i].u64Base, bFiller1, bFiller2, cbIdtr*2, pbBufSave);2262 s_aValues64[i].cbLimit, s_aValues64[i].u64Base, bFiller1, bFiller2, cbIdtr*2, pbBufSave); 2198 2263 } 2199 2264 g_usBs3TestStep++; … … 2202 2267 else 2203 2268 { 2204 static const struct 2205 { 2206 uint16_t cbLimit; 2207 uint32_t u32Base; 2208 } s_aValues[] = 2209 { 2210 { 0x0000, UINT32_C(0x00000000) }, 2211 { 0x0001, UINT32_C(0x00000001) }, 2212 { 0x0002, UINT32_C(0x00000012) }, 2213 { 0x0003, UINT32_C(0x00000123) }, 2214 { 0x0004, UINT32_C(0x00001234) }, 2215 { 0x0005, UINT32_C(0x00012345) }, 2216 { 0x0006, UINT32_C(0x00123456) }, 2217 { 0x0007, UINT32_C(0x01234567) }, 2218 { 0x0008, UINT32_C(0x12345678) }, 2219 { 0x0009, UINT32_C(0x80204060) }, 2220 { 0x000a, UINT32_C(0xddeeffaa) }, 2221 { 0x000b, UINT32_C(0xfdecdbca) }, 2222 { 0x000c, UINT32_C(0x6098456b) }, 2223 { 0x000d, UINT32_C(0x98506099) }, 2224 { 0x000e, UINT32_C(0x206950bc) }, 2225 { 0x000f, UINT32_C(0x9740395d) }, 2226 { 0x0334, UINT32_C(0x64a9455e) }, 2227 { 0xb423, UINT32_C(0xd20b6eff) }, 2228 { 0x4955, UINT32_C(0x85296d46) }, 2229 { 0xffff, UINT32_C(0x07000039) }, 2230 { 0xefe1, UINT32_C(0x0007fe00) }, 2231 }; 2232 for (i = 0; i < RT_ELEMENTS(s_aValues); i++) 2233 { 2234 Bs3MemSet(abBufSave, bFiller1, sizeof(abBufSave)); 2235 Bs3MemCpy(&abBufLoad[0], &s_aValues[i].cbLimit, 2); 2236 Bs3MemCpy(&abBufLoad[2], &s_aValues[i].u32Base, cbBaseLoaded); 2269 for (i = 0; i < RT_ELEMENTS(s_aValues32); i++) 2270 { 2271 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2272 Bs3MemCpy(&abBufLoad[0], &s_aValues32[i].cbLimit, 2); 2273 Bs3MemCpy(&abBufLoad[2], &s_aValues32[i].u32Base, cbBaseLoaded); 2237 2274 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2238 2275 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); … … 2242 2279 { 2243 2280 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2244 if ( Bs3MemCmp(&pbBufSave[0], &s_aValues [i].cbLimit, 2) != 02245 || Bs3MemCmp(&pbBufSave[2], &s_aValues [i].u32Base, cbBaseLoaded) != 02281 if ( Bs3MemCmp(&pbBufSave[0], &s_aValues32[i].cbLimit, 2) != 0 2282 || Bs3MemCmp(&pbBufSave[2], &s_aValues32[i].u32Base, cbBaseLoaded) != 0 2246 2283 || ( cbBaseLoaded != 4 2247 2284 && pbBufSave[2+3] != bTop16BitBase) 2248 2285 || !ASMMemIsAllU8(&pbBufSave[8], cbIdtr, bFiller2)) 2249 Bs3TestFailedF("Mismatch (#3): loaded %04RX16:%08RX32, fillers %#x %#x%s %s (cbIns=%d), got %.*Rhxs\n",2250 s_aValues [i].cbLimit, s_aValues[i].u32Base, bFiller1, bFiller2, f286 ? ", 286" : "",2251 pWorker-> fFlags ? ", opsize" : "", pWorker->cbInstr, cbIdtr*2, pbBufSave);2286 Bs3TestFailedF("Mismatch (#3): loaded %04RX16:%08RX32, fillers %#x %#x%s, %s, got %.*Rhxs\n", 2287 s_aValues32[i].cbLimit, s_aValues32[i].u32Base, bFiller1, bFiller2, f286 ? ", 286" : "", 2288 pWorker->pszDesc, cbIdtr*2, pbBufSave); 2252 2289 } 2253 2290 g_usBs3TestStep++; 2254 2291 } 2255 2256 } 2257 2258 2259 2260 #if 0 2292 } 2261 2293 2262 2294 /* … … 2265 2297 for (off = 0; off < 8; off++) 2266 2298 { 2267 pbBuf = &abBuf[off]; 2268 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, &abBuf[off]); 2299 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, &abBufLoad[off]); 2269 2300 CtxUdExpected.rbx.u = Ctx.rbx.u; 2270 2301 2271 /* First with zero buffer. */ 2272 Bs3MemZero(abBuf, sizeof(abBuf)); 2302 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2303 Bs3MemCpy(&abBufLoad[off], pbBufRestore, cbIdtr); 2304 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2273 2305 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2274 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2275 if (off > 0 && !ASMMemIsZero(abBuf, off)) 2276 Bs3TestFailedF("Unexpected buffer bytes set before (#3): cbIdtr=%u off=%u abBuf=%.*Rhxs\n", 2277 cbIdtr, off, off + cbBuf, abBuf); 2278 if (!ASMMemIsZero(&abBuf[off + cbIdtr], sizeof(abBuf) - cbIdtr - off)) 2279 Bs3TestFailedF("Unexpected buffer bytes set after (#3): cbIdtr=%u off=%u abBuf=%.*Rhxs\n", 2280 cbIdtr, off, off + cbBuf, abBuf); 2281 if (f286 && abBuf[off + cbIdtr - 1] != 0xff) 2282 Bs3TestFailedF("286: Top base byte isn't 0xff (#3): %#x\n", abBuf[off + cbIdtr - 1]); 2283 if (Bs3MemCmp(&abBuf[off], pbExpected, cbIdtr) != 0) 2284 Bs3TestFailedF("Mismatch (#3): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &abBuf[off]); 2306 if (bRing != 0) 2307 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2308 else 2309 { 2310 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2311 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2312 Bs3TestFailedF("Mismatch (#4): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2313 } 2285 2314 g_usBs3TestStep++; 2286 2287 /* Again with a buffer filled with a byte not occuring in the previous result. */ 2288 Bs3MemSet(abBuf, bFiller, sizeof(abBuf)); 2289 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2290 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2291 if (off > 0 && !ASMMemIsAllU8(abBuf, off, bFiller)) 2292 Bs3TestFailedF("Unexpected buffer bytes set before (#4): cbIdtr=%u off=%u bFiller=%#x abBuf=%.*Rhxs\n", 2293 cbIdtr, off, bFiller, off + cbBuf, abBuf); 2294 if (!ASMMemIsAllU8(&abBuf[off + cbIdtr], sizeof(abBuf) - cbIdtr - off, bFiller)) 2295 Bs3TestFailedF("Unexpected buffer bytes set after (#4): cbIdtr=%u off=%u bFiller=%#x abBuf=%.*Rhxs\n", 2296 cbIdtr, off, bFiller, off + cbBuf, abBuf); 2297 if (Bs3MemChr(&abBuf[off], bFiller, cbIdtr) != NULL) 2298 Bs3TestFailedF("Not all bytes touched (#4): cbIdtr=%u off=%u bFiller=%#x abBuf=%.*Rhxs\n", 2299 cbIdtr, off, bFiller, off + cbBuf, abBuf); 2300 if (f286 && abBuf[off + cbIdtr - 1] != 0xff) 2301 Bs3TestFailedF("286: Top base byte isn't 0xff (#4): %#x\n", abBuf[off + cbIdtr - 1]); 2302 if (Bs3MemCmp(&abBuf[off], pbExpected, cbIdtr) != 0) 2303 Bs3TestFailedF("Mismatch (#4): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &abBuf[off]); 2304 g_usBs3TestStep++; 2305 } 2306 pbBuf = abBuf; 2307 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, abBuf); 2315 } 2316 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, abBufLoad); 2308 2317 CtxUdExpected.rbx.u = Ctx.rbx.u; 2309 2318 … … 2316 2325 { 2317 2326 uint16_t cbLimit; 2318 uint32_t uFlatBuf = Bs3SelPtrToFlat(abBuf );2327 uint32_t uFlatBuf = Bs3SelPtrToFlat(abBufLoad); 2319 2328 Bs3GdteTestPage00 = Bs3Gdte_DATA16; 2320 2329 Bs3GdteTestPage00.Gen.u2Dpl = bRing; … … 2335 2344 { 2336 2345 Bs3GdteTestPage00.Gen.u16LimitLow = cbLimit; 2337 Bs3MemSet(abBuf, bFiller, sizeof(abBuf)); 2346 2347 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2348 Bs3MemCpy(&abBufLoad[off], pbBufRestore, cbIdtr); 2349 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2338 2350 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2339 if (off + cbIdtr <= cbLimit + 1) 2351 if (bRing != 0) 2352 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2353 else if (off + cbIdtr <= cbLimit + 1) 2340 2354 { 2341 2355 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2342 if (Bs3MemChr(&abBuf[off], bFiller, cbIdtr) != NULL) 2343 Bs3TestFailedF("Not all bytes touched (#5): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2344 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2345 if (Bs3MemCmp(&abBuf[off], pbExpected, cbIdtr) != 0) 2346 Bs3TestFailedF("Mismatch (#5): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &abBuf[off]); 2347 if (f286 && abBuf[off + cbIdtr - 1] != 0xff) 2348 Bs3TestFailedF("286: Top base byte isn't 0xff (#5): %#x\n", abBuf[off + cbIdtr - 1]); 2356 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2357 Bs3TestFailedF("Mismatch (#5): expected %.*Rhxs, got %.*Rhxs\n", 2358 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2349 2359 } 2360 else if (pWorker->fSs) 2361 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2350 2362 else 2351 { 2352 if (pWorker->fSs) 2353 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2354 else 2355 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2356 if (off + 2 <= cbLimit + 1) 2357 { 2358 if (Bs3MemChr(&abBuf[off], bFiller, 2) != NULL) 2359 Bs3TestFailedF("Limit bytes not touched (#6): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2360 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2361 if (Bs3MemCmp(&abBuf[off], pbExpected, 2) != 0) 2362 Bs3TestFailedF("Mismatch (#6): expected %.2Rhxs, got %.2Rhxs\n", pbExpected, &abBuf[off]); 2363 if (!ASMMemIsAllU8(&abBuf[off + 2], cbIdtr - 2, bFiller)) 2364 Bs3TestFailedF("Base bytes touched on #GP (#6): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2365 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2366 } 2367 else if (!ASMMemIsAllU8(abBuf, sizeof(abBuf), bFiller)) 2368 Bs3TestFailedF("Bytes touched on #GP: cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2369 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2370 } 2371 2372 if (off > 0 && !ASMMemIsAllU8(abBuf, off, bFiller)) 2373 Bs3TestFailedF("Leading bytes touched (#7): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2374 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2375 if (!ASMMemIsAllU8(&abBuf[off + cbIdtr], sizeof(abBuf) - off - cbIdtr, bFiller)) 2376 Bs3TestFailedF("Trailing bytes touched (#7): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2377 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2378 2363 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2379 2364 g_usBs3TestStep++; 2365 2366 /* Again with zero limit and messed up base (should trigger tripple fault if partially loaded). */ 2367 abBufLoad[off] = abBufLoad[off + 1] = 0; 2368 abBufLoad[off + 2] |= 1; 2369 abBufLoad[off + cbIdtr - 2] ^= 0x5a; 2370 abBufLoad[off + cbIdtr - 1] ^= 0xa5; 2371 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2372 if (bRing != 0) 2373 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2374 else if (off + cbIdtr <= cbLimit + 1) 2375 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2376 else if (pWorker->fSs) 2377 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2378 else 2379 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2380 2380 } 2381 2381 } … … 2394 2394 { 2395 2395 Bs3GdteTestPage00.Gen.u16LimitLow = cbLimit; 2396 Bs3MemSet(abBuf, bFiller, sizeof(abBuf)); 2396 2397 Bs3MemSet(abBufLoad, bFiller1, sizeof(abBufLoad)); 2398 Bs3MemCpy(&abBufLoad[off], pbBufRestore, cbIdtr); 2399 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2397 2400 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2398 2399 if (off > cbLimit) 2401 if (bRing != 0) 2402 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2403 else if (off > cbLimit) 2400 2404 { 2401 2405 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2402 if (Bs3MemChr(&abBuf[off], bFiller, cbIdtr) != NULL) 2403 Bs3TestFailedF("Not all bytes touched (#8): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2404 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2405 if (Bs3MemCmp(&abBuf[off], pbExpected, cbIdtr) != 0) 2406 Bs3TestFailedF("Mismatch (#8): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &abBuf[off]); 2407 if (f286 && abBuf[off + cbIdtr - 1] != 0xff) 2408 Bs3TestFailedF("286: Top base byte isn't 0xff (#8): %#x\n", abBuf[off + cbIdtr - 1]); 2406 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2407 Bs3TestFailedF("Mismatch (#6): expected %.*Rhxs, got %.*Rhxs\n", 2408 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2409 2409 } 2410 else if (pWorker->fSs) 2411 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2410 2412 else 2411 { 2412 if (pWorker->fSs) 2413 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2414 else 2415 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2416 if (!ASMMemIsAllU8(abBuf, sizeof(abBuf), bFiller)) 2417 Bs3TestFailedF("Bytes touched on #GP: cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2418 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2419 } 2420 2421 if (off > 0 && !ASMMemIsAllU8(abBuf, off, bFiller)) 2422 Bs3TestFailedF("Leading bytes touched (#9): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2423 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2424 if (!ASMMemIsAllU8(&abBuf[off + cbIdtr], sizeof(abBuf) - off - cbIdtr, bFiller)) 2425 Bs3TestFailedF("Trailing bytes touched (#9): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x abBuf=%.*Rhxs\n", 2426 cbIdtr, off, cbLimit, bFiller, off + cbBuf, abBuf); 2427 2428 g_usBs3TestStep++; 2429 } 2430 } 2431 2432 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, abBuf); 2413 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2414 g_usBs3TestStep++; 2415 2416 /* Again with zero limit and messed up base (should trigger triple fault if partially loaded). */ 2417 abBufLoad[off] = abBufLoad[off + 1] = 0; 2418 abBufLoad[off + 2] |= 3; 2419 abBufLoad[off + cbIdtr - 2] ^= 0x55; 2420 abBufLoad[off + cbIdtr - 1] ^= 0xaa; 2421 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2422 if (bRing != 0) 2423 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2424 else if (off > cbLimit) 2425 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2426 else if (pWorker->fSs) 2427 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2428 else 2429 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2430 } 2431 } 2432 2433 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, abBufLoad); 2433 2434 CtxUdExpected.rbx.u = Ctx.rbx.u; 2434 2435 CtxUdExpected.ss = Ctx.ss; … … 2446 2447 2447 2448 /* 2448 * Slide the buffer towards the trailing guard page. We'll observe the 2449 * first word being written entirely separately from the 2nd dword/qword. 2449 * Slide the load buffer towards the trailing guard page. 2450 2450 */ 2451 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, &pbTest[X86_PAGE_SIZE]); 2452 CtxUdExpected.ss = Ctx.ss; 2453 CtxUdExpected.ds = Ctx.ds; 2451 2454 for (off = X86_PAGE_SIZE - cbIdtr - 4; off < X86_PAGE_SIZE + 4; off++) 2452 2455 { 2453 Bs3MemSet(&pbTest[X86_PAGE_SIZE - cbIdtr * 2], bFiller, cbIdtr * 2); 2456 Bs3MemSet(&pbTest[X86_PAGE_SIZE - cbIdtr * 2], bFiller1, cbIdtr*2); 2457 if (off < X86_PAGE_SIZE) 2458 Bs3MemCpy(&pbTest[off], pbBufRestore, RT_MIN(X86_PAGE_SIZE - off, cbIdtr)); 2454 2459 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, &pbTest[off]); 2460 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2455 2461 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2456 if (off + cbIdtr <= X86_PAGE_SIZE) 2462 if (bRing != 0) 2463 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2464 else if (off + cbIdtr <= X86_PAGE_SIZE) 2457 2465 { 2458 2466 CtxUdExpected.rbx = Ctx.rbx; 2459 CtxUdExpected.ss = Ctx.ss;2460 CtxUdExpected.ds = Ctx.ds;2461 2467 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2462 if (Bs3MemCmp(&pbTest[off], pbExpected, cbIdtr) != 0) 2463 Bs3TestFailedF("Mismatch (#9): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &pbTest[off]); 2468 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr*2) != 0) 2469 Bs3TestFailedF("Mismatch (#7): expected %.*Rhxs, got %.*Rhxs\n", 2470 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2464 2471 } 2465 2472 else 2466 { 2467 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2468 uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2469 if ( off <= X86_PAGE_SIZE - 2 2470 && Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) 2471 Bs3TestPrintf("Mismatch (#10): Expected limit %.2Rhxs, got %.2Rhxs; off=%#x\n", 2472 pbExpected, &pbTest[off], off); 2473 if ( off < X86_PAGE_SIZE - 2 2474 && !ASMMemIsAllU8(&pbTest[off + 2], X86_PAGE_SIZE - off - 2, bFiller)) 2475 Bs3TestPrintf("Wrote partial base on #PF (#10): bFiller=%#x, got %.*Rhxs; off=%#x\n", 2476 bFiller, X86_PAGE_SIZE - off - 2, &pbTest[off + 2], off); 2477 if (off == X86_PAGE_SIZE - 1 && pbTest[off] != bFiller) 2478 Bs3TestPrintf("Wrote partial limit on #PF (#10): Expected %02x, got %02x\n", bFiller, pbTest[off]); 2479 } 2473 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2480 2474 g_usBs3TestStep++; 2475 2476 /* Again with zero limit and maybe messed up base as well (triple fault if buggy). 2477 The 386DX-40 here triple faults (or something) with off == 0xffe, nothing else. */ 2478 if ( off < X86_PAGE_SIZE && off + cbIdtr > X86_PAGE_SIZE 2479 && ( off != X86_PAGE_SIZE - 2 2480 || (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) != BS3CPU_80386) 2481 ) 2482 { 2483 pbTest[off] = 0; 2484 if (off + 1 < X86_PAGE_SIZE) 2485 pbTest[off + 1] = 0; 2486 if (off + 2 < X86_PAGE_SIZE) 2487 pbTest[off + 2] |= 7; 2488 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2489 if (bRing != 0) 2490 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2491 else 2492 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2493 g_usBs3TestStep++; 2494 } 2481 2495 } 2482 2496 … … 2487 2501 for (off = cbIdtr + 4; off >= -cbIdtr - 4; off--) 2488 2502 { 2489 Bs3MemSet(pbTest, bFiller, 48); 2503 Bs3MemSet(pbTest, bFiller1, 48); 2504 if (off >= 0) 2505 Bs3MemCpy(&pbTest[off], pbBufRestore, cbIdtr); 2506 else if (off + cbIdtr > 0) 2507 Bs3MemCpy(pbTest, &pbBufRestore[-off], cbIdtr + off); 2490 2508 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, pWorker->fSs ? &Ctx.ss : &Ctx.ds, &pbTest[off]); 2509 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2491 2510 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2492 if (off >= 0) 2511 if (bRing != 0) 2512 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2513 else if (off >= 0) 2493 2514 { 2494 2515 CtxUdExpected.rbx = Ctx.rbx; 2495 CtxUdExpected.ss = Ctx.ss;2496 CtxUdExpected.ds = Ctx.ds;2497 2516 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2498 if (Bs3MemCmp(&pbTest[off], pbExpected, cbIdtr) != 0) 2499 Bs3TestFailedF("Mismatch (#11): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &pbTest[off]); 2517 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr*2) != 0) 2518 Bs3TestFailedF("Mismatch (#8): expected %.*Rhxs, got %.*Rhxs\n", 2519 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2500 2520 } 2501 2521 else 2502 { 2503 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), uFlatTest + off); 2504 if ( -off < cbIdtr 2505 && !ASMMemIsAllU8(pbTest, cbIdtr + off, bFiller)) 2506 Bs3TestPrintf("Wrote partial content on #PF (#12): bFiller=%#x, found %.*Rhxs; off=%d\n", 2507 bFiller, cbIdtr + off, pbTest, off); 2508 } 2509 if (!ASMMemIsAllU8(&pbTest[RT_MAX(cbIdtr + off, 0)], 16, bFiller)) 2510 Bs3TestPrintf("Wrote beyond expected area (#13): bFiller=%#x, found %.16Rhxs; off=%d\n", 2511 bFiller, &pbTest[RT_MAX(cbIdtr + off, 0)], off); 2522 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off); 2512 2523 g_usBs3TestStep++; 2524 2525 /* Again with messed up base as well (triple fault if buggy). */ 2526 if (off < 0 && off > -cbIdtr) 2527 { 2528 if (off + 2 >= 0) 2529 pbTest[off + 2] |= 15; 2530 pbTest[off + cbIdtr - 1] ^= 0xaa; 2531 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2532 if (bRing != 0) 2533 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2534 else 2535 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off); 2536 g_usBs3TestStep++; 2537 } 2513 2538 } 2514 2539 … … 2516 2541 * Combine paging and segment limit and check ordering. 2517 2542 * This is kind of interesting here since it the instruction seems to 2518 * be doing two separate writes.2543 * actually be doing two separate read, just like it's S[IG]DT counterpart. 2519 2544 */ 2520 2545 if ( !BS3_MODE_IS_RM_OR_V86(bTestMode) … … 2541 2566 { 2542 2567 Bs3GdteTestPage00.Gen.u16LimitLow = cbLimit; 2543 Bs3MemSet(&pbTest[X86_PAGE_SIZE - cbIdtr * 2], bFiller, cbIdtr * 2); 2568 Bs3MemSet(&pbTest[X86_PAGE_SIZE - cbIdtr * 2], bFiller1, cbIdtr * 2); 2569 if (off < X86_PAGE_SIZE) 2570 Bs3MemCpy(&pbTest[off], pbBufRestore, RT_MIN(cbIdtr, X86_PAGE_SIZE - off)); 2571 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2544 2572 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2545 if (off + cbIdtr <= cbLimit + 1) 2573 if (bRing != 0) 2574 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2575 else if (off + cbIdtr <= cbLimit + 1) 2546 2576 { 2547 2577 /* No #GP, but maybe #PF. */ … … 2549 2579 { 2550 2580 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2551 if (Bs3MemCmp( &pbTest[off], pbExpected, cbIdtr) != 0)2552 Bs3TestFailedF("Mismatch (# 14): expected %.*Rhxs, got %.*Rhxs\n",2553 cbIdtr , pbExpected, cbIdtr, &pbTest[off]);2581 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2582 Bs3TestFailedF("Mismatch (#9): expected %.*Rhxs, got %.*Rhxs\n", 2583 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2554 2584 } 2555 2585 else 2556 { 2557 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2558 uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2559 if ( off <= X86_PAGE_SIZE - 2 2560 && Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) 2561 Bs3TestPrintf("Mismatch (#15): Expected limit %.2Rhxs, got %.2Rhxs; off=%#x\n", 2562 pbExpected, &pbTest[off], off); 2563 cb = X86_PAGE_SIZE - off - 2; 2564 if ( off < X86_PAGE_SIZE - 2 2565 && !ASMMemIsAllU8(&pbTest[off + 2], cb, bFiller)) 2566 Bs3TestPrintf("Wrote partial base on #PF (#15): bFiller=%#x, got %.*Rhxs; off=%#x\n", 2567 bFiller, cb, &pbTest[off + 2], off); 2568 if (off == X86_PAGE_SIZE - 1 && pbTest[off] != bFiller) 2569 Bs3TestPrintf("Wrote partial limit on #PF (#15): Expected %02x, got %02x\n", bFiller, pbTest[off]); 2570 } 2586 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2571 2587 } 2572 else if (off + 2 <= cbLimit + 1) 2573 { 2574 /* [ig]tr.limit writing does not cause #GP, but may cause #PG, if not writing the base causes #GP. */ 2575 if (off <= X86_PAGE_SIZE - 2) 2576 { 2577 if (pWorker->fSs) 2578 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2579 else 2580 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2581 if (Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) 2582 Bs3TestPrintf("Mismatch (#16): Expected limit %.2Rhxs, got %.2Rhxs; off=%#x\n", 2583 pbExpected, &pbTest[off], off); 2584 cb = X86_PAGE_SIZE - off - 2; 2585 if ( off < X86_PAGE_SIZE - 2 2586 && !ASMMemIsAllU8(&pbTest[off + 2], cb, bFiller)) 2587 Bs3TestPrintf("Wrote partial base with limit (#16): bFiller=%#x, got %.*Rhxs; off=%#x\n", 2588 bFiller, cb, &pbTest[off + 2], off); 2589 } 2590 else 2591 { 2592 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2593 uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2594 if ( off < X86_PAGE_SIZE 2595 && !ASMMemIsAllU8(&pbTest[off], X86_PAGE_SIZE - off, bFiller)) 2596 Bs3TestPrintf("Mismatch (#16): Partial limit write on #PF: bFiller=%#x, got %.*Rhxs\n", 2597 bFiller, X86_PAGE_SIZE - off, &pbTest[off]); 2598 } 2599 } 2588 /* No #GP/#SS on limit, but instead #PF? */ 2589 else if (off < cbLimit && off >= 0xfff) 2590 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE)); 2591 /* #GP/#SS on limit or base. */ 2592 else if (pWorker->fSs) 2593 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2600 2594 else 2601 { 2602 /* #GP/#SS on limit. */ 2603 if (pWorker->fSs) 2604 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2605 else 2606 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2607 if ( off < X86_PAGE_SIZE 2608 && !ASMMemIsAllU8(&pbTest[off], X86_PAGE_SIZE - off, bFiller)) 2609 Bs3TestPrintf("Mismatch (#17): Partial write on #GP: bFiller=%#x, got %.*Rhxs\n", 2610 bFiller, X86_PAGE_SIZE - off, &pbTest[off]); 2611 } 2612 2613 cb = RT_MIN(cbIdtr * 2, off - (X86_PAGE_SIZE - cbIdtr*2)); 2614 if (!ASMMemIsAllU8(&pbTest[X86_PAGE_SIZE - cbIdtr * 2], cb, bFiller)) 2615 Bs3TestFailedF("Leading bytes touched (#18): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x pbTest=%.*Rhxs\n", 2616 cbIdtr, off, cbLimit, bFiller, cb, pbTest[X86_PAGE_SIZE - cbIdtr * 2]); 2595 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2617 2596 2618 2597 g_usBs3TestStep++; … … 2645 2624 { 2646 2625 Bs3GdteTestPage00.Gen.u16LimitLow = cbLimit; 2647 Bs3MemSet(&pbTest[X86_PAGE_SIZE], bFiller, cbIdtr * 2); 2626 Bs3MemSet(&pbTest[X86_PAGE_SIZE], bFiller1, cbIdtr * 2); 2627 if (off >= X86_PAGE_SIZE) 2628 Bs3MemCpy(&pbTest[off], pbBufRestore, cbIdtr); 2629 else if (off > X86_PAGE_SIZE - cbIdtr) 2630 Bs3MemCpy(&pbTest[X86_PAGE_SIZE], &pbBufRestore[X86_PAGE_SIZE - off], cbIdtr - (X86_PAGE_SIZE - off)); 2631 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2648 2632 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2649 if (cbLimit < off && off >= X86_PAGE_SIZE) 2633 if (bRing != 0) 2634 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2635 else if (cbLimit < off && off >= X86_PAGE_SIZE) 2650 2636 { 2651 2637 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2652 if (Bs3MemCmp(&pbTest[off], pbExpected, cbIdtr) != 0) 2653 Bs3TestFailedF("Mismatch (#19): expected %.*Rhxs, got %.*Rhxs\n", 2654 cbIdtr, pbExpected, cbIdtr, &pbTest[off]); 2655 cb = X86_PAGE_SIZE + cbIdtr*2 - off; 2656 if (!ASMMemIsAllU8(&pbTest[off + cbIdtr], cb, bFiller)) 2657 Bs3TestFailedF("Trailing bytes touched (#20): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x pbTest=%.*Rhxs\n", 2658 cbIdtr, off, cbLimit, bFiller, cb, pbTest[off + cbIdtr]); 2638 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2639 Bs3TestFailedF("Mismatch (#10): expected %.*Rhxs, got %.*Rhxs\n", 2640 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2659 2641 } 2642 else if (cbLimit < off && off < X86_PAGE_SIZE) 2643 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off); 2644 else if (pWorker->fSs) 2645 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2660 2646 else 2661 { 2662 if (cbLimit < off && off < X86_PAGE_SIZE) 2663 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2664 uFlatTest + off); 2665 else if (pWorker->fSs) 2666 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); 2667 else 2668 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2669 cb = cbIdtr*2; 2670 if (!ASMMemIsAllU8(&pbTest[X86_PAGE_SIZE], cb, bFiller)) 2671 Bs3TestFailedF("Trailing bytes touched (#20): cbIdtr=%u off=%u cbLimit=%u bFiller=%#x pbTest=%.*Rhxs\n", 2672 cbIdtr, off, cbLimit, bFiller, cb, pbTest[X86_PAGE_SIZE]); 2673 } 2647 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2674 2648 g_usBs3TestStep++; 2675 2649 } … … 2696 2670 { 2697 2671 Ctx.rbx.u = CtxUdExpected.rbx.u = UINT64_C(0x0000800000000000) + off; 2698 Bs3MemSet(&pbTest[-64], bFiller, 64*2); 2672 Bs3MemSet(&pbTest[-64], bFiller1, 64*2); 2673 Bs3MemCpy(&pbTest[off], pbBufRestore, cbIdtr); 2674 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2699 2675 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2700 if (off + cbIdtr <= 0) 2676 if (off + cbIdtr > 0 || bRing != 0) 2677 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2678 else 2701 2679 { 2702 2680 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2703 if (Bs3MemCmp(&pbTest[off], pbExpected, cbIdtr) != 0) 2704 Bs3TestFailedF("Mismatch (#21): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &pbTest[off]); 2705 } 2706 else 2707 { 2708 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2709 if (off <= -2 && Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) 2710 Bs3TestFailedF("Mismatch (#21): expected limit %.2Rhxs, got %.2Rhxs\n", pbExpected, &pbTest[off]); 2711 off2 = off <= -2 ? 2 : 0; 2712 cb = cbIdtr - off2; 2713 if (!ASMMemIsAllU8(&pbTest[off + off2], cb, bFiller)) 2714 Bs3TestFailedF("Mismatch (#21): touched base %.*Rhxs, got %.*Rhxs\n", 2715 cb, &pbExpected[off], cb, &pbTest[off + off2]); 2716 } 2717 if (!ASMMemIsAllU8(&pbTest[off - 16], 16, bFiller)) 2718 Bs3TestFailedF("Leading bytes touched (#21): bFiller=%#x, got %.16Rhxs\n", bFiller, &pbTest[off]); 2719 if (!ASMMemIsAllU8(&pbTest[off + cbIdtr], 16, bFiller)) 2720 Bs3TestFailedF("Trailing bytes touched (#21): bFiller=%#x, got %.16Rhxs\n", bFiller, &pbTest[off + cbIdtr]); 2681 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2682 Bs3TestFailedF("Mismatch (#18): expected %.*Rhxs, got %.*Rhxs\n", 2683 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2684 } 2721 2685 } 2722 2686 … … 2725 2689 { 2726 2690 Ctx.rbx.u = CtxUdExpected.rbx.u = UINT64_C(0xffff800000000000) + off; 2727 Bs3MemSet(&pbTest[-64], bFiller, 64*2); 2691 Bs3MemSet(&pbTest[-64], bFiller1, 64*2); 2692 Bs3MemCpy(&pbTest[off], pbBufRestore, cbIdtr); 2693 Bs3MemSet(abBufSave, bFiller2, sizeof(abBufSave)); 2728 2694 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 2729 if (off >= 0) 2695 if (off < 0 || bRing != 0) 2696 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2697 else 2730 2698 { 2731 2699 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxUdExpected); 2732 if (Bs3MemCmp(&pbTest[off], pbExpected, cbIdtr) != 0) 2733 Bs3TestFailedF("Mismatch (#22): expected %.*Rhxs, got %.*Rhxs\n", cbIdtr, pbExpected, cbIdtr, &pbTest[off]); 2734 } 2735 else 2736 { 2737 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2738 if (!ASMMemIsAllU8(&pbTest[off], cbIdtr, bFiller)) 2739 Bs3TestFailedF("Mismatch (#22): touched base %.*Rhxs, got %.*Rhxs\n", 2740 cbIdtr, &pbExpected[off], cbIdtr, &pbTest[off]); 2741 } 2742 if (!ASMMemIsAllU8(&pbTest[off - 16], 16, bFiller)) 2743 Bs3TestFailedF("Leading bytes touched (#22): bFiller=%#x, got %.16Rhxs\n", bFiller, &pbTest[off]); 2744 if (!ASMMemIsAllU8(&pbTest[off + cbIdtr], 16, bFiller)) 2745 Bs3TestFailedF("Trailing bytes touched (#22): bFiller=%#x, got %.16Rhxs\n", bFiller, &pbTest[off + cbIdtr]); 2746 } 2747 2748 } 2749 #endif 2700 if (Bs3MemCmp(pbBufSave, abExpectedFilled, cbIdtr * 2) != 0) 2701 Bs3TestFailedF("Mismatch (#19): expected %.*Rhxs, got %.*Rhxs\n", 2702 cbIdtr*2, abExpectedFilled, cbIdtr*2, pbBufSave); 2703 } 2704 } 2705 2706 } 2750 2707 } 2751 2708 … … 2765 2722 for (idx = 0; idx < cWorkers; idx++) 2766 2723 if ( (paWorkers[idx].bMode & (bTestMode & BS3_MODE_CODE_MASK)) 2767 && (!paWorkers[idx].fSs || bRing != 0 /** @todo || BS3_MODE_IS_64BIT_SYS(bTestMode)*/ )) 2724 && (!paWorkers[idx].fSs || bRing != 0 /** @todo || BS3_MODE_IS_64BIT_SYS(bTestMode)*/ ) 2725 && ( !(paWorkers[idx].fFlags & BS3CB2SIDTSGDT_F_386PLUS) 2726 || ( bTestMode > BS3_MODE_PE16 2727 || ( bTestMode == BS3_MODE_PE16 2728 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)) ) ) 2768 2729 { 2769 2730 //Bs3TestPrintf("idx=%-2d fpfnWorker=%p fSs=%d cbInstr=%d\n", … … 3151 3112 } 3152 3113 3153 #if 03154 3114 BS3_DECL_FAR(uint8_t) TMPL_NM(bs3CpuBasic2_lgdt)(uint8_t bMode) 3155 3115 { 3156 uint64_t const uOrgAddr = Bs3Lgdt_Gdt.uAddr;3157 uint64_t uNew = 0;3158 3116 union 3159 3117 { 3160 3118 RTGDTR Gdtr; 3161 uint8_t ab[ 16];3119 uint8_t ab[32]; /* At least cbIdtr*2! */ 3162 3120 } Expected; 3163 3121 … … 3165 3123 g_bTestMode = bMode; 3166 3124 g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE); 3125 3167 3126 BS3_ASSERT(bMode == TMPL_MODE); 3168 3127 … … 3170 3129 * Pass to common worker which is only compiled once per mode. 3171 3130 */ 3131 if (BS3_MODE_IS_RM_SYS(bMode)) 3132 ASMSetGDTR((PRTGDTR)&Bs3LgdtDef_Gdt); 3172 3133 Bs3MemZero(&Expected, sizeof(Expected)); 3173 3134 ASMGetGDTR(&Expected.Gdtr); 3174 bs3CpuBasic2_lidt_lgdt_Common(bMode, g_aSgdtWorkers, RT_ELEMENTS(g_aSgdtWorkers), Expected.ab); 3175 3176 /* 3177 * Unalias the GDT. 3178 */ 3179 if (uNew != 0) 3180 { 3181 Bs3Lgdt_Gdt.uAddr = uOrgAddr; 3182 Bs3UtilSetFullGdtr(Bs3Lgdt_Gdt.cb, uOrgAddr); 3183 Bs3PagingUnalias(uNew, Bs3Lgdt_Gdt.cb); 3184 } 3135 3136 bs3CpuBasic2_lidt_lgdt_Common(bMode, g_aLgdtWorkers, RT_ELEMENTS(g_aLgdtWorkers), 3137 &Bs3LgdtDef_Gdt, sizeof(Bs3LgdtDef_Gdt), Expected.ab); 3185 3138 3186 3139 /* … … 3190 3143 return 0; 3191 3144 } 3192 #endif3193 3145 3194 3146 #endif /* BS3_INSTANTIATING_MODE */ -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac
r60724 r60728 178 178 BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2 179 179 180 %if TMPL_BITS == 16 181 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2, BS3_PBC_NEAR 182 db X86_OP_PRF_SIZE_OP 183 lidt [xBX] 184 jmp dword BS3_SEL_R0_CS32:.in_32bit wrt FLAT 185 BS3_SET_BITS 32 186 .in_32bit: 187 sidt [es:edi] 188 lidt [es:esi] 189 jmp dword BS3_SEL_R0_CS16:.again wrt CGROUP16 190 BS3_SET_BITS 16 191 .again: 192 ud2 193 jmp .again 194 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2) == 27) 195 BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2 196 %endif 197 180 198 %if TMPL_BITS == 64 181 199 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR … … 227 245 228 246 247 ; 248 ; LGDT 249 ; 250 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 251 lgdt [xBX] 252 sgdt [BS3_NOT_64BIT(es:) xDI] 253 lgdt [BS3_NOT_64BIT(es:) xSI] 254 .again: 255 ud2 256 jmp .again 257 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(9,11)) 258 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2 259 260 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 261 db X86_OP_PRF_SIZE_OP 262 lgdt [xBX] 263 sgdt [BS3_NOT_64BIT(es:) xDI] 264 lgdt [BS3_NOT_64BIT(es:) xSI] 265 .again: 266 ud2 267 jmp .again 268 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(10,12)) 269 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2 270 271 %if TMPL_BITS == 64 272 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 273 db X86_OP_REX_W 274 lgdt [xBX] 275 sgdt [xDI] 276 lgdt [xSI] 277 .again: 278 ud2 279 jmp .again 280 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 10) 281 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2 282 283 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 284 db X86_OP_PRF_SIZE_OP 285 db X86_OP_REX_W 286 lgdt [xBX] 287 sgdt [xDI] 288 lgdt [xSI] 289 .again: 290 ud2 291 jmp .again 292 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 11) 293 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2 294 %endif 295 296 %if TMPL_BITS != 64 297 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 298 lgdt [ss:xBX] 299 sgdt [BS3_NOT_64BIT(es:) xDI] 300 lgdt [BS3_NOT_64BIT(es:) xSI] 301 .again: 302 ud2 303 jmp .again 304 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 12) 305 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2 306 307 BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR 308 db X86_OP_PRF_SIZE_OP 309 lgdt [ss:xBX] 310 sgdt [BS3_NOT_64BIT(es:) xDI] 311 lgdt [BS3_NOT_64BIT(es:) xSI] 312 .again: 313 ud2 314 jmp .again 315 AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 13) 316 BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2 317 %endif 318 319 229 320 %endif ; BS3_INSTANTIATING_CMN 230 321 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2.c
r60724 r60728 60 60 #endif 61 61 BS3TESTMODEENTRY_MODE("lidt", bs3CpuBasic2_lidt), 62 BS3TESTMODEENTRY_MODE("lgdt", bs3CpuBasic2_lgdt), 62 63 }; 63 64 -
trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-rm-InitAll.c
r60585 r60728 34 34 #include <iprt/asm-amd64-x86.h> 35 35 36 BS3_MODE_PROTO_NOSB(void, Bs3EnteredMode,(void)); 37 36 38 37 39 BS3_DECL(void) Bs3InitAll_rm(void) 38 40 { 41 uint32_t volatile BS3_FAR *pcTicks = (uint32_t volatile BS3_FAR *)BS3_FP_MAKE(0x40, 0x6c); 42 uint32_t cInitialTicks = *pcTicks; 43 int i = 3; 44 39 45 Bs3CpuDetect_rm_far(); 40 46 Bs3InitMemory_rm_far(); 41 47 Bs3InitGdt_rm_far(); 42 48 49 /* For for floppy to stop (a couple of ticks), then disable interrupts. */ 50 ASMIntEnable(); 51 while (i-- > 0) 52 { 53 while (*pcTicks == cInitialTicks) 54 ASMHalt(); 55 *pcTicks = cInitialTicks; 56 } 43 57 ASMIntDisable(); 44 58 Bs3PicMaskAll(); … … 51 65 Bs3Trap16Init(); 52 66 Bs3TrapRmV86Init(); 67 Bs3EnteredMode_rm(); 53 68 } 54 69
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