VirtualBox

Changeset 60689 in vbox


Ignore:
Timestamp:
Apr 25, 2016 1:43:42 PM (8 years ago)
Author:
vboxsync
Message:

VMM/APIC: Implemented old saved-state compatibility, eliminated unnecessary volatile members.

Location:
trunk
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/apic.h

    r60646 r60689  
    256256        struct
    257257        {
    258             uint32_t            u24Reserved0    : 24;
    259             uint32_t            u8LogicalApicId : 8;
     258            uint8_t             u8Reserved0[3];
     259            uint8_t             u8LogicalApicId;
    260260            uint32_t            u32Reserved0[3];
    261261        } u;
    … …  
    530530} XAPICPAGE;
    531531/** Pointer to a XAPICPAGE struct. */
    532 typedef volatile XAPICPAGE *PXAPICPAGE;
     532typedef XAPICPAGE *PXAPICPAGE;
    533533/** Pointer to a const XAPICPAGE struct. */
    534 typedef const volatile XAPICPAGE *PCXAPICPAGE;
     534typedef const XAPICPAGE *PCXAPICPAGE;
    535535AssertCompileSize(XAPICPAGE, 4096);
    536536AssertCompileMemberOffset(XAPICPAGE, id,          XAPIC_OFF_ID);
    … …  
    871871} X2APICPAGE;
    872872/** Pointer to a X2APICPAGE struct. */
    873 typedef volatile X2APICPAGE *PX2APICPAGE;
     873typedef X2APICPAGE *PX2APICPAGE;
    874874/** Pointer to a const X2APICPAGE struct. */
    875 typedef const volatile X2APICPAGE *PCX2APICPAGE;
     875typedef const X2APICPAGE *PCX2APICPAGE;
    876876AssertCompileSize(X2APICPAGE, 4096);
    877877AssertCompileSize(X2APICPAGE, sizeof(XAPICPAGE));

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r60655 r60689  
    24812481                 */
    24822482                apicSetVectorInPib(&pApicCpu->ApicPibLevel, uVector);
    2483                 uint32_t const fAlreadySet = apicSetNotificationBitInPib((PAPICPIB)&pApicCpu->ApicPibLevel);
     2483                uint32_t const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel);
    24842484                if (!fAlreadySet)
    24852485                    APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r60655 r60689  
    174174     * and AMD spec 16.3.2 "APIC Registers".
    175175     */
    176     memset((void *)&pXApicPage->irr,       0, sizeof(pXApicPage->irr));
    177     memset((void *)&pXApicPage->isr,       0, sizeof(pXApicPage->isr));
    178     memset((void *)&pXApicPage->tmr,       0, sizeof(pXApicPage->tmr));
    179     memset((void *)&pXApicPage->icr_hi,    0, sizeof(pXApicPage->icr_hi));
    180     memset((void *)&pXApicPage->icr_lo,    0, sizeof(pXApicPage->icr_lo));
    181     memset((void *)&pXApicPage->ldr,       0, sizeof(pXApicPage->ldr));
    182     memset((void *)&pXApicPage->tpr,       0, sizeof(pXApicPage->tpr));
    183     memset((void *)&pXApicPage->timer_icr, 0, sizeof(pXApicPage->timer_icr));
    184     memset((void *)&pXApicPage->timer_ccr, 0, sizeof(pXApicPage->timer_ccr));
    185     memset((void *)&pXApicPage->timer_dcr, 0, sizeof(pXApicPage->timer_dcr));
     176    RT_ZERO(pXApicPage->irr);
     177    RT_ZERO(pXApicPage->irr);
     178    RT_ZERO(pXApicPage->isr);
     179    RT_ZERO(pXApicPage->tmr);
     180    RT_ZERO(pXApicPage->icr_hi);
     181    RT_ZERO(pXApicPage->icr_lo);
     182    RT_ZERO(pXApicPage->ldr);
     183    RT_ZERO(pXApicPage->tpr);
     184    RT_ZERO(pXApicPage->timer_icr);
     185    RT_ZERO(pXApicPage->timer_ccr);
     186    RT_ZERO(pXApicPage->timer_dcr);
    186187
    187188    pXApicPage->dfr.u.u4Model        = XAPICDESTFORMAT_FLAT;
    … …  
    190191    /** @todo CMCI. */
    191192
    192     memset((void *)&pXApicPage->lvt_timer, 0, sizeof(pXApicPage->lvt_timer));
     193    RT_ZERO(pXApicPage->lvt_timer);
    193194    pXApicPage->lvt_timer.u.u1Mask = 1;
    194195
    195196#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
    196     memset((void *)&pXApicPage->lvt_thermal, 0, sizeof(pXApicPage->lvt_thermal));
     197    RT_ZERO(pXApicPage->lvt_thermal);
    197198    pXApicPage->lvt_thermal.u.u1Mask = 1;
    198199#endif
    199200
    200     memset((void *)&pXApicPage->lvt_perf, 0, sizeof(pXApicPage->lvt_perf));
     201    RT_ZERO(pXApicPage->lvt_perf);
    201202    pXApicPage->lvt_perf.u.u1Mask = 1;
    202203
    203     memset((void *)&pXApicPage->lvt_lint0, 0, sizeof(pXApicPage->lvt_lint0));
     204    RT_ZERO(pXApicPage->lvt_lint0);
    204205    pXApicPage->lvt_lint0.u.u1Mask = 1;
    205206
    206     memset((void *)&pXApicPage->lvt_lint1, 0, sizeof(pXApicPage->lvt_lint1));
     207    RT_ZERO(pXApicPage->lvt_lint1);
    207208    pXApicPage->lvt_lint1.u.u1Mask = 1;
    208209
    209     memset((void *)&pXApicPage->lvt_error, 0, sizeof(pXApicPage->lvt_error));
     210    RT_ZERO(pXApicPage->lvt_error);
    210211    pXApicPage->lvt_error.u.u1Mask = 1;
    211212
    212     memset((void *)&pXApicPage->svr, 0, sizeof(pXApicPage->svr));
     213    RT_ZERO(pXApicPage->svr);
    213214    pXApicPage->svr.u.u8SpuriousVector = 0xff;
    214215
    215216    /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
    216217    PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
    217     memset((void *)&pX2ApicPage->self_ipi, 0, sizeof(pX2ApicPage->self_ipi));
     218    RT_ZERO(pX2ApicPage->self_ipi);
    218219
    219220    /* Clear the pending-interrupt bitmaps. */
    220221    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    221     memset((void *)&pApicCpu->ApicPibLevel, 0, sizeof(APICPIB));
    222     memset((void *)pApicCpu->pvApicPibR3,   0, sizeof(APICPIB));
     222    RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
     223    RT_BZERO(pApicCpu->pvApicPibR3,  sizeof(APICPIB));
    223224}
    224225
    … …  
    347348    pHlp->pfnPrintf(pHlp, "\n");
    348349
    349     size_t cPending = 0;
     350    uint32_t cPending = 0;
    350351    pHlp->pfnPrintf(pHlp, "    Pending:\n");
    351352    pHlp->pfnPrintf(pHlp, "     ");
    … …  
    654655    LogRel(("APIC%u: uHintedTimerShift        = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
    655656
     657    PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
     658    LogRel(("APIC%u: uTimerICR                = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
     659    LogRel(("APIC%u: uTimerCCR                = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
     660
    656661    /* The PIBs. */
    657662    LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
    … …  
    720725
    721726/**
     727 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
     728 *
     729 * @returns VBox status code.
     730 * @param   pVM         The cross context VM structure.
     731 * @param   pVCpu       The cross context virtual CPU structure.
     732 * @param   pSSM        The SSM handle.
     733 * @param   uVersion    Data layout version.
     734 */
     735static int apicR3LoadLegacyVCpuData(PVM pVM, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
     736{
     737    AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
     738
     739    PAPICCPU   pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
     740    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     741
     742    uint32_t uApicBaseLo;
     743    int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
     744    AssertRCReturn(rc, rc);
     745    pApicCpu->uApicBaseMsr = uApicBaseLo;
     746
     747    switch (uVersion)
     748    {
     749        case APIC_SAVED_STATE_VERSION_ANCIENT:
     750        {
     751            uint8_t uPhysApicId;
     752            SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
     753            SSMR3GetU8(pSSM, &uPhysApicId);   NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
     754            break;
     755        }
     756
     757        case APIC_SAVED_STATE_VERSION_VBOX_50:
     758        case APIC_SAVED_STATE_VERSION_VBOX_30:
     759        {
     760            uint32_t uApicId, uPhysApicId, uArbId;
     761            SSMR3GetU32(pSSM, &uApicId);      pXApicPage->id.u8ApicId = uApicId;
     762            SSMR3GetU32(pSSM, &uPhysApicId);  NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
     763            SSMR3GetU32(pSSM, &uArbId);       NOREF(uArbId);      /* ArbID is & was unused. */
     764            break;
     765        }
     766
     767        default:
     768            return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
     769    }
     770
     771    uint32_t u32Tpr;
     772    SSMR3GetU32(pSSM, &u32Tpr);
     773    pXApicPage->tpr.u8Tpr = XAPIC_TPR_GET_TPR_FROM_U32(u32Tpr);
     774
     775    SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
     776    SSMR3GetU8(pSSM,  &pXApicPage->ldr.u.u8LogicalApicId);
     777
     778    uint8_t uDfr;
     779    SSMR3GetU8(pSSM,  &uDfr);
     780    pXApicPage->dfr.u.u4Model = uDfr >> 4;
     781
     782    AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
     783    AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
     784    AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
     785    for (size_t i = 0; i < 8; i++)
     786    {
     787        SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
     788        SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
     789        SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
     790    }
     791
     792    SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
     793    SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
     794    SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
     795    SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
     796    SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
     797    SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
     798
     799    SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
     800    SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
     801    SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
     802
     803    uint32_t u32TimerShift;
     804    SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
     805    SSMR3GetU32(pSSM, &u32TimerShift);
     806    uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
     807    AssertMsgReturn(u32TimerShift == uTimerShift, ("Timer shift invalid! Saved-state contains %u, expected %u\n", u32TimerShift,
     808                                                   uTimerShift), VERR_INVALID_STATE);
     809
     810    SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
     811    SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
     812    uint64_t uNextTS;
     813    rc = SSMR3GetU64(pSSM, &uNextTS);       AssertRCReturn(rc, rc);
     814    if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
     815        pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
     816
     817    rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
     818    AssertRCReturn(rc, rc);
     819    Assert(pApicCpu->uHintedTimerInitialCount == 0);
     820    Assert(pApicCpu->uHintedTimerShift == 0);
     821    if (TMTimerIsActive(pApicCpu->pTimerR3))
     822    {
     823        uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
     824        apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
     825    }
     826
     827    return rc;
     828}
     829
     830
     831/**
    722832 * @copydoc FNSSMDEVLIVEEXEC
    723833 */
    … …  
    773883
    774884        /* Save the timer. */
     885        SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
    775886        TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
    776         SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
    777887
    778888#ifdef DEBUG_ramshankar
    … …  
    793903    PVM      pVM      = PDMDevHlpGetVM(pDevIns);
    794904    PAPIC    pApic    = VM_TO_APIC(pVM);
     905
    795906    AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
    796 
    797     LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%u\n", uVersion, uPass));
     907    AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
     908
     909    LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
    798910
    799911    /* Weed out invalid versions. */
    … …  
    803915        &&  uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
    804916    {
     917        LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
    805918        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    806919    }
    807920
     921    int rc = VINF_SUCCESS;
    808922    if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
    809923    {
    810         int rc2 = apicR3LoadVMData(pVM, pSSM);
    811         AssertRCReturn(rc2, rc2);
     924        rc = apicR3LoadVMData(pVM, pSSM);
     925        AssertRCReturn(rc, rc);
    812926
    813927        if (uVersion == APIC_SAVED_STATE_VERSION)
    … …  
    815929    }
    816930
    817     if (uPass != SSM_PASS_FINAL)
    818         return VINF_SUCCESS;
    819 
    820     int rc = VINF_SUCCESS;
    821931    for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
    822932    {
    … …  
    832942            /* Load the APIC page. */
    833943            if (XAPIC_IN_X2APIC_MODE(pVCpu))
    834                 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
     944                SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
    835945            else
    836                 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
     946                SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
    837947
    838948            /* Load the PIBs. */
    839             SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPibR3,   &g_aApicPibFields[0]);
    840             SSMR3GetStruct(pSSM, (void *)&pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
     949            SSMR3GetStruct(pSSM, pApicCpu->pvApicPibR3,   &g_aApicPibFields[0]);
     950            SSMR3GetStruct(pSSM, &pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
    841951
    842952            /* Load the timer. */
     953            rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);     AssertRCReturn(rc, rc);
    843954            rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);           AssertRCReturn(rc, rc);
    844             rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);     AssertRCReturn(rc, rc);
    845955            Assert(pApicCpu->uHintedTimerShift == 0);
    846956            Assert(pApicCpu->uHintedTimerInitialCount == 0);
    … …  
    852962                apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
    853963            }
    854 
    855 #ifdef DEBUG_ramshankar
    856             apicR3DumpState(pVCpu, "Loaded state:");
    857 #endif
    858964        }
    859965        else
    860966        {
    861             /** @todo load & translate old per-VCPU data to new APIC code. */
    862             uint32_t uApicBaseMsrLo;
    863             SSMR3GetU32(pSSM, &uApicBaseMsrLo);
    864             pApicCpu->uApicBaseMsr = uApicBaseMsrLo;
     967            rc = apicR3LoadLegacyVCpuData(pVM, pVCpu, pSSM, uVersion);
     968            AssertRCReturn(rc, rc);
    865969        }
     970
     971#ifdef DEBUG_ramshankar
     972        char szLoadedState[128];
     973        RTStrPrintf(szLoadedState, sizeof(szLoadedState), "Loaded state (version %u):", uVersion);
     974        apicR3DumpState(pVCpu, &szLoadedState[0]);
     975#endif
    866976    }
    867977
    … …  
    10091119        size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
    10101120        if (cPages == 1)
    1011             SUPR3PageFreeEx((void *)pApic->pvApicPibR3, cPages);
     1121            SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
    10121122        else
    1013             SUPR3ContFree((void *)pApic->pvApicPibR3, cPages);
     1123            SUPR3ContFree(pApic->pvApicPibR3, cPages);
    10141124        pApic->pvApicPibR3 = NIL_RTR3PTR;
    10151125        pApic->pvApicPibR0 = NIL_RTR0PTR;
    … …  
    10291139        if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
    10301140        {
    1031             SUPR3PageFreeEx((void *)pApicCpu->pvApicPageR3, 1 /* cPages */);
     1141            SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
    10321142            pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
    10331143            pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
    … …  
    10681178        RT_ZERO(SupApicPib);
    10691179        SupApicPib.Phys = NIL_RTHCPHYS;
    1070         int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
     1180        int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
    10711181        if (RT_SUCCESS(rc))
    10721182        {
    … …  
    10891199
    10901200        /* Initialize the PIB. */
    1091         memset((void *)pApic->pvApicPibR3, 0, pApic->cbApicPib);
     1201        RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
    10921202
    10931203        /* Map the PIB into GC.  */
    … …  
    10951205        {
    10961206            pApic->pvApicPibRC = NIL_RTRCPTR;
    1097             int rc = MMR3HyperMapHCPhys(pVM, (void *)pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
     1207            int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
    10981208                                        "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
    10991209            if (RT_FAILURE(rc))
    … …  
    11261236            AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
    11271237            pApicCpu->cbApicPage = sizeof(XAPICPAGE);
    1128             int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
     1238            int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
    11291239                                      &SupApicPage);
    11301240            if (RT_SUCCESS(rc))
    … …  
    11371247                if (fNeedsGCMapping)
    11381248                {
    1139                     rc = MMR3HyperMapHCPhys(pVM, (void *)pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
     1249                    rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
    11401250                                            pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
    11411251                    if (RT_FAILURE(rc))
    … …  
    11581268
    11591269                /* Initialize the virtual-APIC state. */
    1160                 memset((void *)pApicCpu->pvApicPageR3, 0, pApicCpu->cbApicPage);
     1270                RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
    11611271                APICR3Reset(pVCpu, true /* fResetApicBaseMsr */);
    11621272

  • trunk/src/VBox/VMM/include/APICInternal.h

    r60652 r60689  
    109109/** TPR - Task-priority subclass. */
    110110#define XAPIC_TPR_TP_SUBCLASS                UINT32_C(0x0f)
    111 /** TPR - Get the task-priority class. */
     111/** TPR - Gets the task-priority class. */
    112112#define XAPIC_TPR_GET_TP(a_Tpr)              ((a_Tpr) & XAPIC_TPR_TP)
    113 /** TPR - Get the task-priority subclass. */
     113/** TPR - Gets the task-priority subclass. */
    114114#define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr)     ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)
     115/** TPR - Gets the TPR from its 32-bit register. */
     116#define XAPIC_TPR_GET_TPR_FROM_U32(a_32Tpr)  (((a_32Tpr) >> 24) & XAPIC_TPR)
    115117
    116118/** PPR - Valid bits. */
    … …  
    450452    RTR0MEMOBJ                  hMapObjApicPibR0;
    451453    /** The APIC PIB virtual address - R0 ptr. */
    452     R0PTRTYPE(volatile void *)  pvApicPibR0;
     454    R0PTRTYPE(void *)           pvApicPibR0;
    453455    /** The APIC PIB virtual address - R3 ptr. */
    454     R3PTRTYPE(volatile void *)  pvApicPibR3;
     456    R3PTRTYPE(void *)           pvApicPibR3;
    455457    /** The APIC PIB virtual address - RC ptr. */
    456     RCPTRTYPE(volatile void *)  pvApicPibRC;
     458    RCPTRTYPE(void *)           pvApicPibRC;
    457459    /** Alignment padding. */
    458460    RTRCPTR                     RCPtrAlignment1;
    … …  
    500502    RTR0MEMOBJ                  hMapObjApicPageR0;
    501503    /** The APIC page virtual address - R0 ptr. */
    502     R0PTRTYPE(volatile void *)  pvApicPageR0;
     504    R0PTRTYPE(void *)           pvApicPageR0;
    503505    /** The APIC page virtual address - R3 ptr. */
    504     R3PTRTYPE(volatile void *)  pvApicPageR3;
     506    R3PTRTYPE(void *)           pvApicPageR3;
    505507    /** The APIC page virtual address - RC ptr. */
    506     RCPTRTYPE(volatile void *)  pvApicPageRC;
     508    RCPTRTYPE(void *)           pvApicPageRC;
    507509    /** Alignment padding. */
    508510    RTRCPTR                     RCPtrAlignment0;
    … …  
    524526    RTHCPHYS                    HCPhysApicPib;
    525527    /** The APIC PIB virtual address - R0 ptr. */
    526     R0PTRTYPE(volatile void *)  pvApicPibR0;
     528    R0PTRTYPE(void *)           pvApicPibR0;
    527529    /** The APIC PIB virtual address - R3 ptr. */
    528     R3PTRTYPE(volatile void *)  pvApicPibR3;
     530    R3PTRTYPE(void *)           pvApicPibR3;
    529531    /** The APIC PIB virtual address - RC ptr. */
    530     RCPTRTYPE(volatile void *)  pvApicPibRC;
     532    RCPTRTYPE(void *)           pvApicPibRC;
    531533    /** Alignment padding. */
    532534    RTRCPTR                     RCPtrAlignment1;
    533535    /** The APIC PIB for level-sensitive interrupts. */
    534     volatile APICPIB            ApicPibLevel;
     536    APICPIB                     ApicPibLevel;
    535537    /** @} */
    536538
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