Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60651)
+++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60652)
@@ -1143,4 +1143,6 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
+    Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
+
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
         && (uTpr & ~XAPIC_TPR))
@@ -1362,7 +1364,7 @@
         pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
         if (uInitialCount)
-            APICStartTimer(pApicCpu, uInitialCount);
+            APICStartTimer(pVCpu, uInitialCount);
         else
-            APICStopTimer(pApicCpu);
+            APICStopTimer(pVCpu);
         TMTimerUnlock(pTimer);
     }
@@ -2162,5 +2164,4 @@
     AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
     AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
-    LogFlow(("APIC%u: APICLocalInterrupt\n", pVCpu->idCpu));
 
     VBOXSTRICTRC rcStrict = VINF_SUCCESS;
@@ -2248,5 +2249,5 @@
         {
             /* LINT0 behaves as an external interrupt pin. */
-            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s ExtINT through LINT0\n", pVCpu->idCpu,
+            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
                   u8Level ? "raising" : "lowering"));
             if (u8Level)
@@ -2258,5 +2259,5 @@
         {
             /* LINT1 behaves as NMI. */
-            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI through LINT1\n", pVCpu->idCpu));
+            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
             APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
         }
@@ -2483,12 +2484,13 @@
  * Starts the APIC timer.
  *
- * @param   pApicCpu        The APIC CPU state.
+ * @param   pVCpu           The cross context virtual CPU structure.
  * @param   uInitialCount   The timer's Initial-Count Register (ICR), must be >
  *                          0.
  * @thread  Any.
  */
-VMM_INT_DECL(void) APICStartTimer(PAPICCPU pApicCpu, uint32_t uInitialCount)
-{
-    Assert(pApicCpu);
+VMM_INT_DECL(void) APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
+{
+    Assert(pVCpu);
+    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
     Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
     Assert(uInitialCount > 0);
@@ -2497,4 +2499,7 @@
     uint8_t  const uTimerShift  = apicGetTimerShift(pXApicPage);
     uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
+
+    Log2(("APIC%u: APICStartTimer: uInitialCount=%u uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
+          uTimerShift, cTicksToNext));
 
     /*
@@ -2513,11 +2518,14 @@
  * Stops the APIC timer.
  *
- * @param   pApicCpu        The APIC CPU state.
+ * @param   pVCpu               The cross context virtual CPU structure.
  * @thread  Any.
  */
-VMM_INT_DECL(void) APICStopTimer(PAPICCPU pApicCpu)
-{
-    Assert(pApicCpu);
+VMM_INT_DECL(void) APICStopTimer(PVMCPU pVCpu)
+{
+    Assert(pVCpu);
+    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
     Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
+
+    Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
 
     PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
Index: /trunk/src/VBox/VMM/VMMR3/APIC.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 60651)
+++ /trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 60652)
@@ -260,5 +260,5 @@
     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
 
-    LogFlow(("APIC%u: APICR3Reset\n", pVCpu->idCpu));
+    LogFlow(("APIC%u: APICR3Reset: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
 
 #ifdef VBOX_STRICT
@@ -718,4 +718,6 @@
     PVM      pVM      = PDMDevHlpGetVM(pApicDev->pDevInsR3);
 
+    LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
+
     int rc = apicR3SaveVMData(pVM, pSSM);
     AssertRCReturn(rc, rc);
@@ -733,4 +735,6 @@
     PAPIC    pApic    = VM_TO_APIC(pVM);
     AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
+
+    LogFlow(("APIC: apicR3SaveExec\n"));
 
     /* Save per-VM data. */
@@ -781,4 +785,6 @@
     PAPIC    pApic    = VM_TO_APIC(pVM);
     AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
+
+    LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%u\n", uVersion, uPass));
 
     /* Weed out invalid versions. */
@@ -897,5 +903,5 @@
             {
                 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
-                APICStartTimer(pApicCpu, uInitialCount);
+                APICStartTimer(pVCpu, uInitialCount);
             }
             break;
@@ -927,4 +933,6 @@
     VM_ASSERT_EMT0(pVM);
     VM_ASSERT_IS_NOT_RUNNING(pVM);
+
+    LogFlow(("APIC: apicR3Reset\n"));
 
     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
Index: /trunk/src/VBox/VMM/include/APICInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/APICInternal.h	(revision 60651)
+++ /trunk/src/VBox/VMM/include/APICInternal.h	(revision 60652)
@@ -649,6 +649,6 @@
 
 VMM_INT_DECL(void)      APICPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode);
-VMM_INT_DECL(void)      APICStartTimer(PAPICCPU pApicCpu, uint32_t uInitialCount);
-VMM_INT_DECL(void)      APICStopTimer(PAPICCPU pApicCpu);
+VMM_INT_DECL(void)      APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount);
+VMM_INT_DECL(void)      APICStopTimer(PVMCPU pVCpu);
 VMM_INT_DECL(void)      APICUpdateCpuIdForMode(PVM pVM, APICMODE enmMode);