Changeset 60650 in vbox

Timestamp:

Apr 22, 2016 1:53:12 PM (8 years ago)

Author:

vboxsync

Message:

VMM/APIC: Log4 -> Log2.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (30 diffs)
• VMMR3/APIC.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -621 +621 @@
                 APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             else
-                Log4(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
+                Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
             break;
         }
@@ -631 +631 @@
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
                 {
-                    Log4(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
+                    Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
                 }
@@ -645 +645 @@
                     && apicIsEnabled(&pVM->aCpus[idCpu]))
                 {
-                    Log4(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
+                    Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
                 }
@@ -658 +658 @@
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
                 {
-                    Log4(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
+                    Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
                     VMMR3SendInitIpi(pVM, idCpu);
                 }
@@ -674 +674 @@
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
                 {
-                    Log4(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
+                    Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
                     VMMR3SendStartupIpi(pVM, idCpu, uVector);
                 }
@@ -689 +689 @@
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
                 {
-                    Log4(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
+                    Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
                 }
@@ -946 +946 @@
                     && enmTriggerMode  == XAPICTRIGGERMODE_LEVEL))
     {
-        Log4(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
+        Log2(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
         return VINF_SUCCESS;
     }
@@ -1007 +1007 @@
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
-    Log4(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
+    Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
 
     return VINF_SUCCESS;
@@ -1028 +1028 @@
     PXAPICPAGE pXApicPage  = VMCPU_TO_XAPICPAGE(pVCpu);
     pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR;
-    Log4(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
+    Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
 
     return apicSendIpi(pVCpu, rcRZ);
@@ -1072 +1072 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    Log4(("APIC%u: apicSetEr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
+    Log2(("APIC%u: apicSetEr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
 
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
@@ -1166 +1166 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    Log4(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
+    Log2(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
 
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
@@ -1192 +1192 @@
             }
 
-            Log4(("APIC%u: apicSetEoi: Acknowledged %s triggered interrupt. uVector=%#x\n", pVCpu->idCpu,
+            Log2(("APIC%u: apicSetEoi: Acknowledged %s triggered interrupt. uVector=%#x\n", pVCpu->idCpu,
                   fLevelTriggered ? "level" : "edge", uVector));
 
@@ -1217 +1217 @@
     Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
 
-    Log4(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
+    Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -1242 +1242 @@
     uDfr |= XAPIC_DFR_RSVD_MB1;
 
-    Log4(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
+    Log2(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -1264 +1264 @@
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
 
-    Log4(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
+    Log2(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -1349 +1349 @@
         return VINF_SUCCESS;
 
-    Log4(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
+    Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
 
     /*
@@ -1443 +1443 @@
         apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
 
-    Log4(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
+    Log2(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
 
     apicWriteRaw32(pXApicPage, offLvt, uLvt);
@@ -1979 +1979 @@
     uint64_t uBaseMsr   = pApicCpu->uApicBaseMsr;
 
-    Log4(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
+    Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
           apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
 
@@ -2017 +2017 @@
                 APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
                 uBaseMsr &= ~(MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT);
-                Log4(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
+                Log2(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
                 break;
             }
@@ -2029 +2029 @@
                 }
                 uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
-                Log4(("APIC%u: Switched mode to xApic\n", pVCpu->idCpu));
+                Log2(("APIC%u: Switched mode to xApic\n", pVCpu->idCpu));
                 break;
             }
@@ -2054 +2054 @@
                 pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
                                                   | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
-                Log4(("APIC%u: Switched mode to x2Apic\n", pVCpu->idCpu));
+                Log2(("APIC%u: Switched mode to x2Apic\n", pVCpu->idCpu));
                 break;
             }
@@ -2142 +2142 @@
     uint32_t          fBroadcastMask  = UINT32_C(0xff);
 
-    Log4(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s\n", fDestMask,
+    Log2(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s\n", fDestMask,
           apicGetDestModeName(enmDestMode), apicGetTriggerModeName(enmTriggerMode), apicGetDeliveryModeName(enmDeliveryMode)));
 
@@ -2220 +2220 @@
                 case XAPICDELIVERYMODE_EXTINT:
                 {
-                    Log4(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
+                    Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
                           u8Level ? "Raising" : "Lowering", u8Pin));
                     if (u8Level)
@@ -2248 +2248 @@
         {
             /* LINT0 behaves as an external interrupt pin. */
-            Log4(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s ExtINT through LINT0\n", pVCpu->idCpu,
+            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s ExtINT through LINT0\n", pVCpu->idCpu,
                   u8Level ? "raising" : "lowering"));
             if (u8Level)
@@ -2258 +2258 @@
         {
             /* LINT1 behaves as NMI. */
-            Log4(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI through LINT1\n", pVCpu->idCpu));
+            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI through LINT1\n", pVCpu->idCpu));
             APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
         }
@@ -2302 +2302 @@
             if (uTpr > 0 && uVector <= uTpr)
             {
-                Log4(("APIC%u: APICGetInterrupt: Spurious interrupt. uVector=%#x\n", pVCpu->idCpu,
+                Log2(("APIC%u: APICGetInterrupt: Spurious interrupt. uVector=%#x\n", pVCpu->idCpu,
                       pXApicPage->svr.u.u8SpuriousVector));
                 return pXApicPage->svr.u.u8SpuriousVector;
@@ -2316 +2316 @@
                 apicSignalNextPendingIntr(pVCpu);
 
-                Log4(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
+                Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
                 return uVector;
             }
             else
-                Log4(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR uVector=%#x PPR=%#x\n",
+                Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR uVector=%#x PPR=%#x\n",
                       pVCpu->idCpu, uVector, uPpr));
         }
         else
-            Log4(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
+            Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
     }
     else
-        Log4(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
+        Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
 
     return -1;
@@ -2352 +2352 @@
     *(uint32_t *)pv = uValue;
 
-    Log4(("APIC%u: ApicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    Log2(("APIC%u: ApicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     return rc;
 }
@@ -2373 +2373 @@
     STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
 
-    Log4(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    Log2(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
 
     int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
@@ -2445 +2445 @@
         if (!apicTestVectorInReg(&pXApicPage->irr, uVector))     /* PAV */
         {
-            Log4(("APIC%u: APICPostInterrupt: uVector=%#x\n", pVCpu->idCpu, uVector));
+            Log2(("APIC%u: APICPostInterrupt: uVector=%#x\n", pVCpu->idCpu, uVector));
             if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
             {

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -530 +530 @@
 
     uint32_t const uLvtError = pXApicPage->lvt_error.all.u32LvtError;
-    pHlp->pfnPrintf(pHlp, "LVT Perf           = %#RX32\n",   uLvtError);
+    pHlp->pfnPrintf(pHlp, "LVT Error          = %#RX32\n",   uLvtError);
     pHlp->pfnPrintf(pHlp, "  Vector           = %u (%#x)\n", pXApicPage->lvt_error.u.u8Vector, pXApicPage->lvt_error.u.u8Vector);
     pHlp->pfnPrintf(pHlp, "  Delivery status  = %u\n",       pXApicPage->lvt_error.u.u1DeliveryStatus);
@@ -882 +882 @@
     {
         uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
-        Log4(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
+        Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
         APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
     }
@@ -896 +896 @@
             if (uInitialCount)
             {
-                Log4(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
+                Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
                 APICStartTimer(pApicCpu, uInitialCount);
             }