Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60618)
+++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60619)
@@ -1304,5 +1304,5 @@
      */
     PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-    PTMTIMER  pTimer   = CTX_SUFF(pApicCpu->pTimer);
+    PTMTIMER  pTimer   = pApicCpu->CTX_SUFF(pTimer);
 
     int rc = TMTimerLock(pTimer, rcBusy);
@@ -1339,8 +1339,8 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    PAPIC      pApic      = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
+    PAPIC      pApic      = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     PAPICCPU   pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    PTMTIMER   pTimer     = CTX_SUFF(pApicCpu->pTimer);
+    PTMTIMER   pTimer     = pApicCpu->CTX_SUFF(pTimer);
 
     /* In TSC-deadline mode, timer ICR writes are ignored, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
@@ -1396,5 +1396,5 @@
      * and raise #GP(0) in x2APIC mode.
      */
-    PCAPIC pApic = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
+    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     if (offLvt == XAPIC_OFF_LVT_TIMER)
     {
@@ -2378,5 +2378,5 @@
 VMMDECL(void) APICSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
 {
-    PVM      pVM      = CTX_SUFF(pVCpu->pVM);
+    PVM      pVM      = pVCpu->CTX_SUFF(pVM);
     PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
     CTX_SUFF(pApicDev->pApicHlp)->pfnSetInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
@@ -2392,7 +2392,7 @@
 VMMDECL(void) APICClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
 {
-    PVM      pVM      = CTX_SUFF(pVCpu->pVM);
+    PVM      pVM      = pVCpu->CTX_SUFF(pVM);
     PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
-    CTX_SUFF(pApicDev->pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
+    pApicDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
 }
 
@@ -2481,5 +2481,5 @@
 {
     Assert(pApicCpu);
-    Assert(TMTimerIsLockOwner(CTX_SUFF(pApicCpu->pTimer)));
+    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
     Assert(uInitialCount > 0);
 
@@ -2494,5 +2494,5 @@
      * tick.
      */
-    PTMTIMER pTimer = CTX_SUFF(pApicCpu->pTimer);
+    PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
     TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
     apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
@@ -2509,7 +2509,7 @@
 {
     Assert(pApicCpu);
-    Assert(TMTimerIsLockOwner(CTX_SUFF(pApicCpu->pTimer)));
-
-    PTMTIMER pTimer = CTX_SUFF(pApicCpu->pTimer);
+    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
+
+    PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
     TMTimerStop(pTimer);    /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
     pApicCpu->uHintedTimerInitialCount = 0;
@@ -2572,5 +2572,6 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    PAPIC pApic = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
+    PVM   pVM   = pVCpu->CTX_SUFF(pVM);
+    PAPIC pApic = VM_TO_APIC(pVM);
     Assert(!pApic->fVirtApicRegsEnabled);
     NOREF(pApic);
@@ -2603,5 +2604,6 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    PAPIC pApic = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
+    PVM   pVM   = pVCpu->CTX_SUFF(pVM);
+    PAPIC pApic = VM_TO_APIC(pVM);
     Assert(!pApic->fVirtApicRegsEnabled);
     NOREF(pApic);
@@ -2639,5 +2641,5 @@
             break;
 
-        PAPICPIB pPib = (PAPICPIB)CTX_SUFF(pApicCpu->pvApicPib);
+        PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
         AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));