Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60572)
+++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60573)
@@ -629,5 +629,8 @@
             {
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
+                {
+                    Log4(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
+                }
             }
             break;
@@ -640,5 +643,8 @@
                 if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
                     && apicIsEnabled(&pVM->aCpus[idCpu]))
+                {
+                    Log4(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
+                }
             }
             break;
@@ -650,5 +656,8 @@
             for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
+                {
+                    Log4(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
                     VMMR3SendInitIpi(pVM, idCpu);
+                }
 #else
             /* We need to return to ring-3 to deliver the INIT. */
@@ -663,5 +672,8 @@
             for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
+                {
+                    Log4(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
                     VMMR3SendStartupIpi(pVM, idCpu, uVector);
+                }
 #else
             /* We need to return to ring-3 to deliver the SIPI. */
@@ -675,5 +687,8 @@
             for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
                 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
+                {
+                    Log4(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
                     APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
+                }
             break;
         }
@@ -911,8 +926,8 @@
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    XAPICDELIVERYMODE  const enmDeliveryMode  = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
+    XAPICDELIVERYMODE const  enmDeliveryMode  = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
     XAPICDESTMODE const      enmDestMode      = (XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode;
-    XAPICINITLEVEL           enmInitLevel     = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
-    XAPICTRIGGERMODE         enmTriggerMode   = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
+    XAPICINITLEVEL const     enmInitLevel     = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
+    XAPICTRIGGERMODE const   enmTriggerMode   = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
     XAPICDESTSHORTHAND const enmDestShorthand = (XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand;
     uint8_t const            uVector          = pXApicPage->icr_lo.u.u8Vector;
@@ -924,4 +939,5 @@
     /*
      * INIT Level De-assert is not support on Pentium 4 and Xeon processors.
+     * See AMD spec. 16.5 "Interprocessor Interrupts (IPI)" for a table of valid ICR combinations.
      */
     if (RT_UNLIKELY(   enmDeliveryMode == XAPICDELIVERYMODE_INIT_LEVEL_DEASSERT
@@ -929,9 +945,7 @@
                     && enmTriggerMode  == XAPICTRIGGERMODE_LEVEL))
     {
+        Log4(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
         return VINF_SUCCESS;
     }
-
-    enmInitLevel   = XAPICINITLEVEL_ASSERT;
-    enmTriggerMode = XAPICTRIGGERMODE_EDGE;
 #else
 # error "Implement Pentium and P6 family APIC architectures"
@@ -1015,6 +1029,5 @@
     Log4(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
 
-    apicSendIpi(pVCpu, rcRZ);
-    return VINF_SUCCESS;
+    return apicSendIpi(pVCpu, rcRZ);
 }
 
@@ -2263,5 +2276,6 @@
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    if (   apicIsEnabled(pVCpu)
+    bool const fApicHwEnabled = apicIsEnabled(pVCpu);
+    if (   fApicHwEnabled
         && pXApicPage->svr.u.fApicSoftwareEnable)
     {
@@ -2295,6 +2309,13 @@
                 return uVector;
             }
-        }
-    }
+            else
+                Log4(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR uVector=%#x PPR=%#x\n",
+                      pVCpu->idCpu, uVector, uPpr));
+        }
+        else
+            Log4(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
+    }
+    else
+        Log4(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
 
     return -1;
@@ -2318,8 +2339,8 @@
     STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead));
 
-    Log4(("APIC%u: ApicReadMmio: offReg=%#RX16\n", pVCpu->idCpu, offReg));
-
     int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue);
     *(uint32_t *)pv = uValue;
+
+    Log4(("APIC%u: ApicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     return rc;
 }
Index: /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp	(revision 60572)
+++ /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp	(revision 60573)
@@ -61,5 +61,7 @@
         uint32_t uTagSrc;
         int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uTagSrc);
+#ifndef VBOX_WITH_NEW_APIC
         AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
+#endif
         if (i >= 0)
         {
Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 60572)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 60573)
@@ -7444,6 +7444,8 @@
             else
             {
-                /** @todo Does this actually happen? If not turn it into an assertion. */
+                /* This can happen with the new APIC code. */
+#ifndef VBOX_WITH_NEW_APIC
                 Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)));
+#endif
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
             }
Index: /trunk/src/VBox/VMM/VMMR3/TRPM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/TRPM.cpp	(revision 60572)
+++ /trunk/src/VBox/VMM/VMMR3/TRPM.cpp	(revision 60573)
@@ -1555,5 +1555,7 @@
         else
         {
+#ifndef VBOX_WITH_NEW_APIC
             AssertRC(rc);
+#endif
             return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
         }