Index: /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
===================================================================
--- /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 60515)
+++ /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 60516)
@@ -792,4 +792,6 @@
     GEN_CHECK_OFF(APICCPU, StatMsrWriteR3);
     GEN_CHECK_OFF(APICCPU, StatMsrWriteRC);
+    GEN_CHECK_OFF(APICCPU, StatUpdatePendingIntrs);
+    GEN_CHECK_OFF(APICCPU, StatPostInterrupt);
 #else
     /* PC/DevAPIC.cpp */
Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60515)
+++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60516)
@@ -1081,5 +1081,5 @@
 static void apicUpdatePpr(PVMCPU pVCpu)
 {
-    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
 
     /* See Intel spec 10.8.3.1 "Task and Processor Priorities". */
@@ -1103,5 +1103,5 @@
 static uint8_t apicGetPpr(PVMCPU pVCpu)
 {
-    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
 
     /*
@@ -2394,7 +2394,11 @@
 {
     Assert(pVCpu);
+    Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
 
     PCAPIC   pApic    = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+
+    STAM_PROFILE_START(&pApicCpu->StatPostInterrupt, a);
+
     /* Validate the vector. See Intel spec. 10.5.2 "Valid Interrupt Vectors". */
     if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END))
@@ -2406,11 +2410,11 @@
             apicSetVectorInPib(CTX_SUFF(pApicCpu->pvApicPib), uVector);
             bool const fAlreadySet = apicSetNotificationBitInPib(CTX_SUFF(pApicCpu->pvApicPib));
-            if (fAlreadySet)
-                return;
-
-            if (pApic->fPostedIntrsEnabled)
-            { /** @todo posted-interrupt call to hardware */ }
-            else
-                APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
+            if (!fAlreadySet)
+            {
+                if (pApic->fPostedIntrsEnabled)
+                { /** @todo posted-interrupt call to hardware */ }
+                else
+                    APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
+            }
         }
         else
@@ -2422,12 +2426,12 @@
             apicSetVectorInPib(&pApicCpu->ApicPibLevel.aVectorBitmap[0], uVector);
             bool const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel.aVectorBitmap[0]);
-            if (fAlreadySet)
-                return;
-
-            APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
+            if (!fAlreadySet)
+                APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
         }
     }
     else
         apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
+
+    STAM_PROFILE_STOP(&pApicCpu->StatPostInterrupt, a);
 }
 
@@ -2537,4 +2541,5 @@
     PAPIC pApic = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
     Assert(!pApic->fVirtApicRegsEnabled);
+    NOREF(pApic);
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -2567,4 +2572,5 @@
     PAPIC pApic = VM_TO_APIC(CTX_SUFF(pVCpu->pVM));
     Assert(!pApic->fVirtApicRegsEnabled);
+    NOREF(pApic);
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -2591,4 +2597,6 @@
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
 
+    STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
+
     /* Update edge-triggered pending interrupts. */
     for (;;)
@@ -2628,4 +2636,6 @@
         }
     }
+
+    STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
 }
 
Index: /trunk/src/VBox/VMM/VMMR3/APIC.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 60515)
+++ /trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 60516)
@@ -411,5 +411,5 @@
     pHlp->pfnPrintf(pHlp, "    Recv Illegal Vector         = %RTbool\n",  pXApicPage->esr.u.fRcvdIllegalVector);
     pHlp->pfnPrintf(pHlp, "    Illegal Register Address    = %RTbool\n",  pXApicPage->esr.u.fIllegalRegAddr);
-    pHlp->pfnPrintf(pHlp, "  ICR Low                       = %#x\n",      pXApicPage->icr_lo.all);
+    pHlp->pfnPrintf(pHlp, "  ICR Low                       = %#x\n",      pXApicPage->icr_lo.all.u32IcrLo);
     pHlp->pfnPrintf(pHlp, "    Vector                      = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
                                                                           pXApicPage->icr_lo.u.u8Vector);
@@ -1295,4 +1295,11 @@
     } while(0)
 
+#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
+    do { \
+        rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
+                             idCpu); \
+        AssertRCReturn(rc, rc); \
+    } while(0)
+
     bool const fHasRC = !HMIsEnabled(pVM);
     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
@@ -1318,4 +1325,8 @@
             APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC,  "Number of APIC MSR writes in RC.",  "/Devices/APIC/%u/RC/MsrWrite");
         }
+
+        APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
+                          "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
+        APIC_PROF_COUNTER(&pApicCpu->StatPostInterrupt, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
     }
 # undef APIC_REG_ACCESS_COUNTER
Index: /trunk/src/VBox/VMM/include/APICInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/APICInternal.h	(revision 60515)
+++ /trunk/src/VBox/VMM/include/APICInternal.h	(revision 60516)
@@ -587,4 +587,9 @@
     /** Number of MSR writes in RC. */
     STAMCOUNTER                 StatMsrWriteRC;
+
+    /** Profiling of APICUpdatePendingInterrupts().  */
+    STAMPROFILE                 StatUpdatePendingIntrs;
+    /** Profiling of APICPostInterrupt().  */
+    STAMPROFILE                 StatPostInterrupt;
     /** @} */
 #endif