Index: /trunk/include/VBox/vmm/apic.h =================================================================== --- /trunk/include/VBox/vmm/apic.h (revision 60427) +++ /trunk/include/VBox/vmm/apic.h (revision 60428) @@ -49,5 +49,5 @@ #define MSR_APICBASE_BOOTSTRAP_CPU_BIT RT_BIT_64(8) /** The default APIC base address. */ -#define XAPIC_APICBASE_PHYSADDR (UINT64_C(0xfee00000) << PAGE_SHIFT) +#define XAPIC_APICBASE_PHYSADDR UINT64_C(0xfee00000) /** The APIC base MSR - Is the APIC enabled? */ #define MSR_APICBASE_IS_ENABLED(a_Msr) RT_BOOL((a_Msr) & MSR_APICBASE_XAPIC_ENABLE_BIT) Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp (revision 60427) +++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp (revision 60428) @@ -373,5 +373,5 @@ if (pXApicPage->svr.u.fApicSoftwareEnable) { - int const irrv = apicGetLastSetBit(&pXApicPage->irr, VERR_NOT_FOUND); + int const irrv = apicGetLastSetBit(&pXApicPage->irr, -1 /* rcNotFound */); if (irrv >= 0) { @@ -963,5 +963,5 @@ static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr) { - VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); + VMCPU_ASSERT_EMT(pVCpu); if ( XAPIC_IN_X2APIC_MODE(pVCpu) @@ -993,5 +993,5 @@ PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu); - int isrv = apicGetLastSetBit(&pXApicPage->isr, VERR_NOT_FOUND); + int isrv = apicGetLastSetBit(&pXApicPage->isr, -1 /* rcNotFound */); if (isrv >= 0) { @@ -1546,5 +1546,5 @@ return VINF_CPUM_R3_MSR_READ; - STAM_COUNTER_INC(&VMCPU_TO_APICCPU(pVCpu)->StatMsrWrite); + STAM_COUNTER_INC(&VMCPU_TO_APICCPU(pVCpu)->StatMsrRead); VBOXSTRICTRC rcStrict = VINF_SUCCESS; @@ -1904,5 +1904,5 @@ VMMDECL(uint8_t) APICGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu) { - VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); + VMCPU_ASSERT_EMT(pVCpu); PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu); return pXApicPage->tpr.u8Tpr; @@ -1961,4 +1961,6 @@ AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER); AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER); + + LogFlow(("APIC%u: APICLocalInterrupt\n", pVCpu->idCpu)); PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu); @@ -2006,4 +2008,8 @@ VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu); uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt); + + Log4(("APIC%u: APICLocalInterrupt: Sending interrupt. enmDeliveryMode=%u u8Pin=%u uVector=%u\n", + pVCpu->idCpu, enmDeliveryMode, u8Pin, uVector)); + rcStrict = apicSendIntr(pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ); break; @@ -2026,4 +2032,6 @@ { /* The APIC is disabled, pass it through the CPU. */ + LogFlow(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, passing interrupt to CPU. u8Pin=%u u8Level=%u\n", u8Pin, + u8Level)); if (u8Level) APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT); @@ -2052,4 +2060,6 @@ VMCPU_ASSERT_EMT(pVCpu); + LogFlow(("APIC%u: APICGetInterrupt\n", pVCpu->idCpu)); + PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu); if ( apicIsEnabled(pVCpu) @@ -2067,11 +2077,22 @@ uint8_t const uTpr = pXApicPage->tpr.u8Tpr; if (uTpr > 0 && uVector <= uTpr) + { + Log4(("APIC%u: APICGetInterrupt: Returns spurious vector %#x\n", pVCpu->idCpu, + pXApicPage->svr.u.u8SpuriousVector)); return pXApicPage->svr.u.u8SpuriousVector; - - apicClearVectorInReg(&pXApicPage->irr, uVector); - apicSetVectorInReg(&pXApicPage->isr, uVector); - apicUpdatePpr(pVCpu); - apicSignalNextPendingIntr(pVCpu); - return uVector; + } + + uint8_t const uPpr = pXApicPage->ppr.u8Ppr; + if ( !uPpr + || XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr)) + { + apicClearVectorInReg(&pXApicPage->irr, uVector); + apicSetVectorInReg(&pXApicPage->isr, uVector); + apicUpdatePpr(pVCpu); + apicSignalNextPendingIntr(pVCpu); + + Log4(("APIC%u: APICGetInterrupt: Returns vector %#x\n", pVCpu->idCpu, uVector)); + return uVector; + } } } @@ -2094,8 +2115,12 @@ uint16_t offReg = (GCPhysAddr & 0xff0); uint32_t uValue = 0; + #ifdef VBOX_WITH_STATISTICS PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); STAM_COUNTER_INC(&CTXSUFF(pApicCpu->StatMmioRead)); #endif + + Log4(("APIC%u: ApicReadMmio: offReg=%#RX16\n", pVCpu->idCpu, offReg)); + int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue); *(uint32_t *)pv = uValue; @@ -2117,8 +2142,12 @@ uint16_t offReg = (GCPhysAddr & 0xff0); uint32_t uValue = *(uint32_t *)pv; + #ifdef VBOX_WITH_STATISTICS PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu); STAM_COUNTER_INC(&CTXSUFF(pApicCpu->StatMmioWrite)); #endif + + LogRel(("APIC%u: APICWriteMmio: offReg=%#RX16\n", pVCpu->idCpu, offReg)); + int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue)); return rc; @@ -2177,4 +2206,5 @@ if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END)) { + Log4(("APIC%u: APICPostInterrupt: uVector=%#x\n", pVCpu->idCpu, uVector)); if (enmTriggerMode == XAPICTRIGGERMODE_EDGE) { Index: /trunk/src/VBox/VMM/VMMR3/APIC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/APIC.cpp (revision 60427) +++ /trunk/src/VBox/VMM/VMMR3/APIC.cpp (revision 60428) @@ -456,6 +456,6 @@ size_t cPending = 0; - pHlp->pfnPrintf(pHlp, " Pending\n"); - pHlp->pfnPrintf(pHlp, " "); + pHlp->pfnPrintf(pHlp, " Pending:\n"); + pHlp->pfnPrintf(pHlp, " "); for (ssize_t i = cFragments - 1; i >= 0; i--) { @@ -494,6 +494,6 @@ bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu); - pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC at %#RGp (%s mode):\n", pVCpu->idCpu, MSR_APICBASE_GET_PHYSADDR(pApicCpu->uApicBaseMsr), - fX2ApicMode ? "x2APIC" : "xAPIC"); + pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC at %#RGp\n", pVCpu->idCpu, MSR_APICBASE_GET_PHYSADDR(pApicCpu->uApicBaseMsr)); + pHlp->pfnPrintf(pHlp, " Mode = %s\n", fX2ApicMode ? "x2Apic" : "xApic"); if (fX2ApicMode) { @@ -537,5 +537,5 @@ pHlp->pfnPrintf(pHlp, " IRR\n"); apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp); - pHlp->pfnPrintf(pHlp, "ESR Internal = %#x\n", pApicCpu->uEsrInternal); + pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal); pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors); pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi); @@ -574,5 +574,5 @@ uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer; pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer); - pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector); + pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector); pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus); pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer)); @@ -626,4 +626,5 @@ apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint0.u.u1TriggerMode)); pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint0)); + pHlp->pfnPrintf(pHlp, "\n"); uint32_t const uLvtLint1 = pXApicPage->lvt_lint1.all.u32LvtLint1; @@ -665,5 +666,5 @@ pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue); pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage)); - pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64", pApicCpu->u64TimerInitial); + pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial); pHlp->pfnPrintf(pHlp, "\n"); @@ -1296,5 +1297,6 @@ PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]); RTGCPHYS GCPhysApicBase = MSR_APICBASE_GET_PHYSADDR(pApicCpu0->uApicBaseMsr); - rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), pVM, + LogRel(("APIC: PDMDevHlpMMIORegister new = %#RGp\n", GCPhysApicBase)); + rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, APICWriteMmio, APICReadMmio, "APIC");