Index: /trunk/include/VBox/vmm/em.h =================================================================== --- /trunk/include/VBox/vmm/em.h (revision 55247) +++ /trunk/include/VBox/vmm/em.h (revision 55248) @@ -193,8 +193,4 @@ VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen); VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx); -VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen); -VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx); -VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data); -VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu); VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); Index: /trunk/include/VBox/vmm/hm.h =================================================================== --- /trunk/include/VBox/vmm/hm.h (revision 55247) +++ /trunk/include/VBox/vmm/hm.h (revision 55248) @@ -208,4 +208,6 @@ VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM); # endif + +VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx); /** @} */ Index: /trunk/include/VBox/vmm/iem.h =================================================================== --- /trunk/include/VBox/vmm/iem.h (revision 55247) +++ /trunk/include/VBox/vmm/iem.h (revision 55248) @@ -51,4 +51,14 @@ +/** @name IEM status codes. + * + * Not quite sure how this will play out in the end, just aliasing safe status + * codes for now. + * + * @{ */ +#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE +/** @} */ + + VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu); VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten); @@ -72,4 +82,8 @@ VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode, bool fRepPrefix, uint8_t cbInstr); +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg); +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg); +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr); +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue); /** @} */ Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 55247) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 55248) @@ -1453,5 +1453,5 @@ /** @todo Clean up this mess. */ - LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val)); + LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val)); Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu)); switch (DestRegCrx) @@ -1610,5 +1610,5 @@ * */ -VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen) +static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen) { uint64_t val; @@ -1629,45 +1629,4 @@ return VERR_EM_INTERPRETER; -} - -/** - * Interpret LMSW. - * - * @returns VBox status code. - * @param pVM Pointer to the VM. - * @param pVCpu Pointer to the VMCPU. - * @param pRegFrame The register frame. - * @param u16Data LMSW source data. - * - */ -VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data) -{ - Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu)); - uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu); - - /* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */ - uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) - | (u16Data & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)); - - return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0); -} - - -/** - * Interpret CLTS. - * - * @returns VBox status code. - * @param pVM Pointer to the VM. - * @param pVCpu Pointer to the VMCPU. - * - */ -VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu) -{ - NOREF(pVM); - - uint64_t cr0 = CPUMGetGuestCR0(pVCpu); - if (!(cr0 & X86_CR0_TS)) - return VINF_SUCCESS; - return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS); } @@ -1805,5 +1764,5 @@ * */ -VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx) +static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx) { Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu)); @@ -3351,6 +3310,10 @@ static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) { - NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize); - return EMInterpretCLTS(pVM, pVCpu); + NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize); + + uint64_t cr0 = CPUMGetGuestCR0(pVCpu); + if (!(cr0 & X86_CR0_TS)) + return VINF_SUCCESS; + return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS); } @@ -3364,4 +3327,5 @@ uint32_t val; NOREF(pvFault); NOREF(pcbSize); + Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu)); int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, ¶m1, DISQPVWHICH_SRC); @@ -3383,5 +3347,12 @@ LogFlow(("emInterpretLmsw %x\n", val)); - return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val); + uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu); + + /* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */ + uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) + | (val & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)); + + return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0); + } @@ -3446,8 +3417,8 @@ NOREF(pvFault); NOREF(pcbSize); if ((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR) - return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg); + return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg); if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64)) - return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg); + return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg); AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER); Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 55247) +++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 55248) @@ -189,13 +189,4 @@ * Defined Constants And Macros * *******************************************************************************/ -/** @name IEM status codes. - * - * Not quite sure how this will play out in the end, just aliasing safe status - * codes for now. - * - * @{ */ -#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE -/** @} */ - /** Temporary hack to disable the double execution. Will be removed in favor * of a dedicated execution mode in EM. */ @@ -1106,4 +1097,5 @@ if (cbToTryRead > sizeof(pIemCpu->abOpcode) - pIemCpu->cbOpcode) cbToTryRead = sizeof(pIemCpu->abOpcode) - pIemCpu->cbOpcode; +/** @todo r=bird: Convert assertion into undefined opcode exception? */ Assert(cbToTryRead >= cbMin - cbLeft); /* ASSUMPTION based on iemInitDecoderAndPrefetchOpcodes. */ @@ -1201,10 +1193,11 @@ { uint8_t const offOpcode = pIemCpu->offOpcode; - if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode)) - return iemOpcodeGetNextU8Slow(pIemCpu, pu8); - - *pu8 = pIemCpu->abOpcode[offOpcode]; - pIemCpu->offOpcode = offOpcode + 1; - return VINF_SUCCESS; + if (RT_LIKELY(offOpcode < pIemCpu->cbOpcode)) + { + *pu8 = pIemCpu->abOpcode[offOpcode]; + pIemCpu->offOpcode = offOpcode + 1; + return VINF_SUCCESS; + } + return iemOpcodeGetNextU8Slow(pIemCpu, pu8); } @@ -3859,4 +3852,8 @@ { PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); +#ifdef IN_RING0 + int rc = HMR0EnsureCompleteBasicContext(IEMCPU_TO_VMCPU(pIemCpu), pCtx); + AssertRCReturn(rc, rc); +#endif /* @@ -11237,2 +11234,92 @@ } + + +/** + * Interface for HM and EM to write to a CRx register. + * + * @returns Strict VBox status code. + * @param pVCpu The cross context per virtual CPU structure. + * @param cbInstr The instruction length in bytes. + * @param iCrReg The control register number (destination). + * @param iGReg The general purpose register number (source). + * + * @remarks In ring-0 not all of the state needs to be synced in. + */ +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg) +{ + AssertReturn(cbInstr - 2U <= 15U - 2U, VERR_IEM_INVALID_INSTR_LENGTH); + Assert(iCrReg < 16); + Assert(iGReg < 16); + + PIEMCPU pIemCpu = &pVCpu->iem.s; + iemInitExec(pIemCpu, false /*fBypassHandlers*/); + VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_mov_Cd_Rd, iCrReg, iGReg); + return iemExecStatusCodeFiddling(pIemCpu, rcStrict); +} + + +/** + * Interface for HM and EM to read from a CRx register. + * + * @returns Strict VBox status code. + * @param pVCpu The cross context per virtual CPU structure. + * @param cbInstr The instruction length in bytes. + * @param iGReg The general purpose register number (destination). + * @param iCrReg The control register number (source). + * + * @remarks In ring-0 not all of the state needs to be synced in. + */ +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg) +{ + AssertReturn(cbInstr - 2U <= 15U - 2U, VERR_IEM_INVALID_INSTR_LENGTH); + Assert(iCrReg < 16); + Assert(iGReg < 16); + + PIEMCPU pIemCpu = &pVCpu->iem.s; + iemInitExec(pIemCpu, false /*fBypassHandlers*/); + VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_mov_Rd_Cd, iGReg, iCrReg); + return iemExecStatusCodeFiddling(pIemCpu, rcStrict); +} + + +/** + * Interface for HM and EM to clear the CR0[TS] bit. + * + * @returns Strict VBox status code. + * @param pVCpu The cross context per virtual CPU structure. + * @param cbInstr The instruction length in bytes. + * + * @remarks In ring-0 not all of the state needs to be synced in. + */ +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPU pVCpu, uint8_t cbInstr) +{ + AssertReturn(cbInstr - 2U <= 15U - 2U, VERR_IEM_INVALID_INSTR_LENGTH); + + PIEMCPU pIemCpu = &pVCpu->iem.s; + iemInitExec(pIemCpu, false /*fBypassHandlers*/); + VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_clts); + return iemExecStatusCodeFiddling(pIemCpu, rcStrict); +} + + +/** + * Interface for HM and EM to emulate the LMSW instruction (loads CR0). + * + * @returns Strict VBox status code. + * @param pVCpu The cross context per virtual CPU structure. + * @param cbInstr The instruction length in bytes. + * @param uValue The value to load into CR0. + * + * @remarks In ring-0 not all of the state needs to be synced in. + */ +VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPU pVCpu, uint8_t cbInstr, uint16_t uValue) +{ + AssertReturn(cbInstr - 3U <= 15U - 3U, VERR_IEM_INVALID_INSTR_LENGTH); + + PIEMCPU pIemCpu = &pVCpu->iem.s; + iemInitExec(pIemCpu, false /*fBypassHandlers*/); + VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_1(iemCImpl_lmsw, uValue); + return iemExecStatusCodeFiddling(pIemCpu, rcStrict); +} + Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 55247) +++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 55248) @@ -6750,4 +6750,26 @@ return rc; +} + + +/** + * Ensures that we've got a complete basic context. + * + * This excludes the FPU, SSE, AVX, and similar extended state. The interface + * is for the interpreter. + * + * @returns VBox status code. + * @param pVCpu Pointer to the VMCPU of the calling EMT. + * @param pMixedCtx Pointer to the guest-CPU context which may have data + * needing to be synced in. + * @thread EMT(pVCpu) + */ +VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx) +{ + /* Note! Since this is only applicable to VT-x, the implementation is placed + in the VT-x part of the sources instead of the generic stuff. */ + if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported) + return hmR0VmxSaveGuestState(pVCpu, pMixedCtx); + return VINF_SUCCESS; } @@ -10928,4 +10950,5 @@ STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2); int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient); + rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient); AssertRCReturn(rc, rc); @@ -10933,28 +10956,24 @@ uint32_t const uAccessType = VMX_EXIT_QUALIFICATION_CRX_ACCESS(uExitQualification); PVM pVM = pVCpu->CTX_SUFF(pVM); + VBOXSTRICTRC rcStrict; + rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx); + rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* Only really need CS+SS. */ switch (uAccessType) { case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE: /* MOV to CRx */ { -#if 0 - /* EMInterpretCRxWrite() references a lot of guest state (EFER, RFLAGS, Segment Registers, etc.) Sync entire state */ - rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx); -#else - rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx); rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); - rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); -#endif AssertRCReturn(rc, rc); - rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), - VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification), - VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification)); - Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3); - + rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr, + VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification), + VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification)); + AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE + || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)) { case 0: /* CR0 */ HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); - Log4(("CRX CR0 write rc=%d CR0=%#RX64\n", rc, pMixedCtx->cr0)); + Log4(("CRX CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr0)); break; case 2: /* CR2 */ @@ -10964,13 +10983,13 @@ Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx)); HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3); - Log4(("CRX CR3 write rc=%d CR3=%#RX64\n", rc, pMixedCtx->cr3)); + Log4(("CRX CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr3)); break; case 4: /* CR4 */ HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4); - Log4(("CRX CR4 write rc=%d CR4=%#RX64\n", rc, pMixedCtx->cr4)); + Log4(("CRX CR4 write rc=%Rrc CR4=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr4)); break; case 8: /* CR8 */ Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)); - /* CR8 contains the APIC TPR. Was updated by EMInterpretCRxWrite(). */ + /* CR8 contains the APIC TPR. Was updated by IEMExecDecodedMovCRxWrite(). */ HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE); break; @@ -10986,8 +11005,7 @@ case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ: /* MOV from CRx */ { - /* EMInterpretCRxRead() requires EFER MSR, CS. */ - rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); AssertRCReturn(rc, rc); + Assert( !pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx) @@ -10998,10 +11016,11 @@ || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)); - rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), - VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification), - VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)); - Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER); + rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr, + VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification), + VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)); + AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]); - Log4(("CRX CR%d Read access rc=%d\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification), rc)); + Log4(("CRX CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification), + VBOXSTRICTRC_VAL(rcStrict))); break; } @@ -11009,11 +11028,11 @@ case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */ { - rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); + rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); AssertRCReturn(rc, rc); - rc = EMInterpretCLTS(pVM, pVCpu); - AssertRCReturn(rc, rc); + rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr); + AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts); - Log4(("CRX CLTS write rc=%d\n", rc)); + Log4(("CRX CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict))); break; } @@ -11021,32 +11040,22 @@ case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */ { - rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); + rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); AssertRCReturn(rc, rc); - rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification)); - if (RT_LIKELY(rc == VINF_SUCCESS)) - HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); + rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr, + VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification)); + AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw); - Log4(("CRX LMSW write rc=%d\n", rc)); + Log4(("CRX LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict))); break; } default: - { - AssertMsgFailed(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType)); - rc = VERR_VMX_UNEXPECTED_EXCEPTION; - } - } - - /* Validate possible error codes. */ - Assert(rc == VINF_SUCCESS || rc == VINF_PGM_CHANGE_MODE || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_SYNC_CR3 - || rc == VERR_VMX_UNEXPECTED_EXCEPTION); - if (RT_SUCCESS(rc)) - { - int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient); - AssertRCReturn(rc2, rc2); - } - + AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType), + VERR_VMX_UNEXPECTED_EXCEPTION); + } + + HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST); STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2); - return rc; + return VBOXSTRICTRC_TODO(rcStrict); }