Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 55113) +++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 55114) @@ -647,5 +647,22 @@ /* - * Allocate memory for the extended CPU state. + * Figure out which XSAVE/XRSTOR features are available on the host. + */ + uint64_t fXStateHostMask = 0; + if ( pVM->cpum.s.HostFeatures.fXSaveRstor + && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor) + { + fXStateHostMask = ASMGetXcr0() & ( XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK + | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI); + AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE), + ("%#llx\n", fXStateHostMask), fXStateHostMask = 0); + } + pVM->cpum.s.fXStateHostMask = fXStateHostMask; + if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */ + fXStateHostMask = 0; + LogRel(("CPUML: fXStateHostMask=%#llx; initial: %#llx\n", pVM->cpum.s.fXStateHostMask, fXStateHostMask)); + + /* + * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask. */ uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState; @@ -676,4 +693,6 @@ pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates); pbXStates += cbMaxXState; + + pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask; } Index: /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (revision 55113) +++ /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (revision 55114) @@ -1509,5 +1509,5 @@ /* Linear sub-leaf search. Lazy as usual. */ - cLeaves = pLeaf - paLeaves; + cLeaves -= pLeaf - paLeaves; while ( cLeaves-- > 0 && pLeaf->uLeaf == uLeaf) @@ -1529,12 +1529,16 @@ AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1); AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1); - - pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax, - paLeaves[0].uEbx, - paLeaves[0].uEcx, - paLeaves[0].uEdx); - pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax); - pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL); - pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax); + PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0); + AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1); + PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0); + AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1); + + pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax, + pStd0Leaf->uEbx, + pStd0Leaf->uEcx, + pStd0Leaf->uEdx); + pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax); + pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL); + pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax); pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor, pFeatures->uFamily, @@ -1545,5 +1549,5 @@ if (pLeaf) pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff; - else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36) + else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36) pFeatures->cMaxPhysAddrWidth = 36; else @@ -1551,25 +1555,26 @@ /* Standard features. */ - pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR); - pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC); - pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC); - pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE); - pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36); - pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE); - pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT); - pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR); - pFeatures->fXSaveRstor = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE); - pFeatures->fMmx = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MMX); - pFeatures->fSse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SSE); - pFeatures->fSse2 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SSE2); - pFeatures->fSse3 = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_SSE3); - pFeatures->fSsse3 = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_SSSE3); - pFeatures->fSse41 = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_SSE4_1); - pFeatures->fSse42 = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_SSE4_2); - pFeatures->fAvx = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_AVX); - pFeatures->fTsc = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_TSC); - pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP); - pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP); - pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR); + pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR); + pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC); + pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC); + pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE); + pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36); + pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE); + pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT); + pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR); + pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE); + pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE); + pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX); + pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE); + pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2); + pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3); + pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3); + pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1); + pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2); + pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX); + pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC); + pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP); + pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP); + pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR); /* Structured extended features. */ Index: /trunk/src/VBox/VMM/include/CPUMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/CPUMInternal.h (revision 55113) +++ /trunk/src/VBox/VMM/include/CPUMInternal.h (revision 55114) @@ -191,4 +191,6 @@ /** Supports the XSAVE and XRSTOR instructions. */ uint32_t fXSaveRstor : 1; + /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */ + uint32_t fOpSysXSaveRstor : 1; /** Supports MMX. */ uint32_t fMmx : 1; @@ -243,5 +245,5 @@ /** Alignment padding / reserved for future use. */ - uint32_t fPadding : 2; + uint32_t fPadding : 1; uint64_t auPadding[2]; } CPUMFEATURES; @@ -526,4 +528,7 @@ /** Host CPU feature information. */ CPUMFEATURES HostFeatures; + /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed + * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */ + uint64_t fXStateHostMask; /** @name MSR statistics. Index: /trunk/src/VBox/VMM/include/CPUMInternal.mac =================================================================== --- /trunk/src/VBox/VMM/include/CPUMInternal.mac (revision 55113) +++ /trunk/src/VBox/VMM/include/CPUMInternal.mac (revision 55114) @@ -103,4 +103,5 @@ .GuestFeatures resb 32 .HostFeatures resb 32 + .fXStateHostMask resq 1 .cMsrWrites resq 1