Index: /trunk/include/VBox/vmm/cpum.h =================================================================== --- /trunk/include/VBox/vmm/cpum.h (revision 54999) +++ /trunk/include/VBox/vmm/cpum.h (revision 55000) @@ -1179,6 +1179,6 @@ VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu); VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu); -VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore); -VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc); +VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu); +VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc); VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu); VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl); Index: /trunk/include/VBox/vmm/patm.h =================================================================== --- /trunk/include/VBox/vmm/patm.h (revision 54999) +++ /trunk/include/VBox/vmm/patm.h (revision 55000) @@ -145,8 +145,8 @@ VMM_INT_DECL(int) PATMReadPatchCode(PVM pVM, RTGCPTR GCPtrPatchCode, void *pvDst, size_t cbToRead, size_t *pcbRead); -VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore); -VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rawRC); -VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTXCORE pCtxCore); -VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t efl); +VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTX pCtx); +VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTX pCtx, int rawRC); +VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTX pCtx); +VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTX pCtx, uint32_t efl); VMM_INT_DECL(RCPTRTYPE(PPATMGCSTATE)) PATMGetGCState(PVM pVM); VMM_INT_DECL(bool) PATMShouldUseRawMode(PVM pVM, RTRCPTR pAddrGC); @@ -157,5 +157,5 @@ VMM_INT_DECL(bool) PATMAreInterruptsEnabledByCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore); #ifdef PATM_EMULATE_SYSENTER -VMM_INT_DECL(int) PATMSysCall(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); +VMM_INT_DECL(int) PATMSysCall(PVM pVM, PCPUMCTX pCtx, PDISCPUSTATE pCpu); #endif Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 55000) @@ -2260,8 +2260,7 @@ * @returns VBox status. (recompiler failure) * @param pVCpu Pointer to the VMCPU. - * @param pCtxCore The context core (for trap usage). * @see @ref pg_raw */ -VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore) +VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu) { PVM pVM = pVCpu->CTX_SUFF(pVM); @@ -2269,26 +2268,25 @@ Assert(!pVCpu->cpum.s.fRawEntered); Assert(!pVCpu->cpum.s.fRemEntered); - if (!pCtxCore) - pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest); + PCPUMCTX pCtx = &pVCpu->cpum.s.Guest; /* * Are we in Ring-0? */ - if ( pCtxCore->ss.Sel - && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0 - && !pCtxCore->eflags.Bits.u1VM) + if ( pCtx->ss.Sel + && (pCtx->ss.Sel & X86_SEL_RPL) == 0 + && !pCtx->eflags.Bits.u1VM) { /* * Enter execution mode. */ - PATMRawEnter(pVM, pCtxCore); + PATMRawEnter(pVM, pCtx); /* * Set CPL to Ring-1. */ - pCtxCore->ss.Sel |= 1; - if ( pCtxCore->cs.Sel - && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0) - pCtxCore->cs.Sel |= 1; + pCtx->ss.Sel |= 1; + if ( pCtx->cs.Sel + && (pCtx->cs.Sel & X86_SEL_RPL) == 0) + pCtx->cs.Sel |= 1; } else @@ -2296,14 +2294,14 @@ # ifdef VBOX_WITH_RAW_RING1 if ( EMIsRawRing1Enabled(pVM) - && !pCtxCore->eflags.Bits.u1VM - && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1) + && !pCtx->eflags.Bits.u1VM + && (pCtx->ss.Sel & X86_SEL_RPL) == 1) { /* Set CPL to Ring-2. */ - pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2; - if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1) - pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2; + pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 2; + if (pCtx->cs.Sel && (pCtx->cs.Sel & X86_SEL_RPL) == 1) + pCtx->cs.Sel = (pCtx->cs.Sel & ~X86_SEL_RPL) | 2; } # else - AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM, + AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) >= 2 || pCtx->eflags.Bits.u1VM, ("ring-1 code not supported\n")); # endif @@ -2311,5 +2309,5 @@ * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well. */ - PATMRawEnter(pVM, pCtxCore); + PATMRawEnter(pVM, pCtx); } @@ -2317,10 +2315,10 @@ * Assert sanity. */ - AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n")); - AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0, - ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL)); + AssertMsg((pCtx->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n")); + AssertReleaseMsg(pCtx->eflags.Bits.u2IOPL == 0, + ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL)); Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP)); - pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */ + pCtx->eflags.u32 |= X86_EFL_IF; /* paranoia */ pVCpu->cpum.s.fRawEntered = true; @@ -2337,8 +2335,7 @@ * @param pVCpu Pointer to the VMCPU. * @param rc Raw mode return code - * @param pCtxCore The context core (for trap usage). * @see @ref pg_raw */ -VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc) +VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc) { PVM pVM = pVCpu->CTX_SUFF(pVM); @@ -2353,37 +2350,35 @@ PCPUMCTX pCtx = &pVCpu->cpum.s.Guest; - if (!pCtxCore) - pCtxCore = CPUMCTX2CORE(pCtx); - Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL)); - AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL), - ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL)); + Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL)); + AssertMsg(pCtx->eflags.Bits.u1VM || pCtx->eflags.Bits.u2IOPL < (unsigned)(pCtx->ss.Sel & X86_SEL_RPL), + ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL)); /* * Are we executing in raw ring-1? */ - if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1 - && !pCtxCore->eflags.Bits.u1VM) + if ( (pCtx->ss.Sel & X86_SEL_RPL) == 1 + && !pCtx->eflags.Bits.u1VM) { /* * Leave execution mode. */ - PATMRawLeave(pVM, pCtxCore, rc); + PATMRawLeave(pVM, pCtx, rc); /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */ /** @todo See what happens if we remove this. */ - if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1) - pCtxCore->ds.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1) - pCtxCore->es.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1) - pCtxCore->fs.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1) - pCtxCore->gs.Sel &= ~X86_SEL_RPL; + if ((pCtx->ds.Sel & X86_SEL_RPL) == 1) + pCtx->ds.Sel &= ~X86_SEL_RPL; + if ((pCtx->es.Sel & X86_SEL_RPL) == 1) + pCtx->es.Sel &= ~X86_SEL_RPL; + if ((pCtx->fs.Sel & X86_SEL_RPL) == 1) + pCtx->fs.Sel &= ~X86_SEL_RPL; + if ((pCtx->gs.Sel & X86_SEL_RPL) == 1) + pCtx->gs.Sel &= ~X86_SEL_RPL; /* * Ring-1 selector => Ring-0. */ - pCtxCore->ss.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1) - pCtxCore->cs.Sel &= ~X86_SEL_RPL; + pCtx->ss.Sel &= ~X86_SEL_RPL; + if ((pCtx->cs.Sel & X86_SEL_RPL) == 1) + pCtx->cs.Sel &= ~X86_SEL_RPL; } else @@ -2392,28 +2387,28 @@ * PATM is taking care of the IOPL and IF flags for us. */ - PATMRawLeave(pVM, pCtxCore, rc); - if (!pCtxCore->eflags.Bits.u1VM) + PATMRawLeave(pVM, pCtx, rc); + if (!pCtx->eflags.Bits.u1VM) { # ifdef VBOX_WITH_RAW_RING1 if ( EMIsRawRing1Enabled(pVM) - && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2) + && (pCtx->ss.Sel & X86_SEL_RPL) == 2) { /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */ /** @todo See what happens if we remove this. */ - if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2) - pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1; - if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2) - pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1; - if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2) - pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1; - if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2) - pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1; + if ((pCtx->ds.Sel & X86_SEL_RPL) == 2) + pCtx->ds.Sel = (pCtx->ds.Sel & ~X86_SEL_RPL) | 1; + if ((pCtx->es.Sel & X86_SEL_RPL) == 2) + pCtx->es.Sel = (pCtx->es.Sel & ~X86_SEL_RPL) | 1; + if ((pCtx->fs.Sel & X86_SEL_RPL) == 2) + pCtx->fs.Sel = (pCtx->fs.Sel & ~X86_SEL_RPL) | 1; + if ((pCtx->gs.Sel & X86_SEL_RPL) == 2) + pCtx->gs.Sel = (pCtx->gs.Sel & ~X86_SEL_RPL) | 1; /* * Ring-2 selector => Ring-1. */ - pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1; - if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2) - pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1; + pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 1; + if ((pCtx->cs.Sel & X86_SEL_RPL) == 2) + pCtx->cs.Sel = (pCtx->cs.Sel & ~X86_SEL_RPL) | 1; } else @@ -2421,12 +2416,12 @@ # endif /** @todo See what happens if we remove this. */ - if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1) - pCtxCore->ds.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1) - pCtxCore->es.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1) - pCtxCore->fs.Sel &= ~X86_SEL_RPL; - if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1) - pCtxCore->gs.Sel &= ~X86_SEL_RPL; + if ((pCtx->ds.Sel & X86_SEL_RPL) == 1) + pCtx->ds.Sel &= ~X86_SEL_RPL; + if ((pCtx->es.Sel & X86_SEL_RPL) == 1) + pCtx->es.Sel &= ~X86_SEL_RPL; + if ((pCtx->fs.Sel & X86_SEL_RPL) == 1) + pCtx->fs.Sel &= ~X86_SEL_RPL; + if ((pCtx->gs.Sel & X86_SEL_RPL) == 1) + pCtx->gs.Sel &= ~X86_SEL_RPL; # ifdef VBOX_WITH_RAW_RING1 } @@ -2450,5 +2445,5 @@ #ifdef VBOX_WITH_RAW_MODE_NOT_R0 if (pVCpu->cpum.s.fRawEntered) - PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl); + PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.s.Guest, fEfl); else #endif @@ -2467,5 +2462,5 @@ #ifdef VBOX_WITH_RAW_MODE_NOT_R0 if (pVCpu->cpum.s.fRawEntered) - return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest)); + return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.s.Guest); #endif return pVCpu->cpum.s.Guest.eflags.u32; Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 55000) @@ -844,5 +844,5 @@ && PATMIsPatchGCAddr(IEMCPU_TO_VM(pIemCpu), pCtx->eip); if (!pIemCpu->fInPatchCode) - CPUMRawLeave(pVCpu, CPUMCTX2CORE(pCtx), VINF_SUCCESS); + CPUMRawLeave(pVCpu, VINF_SUCCESS); #endif } @@ -914,5 +914,5 @@ && PATMIsPatchGCAddr(IEMCPU_TO_VM(pIemCpu), pCtx->eip); if (!pIemCpu->fInPatchCode) - CPUMRawLeave(pVCpu, CPUMCTX2CORE(pCtx), VINF_SUCCESS); + CPUMRawLeave(pVCpu, VINF_SUCCESS); #endif @@ -10679,5 +10679,5 @@ { if (!pIemCpu->fInPatchCode) - CPUMRawEnter(pVCpu, CPUMCTX2CORE(pCtx)); + CPUMRawEnter(pVCpu); return rcStrict; } Index: /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp (revision 55000) @@ -46,8 +46,8 @@ * * @param pVM Pointer to the VM. - * @param pCtxCore The cpu context core. + * @param pCtx The cpu context. * @see pg_raw */ -VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore) +VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTX pCtx) { Assert(!HMIsEnabled(pVM)); @@ -57,18 +57,18 @@ * For all cases where it isn't, IOPL will be safe and IF will be set. */ - uint32_t efl = pCtxCore->eflags.u32; + uint32_t efl = pCtx->eflags.u32; CTXSUFF(pVM->patm.s.pGCState)->uVMFlags = efl & PATM_VIRTUAL_FLAGS_MASK; - AssertMsg((efl & X86_EFL_IF) || PATMShouldUseRawMode(pVM, (RTRCPTR)pCtxCore->eip), + AssertMsg((efl & X86_EFL_IF) || PATMShouldUseRawMode(pVM, (RTRCPTR)pCtx->eip), ("X86_EFL_IF is clear and PATM is disabled! (eip=%RRv eflags=%08x fPATM=%d pPATMGC=%RRv-%RRv\n", - pCtxCore->eip, pCtxCore->eflags.u32, PATMIsEnabled(pVM), pVM->patm.s.pPatchMemGC, + pCtx->eip, pCtx->eflags.u32, PATMIsEnabled(pVM), pVM->patm.s.pPatchMemGC, pVM->patm.s.pPatchMemGC + pVM->patm.s.cbPatchMem)); - AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF || PATMIsPatchGCAddr(pVM, pCtxCore->eip), - ("fPIF=%d eip=%RRv\n", pVM->patm.s.CTXSUFF(pGCState)->fPIF, pCtxCore->eip)); + AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF || PATMIsPatchGCAddr(pVM, pCtx->eip), + ("fPIF=%d eip=%RRv\n", pVM->patm.s.CTXSUFF(pGCState)->fPIF, pCtx->eip)); efl &= ~PATM_VIRTUAL_FLAGS_MASK; efl |= X86_EFL_IF; - pCtxCore->eflags.u32 = efl; + pCtx->eflags.u32 = efl; #ifdef IN_RING3 @@ -121,23 +121,23 @@ * * @param pVM Pointer to the VM. - * @param pCtxCore The cpu context core. + * @param pCtx The cpu context. * @param rawRC Raw mode return code * @see @ref pg_raw */ -VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rawRC) +VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTX pCtx, int rawRC) { Assert(!HMIsEnabled(pVM)); - bool fPatchCode = PATMIsPatchGCAddr(pVM, pCtxCore->eip); + bool fPatchCode = PATMIsPatchGCAddr(pVM, pCtx->eip); /* * We will only be called if PATMRawEnter was previously called. */ - uint32_t efl = pCtxCore->eflags.u32; + uint32_t efl = pCtx->eflags.u32; efl = (efl & ~PATM_VIRTUAL_FLAGS_MASK) | (CTXSUFF(pVM->patm.s.pGCState)->uVMFlags & PATM_VIRTUAL_FLAGS_MASK); - pCtxCore->eflags.u32 = efl; + pCtx->eflags.u32 = efl; CTXSUFF(pVM->patm.s.pGCState)->uVMFlags = X86_EFL_IF; - AssertReleaseMsg((efl & X86_EFL_IF) || fPatchCode || rawRC == VINF_PATM_PENDING_IRQ_AFTER_IRET || RT_FAILURE(rawRC), ("Inconsistent state at %RRv rc=%Rrc\n", pCtxCore->eip, rawRC)); - AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF || fPatchCode || RT_FAILURE(rawRC), ("fPIF=%d eip=%RRv rc=%Rrc\n", CTXSUFF(pVM->patm.s.pGCState)->fPIF, pCtxCore->eip, rawRC)); + AssertReleaseMsg((efl & X86_EFL_IF) || fPatchCode || rawRC == VINF_PATM_PENDING_IRQ_AFTER_IRET || RT_FAILURE(rawRC), ("Inconsistent state at %RRv rc=%Rrc\n", pCtx->eip, rawRC)); + AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF || fPatchCode || RT_FAILURE(rawRC), ("fPIF=%d eip=%RRv rc=%Rrc\n", CTXSUFF(pVM->patm.s.pGCState)->fPIF, pCtx->eip, rawRC)); #ifdef IN_RING3 @@ -159,5 +159,5 @@ { PATMTRANSSTATE enmState; - RTRCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtxCore->eip, &enmState); + RTRCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState); AssertRelease(pOrgInstrGC); @@ -167,7 +167,7 @@ { Assert(!patmFindActivePatchByEntrypoint(pVM, pOrgInstrGC)); - Log(("Switchback from %RRv to %RRv (Psp=%x)\n", pCtxCore->eip, pOrgInstrGC, CTXSUFF(pVM->patm.s.pGCState)->Psp)); + Log(("Switchback from %RRv to %RRv (Psp=%x)\n", pCtx->eip, pOrgInstrGC, CTXSUFF(pVM->patm.s.pGCState)->Psp)); STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBack); - pCtxCore->eip = pOrgInstrGC; + pCtx->eip = pOrgInstrGC; fPatchCode = false; /* to reset the stack ptr */ @@ -176,5 +176,5 @@ else { - LogFlow(("Patch address %RRv can't be interrupted (state=%d)!\n", pCtxCore->eip, enmState)); + LogFlow(("Patch address %RRv can't be interrupted (state=%d)!\n", pCtx->eip, enmState)); STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBackFail); } @@ -182,5 +182,5 @@ else { - LogFlow(("Patch address %RRv can't be interrupted (fPIF=%d)!\n", pCtxCore->eip, CTXSUFF(pVM->patm.s.pGCState)->fPIF)); + LogFlow(("Patch address %RRv can't be interrupted (fPIF=%d)!\n", pCtx->eip, CTXSUFF(pVM->patm.s.pGCState)->fPIF)); STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBackFail); } @@ -192,12 +192,12 @@ * a single original guest instruction. */ - AssertMsg(!fPatchCode, ("eip=%RRv\n", pCtxCore->eip)); + AssertMsg(!fPatchCode, ("eip=%RRv\n", pCtx->eip)); #endif /* !IN_RING3 */ if (!fPatchCode) { - if (CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts == (RTRCPTR)pCtxCore->eip) + if (CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts == (RTRCPTR)pCtx->eip) { - EMSetInhibitInterruptsPC(VMMGetCpu0(pVM), pCtxCore->eip); + EMSetInhibitInterruptsPC(VMMGetCpu0(pVM), pCtx->eip); } CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts = 0; @@ -220,10 +220,10 @@ * @returns The eflags. * @param pVM Pointer to the VM. - * @param pCtxCore The context core. - */ -VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTXCORE pCtxCore) + * @param pCtx The guest cpu context. + */ +VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTX pCtx) { Assert(!HMIsEnabled(pVM)); - uint32_t efl = pCtxCore->eflags.u32; + uint32_t efl = pCtx->eflags.u32; efl &= ~PATM_VIRTUAL_FLAGS_MASK; efl |= pVM->patm.s.CTXSUFF(pGCState)->uVMFlags & PATM_VIRTUAL_FLAGS_MASK; @@ -236,8 +236,8 @@ * * @param pVM Pointer to the VM. - * @param pCtxCore The context core. + * @param pCtx The guest cpu context. * @param efl The new EFLAGS value. */ -VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t efl) +VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTX pCtx, uint32_t efl) { Assert(!HMIsEnabled(pVM)); @@ -245,5 +245,5 @@ efl &= ~PATM_VIRTUAL_FLAGS_MASK; efl |= X86_EFL_IF; - pCtxCore->eflags.u32 = efl; + pCtx->eflags.u32 = efl; } @@ -478,10 +478,10 @@ * * @param pVM Pointer to the VM. - * @param pCtxCore The relevant core context. - * @param pCpu Disassembly context - */ -VMMDECL(int) PATMSysCall(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) -{ - PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM)); + * @param pCtx The relevant guest cpu context. + * @param pCpu Disassembly state. + */ +VMMDECL(int) PATMSysCall(PVM pVM, PCPUMCTX pCtx, PDISCPUSTATE pCpu) +{ + Assert(CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM)) == pCtx); AssertReturn(!HMIsEnabled(pVM), VERR_PATM_HM_IPE); @@ -489,20 +489,20 @@ { if ( pCtx->SysEnter.cs == 0 - || pRegFrame->eflags.Bits.u1VM - || (pRegFrame->cs.Sel & X86_SEL_RPL) != 3 + || pCtx->eflags.Bits.u1VM + || (pCtx->cs.Sel & X86_SEL_RPL) != 3 || pVM->patm.s.pfnSysEnterPatchGC == 0 || pVM->patm.s.pfnSysEnterGC != (RTRCPTR)(RTRCUINTPTR)pCtx->SysEnter.eip - || !(PATMRawGetEFlags(pVM, pRegFrame) & X86_EFL_IF)) + || !(PATMRawGetEFlags(pVM, pCtx) & X86_EFL_IF)) goto end; - Log2(("PATMSysCall: sysenter from %RRv to %RRv\n", pRegFrame->eip, pVM->patm.s.pfnSysEnterPatchGC)); + Log2(("PATMSysCall: sysenter from %RRv to %RRv\n", pCtx->eip, pVM->patm.s.pfnSysEnterPatchGC)); /** @todo the base and limit are forced to 0 & 4G-1 resp. We assume the selector is wide open here. */ /** @note The Intel manual suggests that the OS is responsible for this. */ - pRegFrame->cs.Sel = (pCtx->SysEnter.cs & ~X86_SEL_RPL) | 1; - pRegFrame->eip = /** @todo ugly conversion! */(uint32_t)pVM->patm.s.pfnSysEnterPatchGC; - pRegFrame->ss.Sel = pRegFrame->cs.Sel + 8; /* SysEnter.cs + 8 */ - pRegFrame->esp = pCtx->SysEnter.esp; - pRegFrame->eflags.u32 &= ~(X86_EFL_VM | X86_EFL_RF); - pRegFrame->eflags.u32 |= X86_EFL_IF; + pCtx->cs.Sel = (pCtx->SysEnter.cs & ~X86_SEL_RPL) | 1; + pCtx->eip = /** @todo ugly conversion! */(uint32_t)pVM->patm.s.pfnSysEnterPatchGC; + pCtx->ss.Sel = pCtx->cs.Sel + 8; /* SysEnter.cs + 8 */ + pCtx->esp = pCtx->SysEnter.esp; + pCtx->eflags.u32 &= ~(X86_EFL_VM | X86_EFL_RF); + pCtx->eflags.u32 |= X86_EFL_IF; /* Turn off interrupts. */ @@ -516,15 +516,15 @@ { if ( pCtx->SysEnter.cs == 0 - || (pRegFrame->cs.Sel & X86_SEL_RPL) != 1 - || pRegFrame->eflags.Bits.u1VM - || !(PATMRawGetEFlags(pVM, pRegFrame) & X86_EFL_IF)) + || (pCtx->cs.Sel & X86_SEL_RPL) != 1 + || pCtx->eflags.Bits.u1VM + || !(PATMRawGetEFlags(pVM, pCtx) & X86_EFL_IF)) goto end; - Log2(("PATMSysCall: sysexit from %RRv to %RRv\n", pRegFrame->eip, pRegFrame->edx)); - - pRegFrame->cs.Sel = ((pCtx->SysEnter.cs + 16) & ~X86_SEL_RPL) | 3; - pRegFrame->eip = pRegFrame->edx; - pRegFrame->ss.Sel = pRegFrame->cs.Sel + 8; /* SysEnter.cs + 24 */ - pRegFrame->esp = pRegFrame->ecx; + Log2(("PATMSysCall: sysexit from %RRv to %RRv\n", pCtx->eip, pCtx->edx)); + + pCtx->cs.Sel = ((pCtx->SysEnter.cs + 16) & ~X86_SEL_RPL) | 3; + pCtx->eip = pCtx->edx; + pCtx->ss.Sel = pCtx->cs.Sel + 8; /* SysEnter.cs + 24 */ + pCtx->esp = pCtx->ecx; STAM_COUNTER_INC(&pVM->patm.s.StatSysExit); Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 55000) @@ -129,9 +129,9 @@ * Resume execution. */ - CPUMRawEnter(pVCpu, NULL); + CPUMRawEnter(pVCpu); CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF); rc = VMMR3ResumeHyper(pVM, pVCpu); Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc)); - rc = CPUMRawLeave(pVCpu, NULL, rc); + rc = CPUMRawLeave(pVCpu, rc); VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); @@ -191,5 +191,5 @@ * We do not start time or anything, if anything we should just do a few nanoseconds. */ - CPUMRawEnter(pVCpu, NULL); + CPUMRawEnter(pVCpu); do { @@ -204,5 +204,5 @@ } while ( rc == VINF_SUCCESS || rc == VINF_EM_RAW_INTERRUPT); - rc = CPUMRawLeave(pVCpu, NULL, rc); + rc = CPUMRawLeave(pVCpu, rc); VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); @@ -1429,5 +1429,5 @@ * and perhaps EIP) needs to be stored with PATM. */ - rc = CPUMRawEnter(pVCpu, NULL); + rc = CPUMRawEnter(pVCpu); if (rc != VINF_SUCCESS) { @@ -1453,5 +1453,5 @@ if (rc != VINF_SUCCESS) { - rc = CPUMRawLeave(pVCpu, NULL, rc); + rc = CPUMRawLeave(pVCpu, rc); break; } @@ -1513,5 +1513,5 @@ * execution FFs before doing anything else. */ - rc = CPUMRawLeave(pVCpu, NULL, rc); + rc = CPUMRawLeave(pVCpu, rc); VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) Index: /trunk/src/VBox/VMM/VMMR3/TRPM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/TRPM.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMR3/TRPM.cpp (revision 55000) @@ -824,4 +824,14 @@ else if (!strcmp(pszSymbol, "g_TRPMCPU")) *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm); + else if (!strcmp(pszSymbol, "g_trpmGuestCtx")) + { + PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0)); + *pRCPtrValue = VM_RC_ADDR(pVM, pCtx); + } + else if (!strcmp(pszSymbol, "g_trpmHyperCtx")) + { + PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0)); + *pRCPtrValue = VM_RC_ADDR(pVM, pCtx); + } else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore")) { Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 54999) +++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 55000) @@ -824,5 +824,5 @@ case OP_SYSEXIT: case OP_SYSRET: - rc = PATMSysCall(pVM, pRegFrame, pCpu); + rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu); TRPM_EXIT_DBG_HOOK(0xd); return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame); @@ -928,5 +928,5 @@ case OP_SYSENTER: #ifdef PATM_EMULATE_SYSENTER - rc = PATMSysCall(pVM, pRegFrame, pCpu); + rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu); if (rc == VINF_SUCCESS) {