Changeset 54812 in vbox
- Timestamp:
- Mar 17, 2015 3:32:35 PM (10 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r54799 r54812 4355 4355 4356 4356 4357 static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, 4358 PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle) 4359 { 4360 if ( pCurLeaf - paLeaves < cLeaves 4361 && pCurLeaf->uLeaf <= uUpToLeaf) 4362 { 4363 pHlp->pfnPrintf(pHlp, 4364 " %s\n" 4365 " Leaf/sub-leaf eax ebx ecx edx\n", pszTitle); 4366 while ( pCurLeaf - paLeaves < cLeaves 4367 && pCurLeaf->uLeaf <= uUpToLeaf) 4368 { 4369 CPUMCPUID Host; 4370 ASMCpuIdExSlow(pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4371 pHlp->pfnPrintf(pHlp, 4372 "Gst: %08x/%04x %08x %08x %08x %08x\n" 4373 "Hst: %08x %08x %08x %08x\n", 4374 pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx, 4375 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4376 pCurLeaf++; 4377 } 4378 } 4379 4380 return pCurLeaf; 4381 } 4382 4383 4357 4384 /** 4358 4385 * Display the guest CpuId leaves. … … 4377 4404 } 4378 4405 4406 uint32_t uLeaf; 4407 CPUMCPUID Host; 4408 uint32_t dummy; 4409 uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves; 4410 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3; 4411 PCCPUMCPUIDLEAF pCurLeaf; 4412 PCCPUMCPUIDLEAF pNextLeaf; 4413 4379 4414 /* 4380 * Start cracking. 4381 */ 4382 CPUMCPUID Host; 4383 CPUMCPUID Guest; 4384 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax; 4385 4386 uint32_t cStdHstMax; 4387 uint32_t dummy; 4388 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy); 4389 4390 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd), cStdHstMax); 4391 4415 * Standard leaves. Custom raw dump here due to ECX sub-leaves host handling. 4416 */ 4417 uint32_t cHstMax = ASMCpuId_EAX(0); 4418 uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0; 4419 uint32_t cMax = RT_MAX(cGstMax, cHstMax); 4392 4420 pHlp->pfnPrintf(pHlp, 4393 " RAW Standard CPUIDs\n" 4394 " Function eax ebx ecx edx\n"); 4395 for (unsigned i = 0; i <= cStdLstMax ; i++) 4396 { 4397 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd)) 4398 { 4399 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[i]; 4400 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4401 4402 pHlp->pfnPrintf(pHlp, 4403 "Gst: %08x %08x %08x %08x %08x%s\n" 4404 "Hst: %08x %08x %08x %08x\n", 4405 i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx, 4406 i <= cStdMax ? "" : "*", 4407 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4408 } 4409 else 4410 { 4411 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4412 4413 pHlp->pfnPrintf(pHlp, 4414 "Hst: %08x %08x %08x %08x %08x\n", 4415 i, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4421 " Raw Standard CPUID Leaves\n" 4422 " Leaf/sub-leaf eax ebx ecx edx\n"); 4423 for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++) 4424 { 4425 uint32_t cMaxSubLeaves = 1; 4426 if (uLeaf == 4 || uLeaf == 7 || uLeaf == 0xb) 4427 cMaxSubLeaves = 16; 4428 else if (uLeaf == 0xd) 4429 cMaxSubLeaves = 128; 4430 4431 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++) 4432 { 4433 ASMCpuIdExSlow(uLeaf, uSubLeaf, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4434 if ( pCurLeaf - paLeaves < cLeaves 4435 && pCurLeaf->uLeaf == uLeaf 4436 && pCurLeaf->uSubLeaf == uSubLeaf) 4437 { 4438 pHlp->pfnPrintf(pHlp, 4439 "Gst: %08x/%04x %08x %08x %08x %08x\n" 4440 "Hst: %08x %08x %08x %08x\n", 4441 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx, 4442 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4443 pCurLeaf++; 4444 } 4445 else if ( uLeaf != 0xd 4446 || uSubLeaf <= 1 4447 || Host.uEbx != 0 ) 4448 pHlp->pfnPrintf(pHlp, 4449 "Hst: %08x/%04x %08x %08x %08x %08x\n", 4450 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4451 4452 /* Done? */ 4453 if ( ( pCurLeaf - paLeaves >= cLeaves 4454 || pCurLeaf->uLeaf != uLeaf) 4455 && ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) 4456 || (uLeaf == 0x7 && Host.uEax == 0) 4457 || (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 || (Host.uEcx & 0xff00) >= 8)) 4458 || (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf) 4459 || (uLeaf == 0xd && uSubLeaf >= 128) 4460 ) 4461 ) 4462 break; 4416 4463 } 4417 4464 } … … 4420 4467 * If verbose, decode it. 4421 4468 */ 4422 if (iVerbosity) 4423 { 4424 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[0]; 4469 if (iVerbosity && paLeaves[0].uLeaf == 0) 4425 4470 pHlp->pfnPrintf(pHlp, 4426 4471 "Name: %.04s%.04s%.04s\n" 4427 4472 "Supports: 0-%x\n", 4428 &Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax); 4429 } 4473 &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx, paLeaves[0].uEax); 4430 4474 4431 4475 /* … … 4435 4479 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx, 4436 4480 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx); 4437 if (c StdMax >= 1 && iVerbosity)4481 if (cGstMax >= 1 && iVerbosity) 4438 4482 { 4439 4483 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" }; 4440 4484 4441 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1]; 4442 uint32_t uEAX = Guest.uEax; 4485 PCPUMCPUIDLEAF pFeatures = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, 1, 0); 4486 uint32_t uEAX = pFeatures ? pFeatures->uEax : 0; 4487 uint32_t uEBX = pFeatures ? pFeatures->uEbx : 0; 4443 4488 4444 4489 pHlp->pfnPrintf(pHlp, … … 4455 4500 ASMGetCpuStepping(uEAX), 4456 4501 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3], 4457 ( Guest.uEbx>> 24) & 0xff,4458 ( Guest.uEbx>> 16) & 0xff,4459 ( Guest.uEbx>> 8) & 0xff,4460 ( Guest.uEbx>> 0) & 0xff);4502 (uEBX >> 24) & 0xff, 4503 (uEBX >> 16) & 0xff, 4504 (uEBX >> 8) & 0xff, 4505 (uEBX >> 0) & 0xff); 4461 4506 if (iVerbosity == 1) 4462 4507 { 4463 uint32_t uEDX = Guest.uEdx;4508 uint32_t uEDX = pFeatures ? pFeatures->uEdx : 0; 4464 4509 pHlp->pfnPrintf(pHlp, "Features EDX: "); 4465 4510 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU"); … … 4497 4542 pHlp->pfnPrintf(pHlp, "\n"); 4498 4543 4499 uint32_t uECX = Guest.uEcx;4544 uint32_t uECX = pFeatures ? pFeatures->uEcx : 0; 4500 4545 pHlp->pfnPrintf(pHlp, "Features ECX: "); 4501 4546 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3"); … … 4539 4584 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.uEdx; 4540 4585 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.uEcx; 4541 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.uEdx; 4542 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.uEcx; 4586 X86CPUIDFEATEDX EdxGuest; 4587 X86CPUIDFEATECX EcxGuest; 4588 if (pFeatures) 4589 { 4590 EdxGuest = *(PX86CPUIDFEATEDX)&pFeatures->uEdx; 4591 EcxGuest = *(PX86CPUIDFEATECX)&pFeatures->uEcx; 4592 } 4593 else 4594 { 4595 RT_ZERO(EdxGuest); 4596 RT_ZERO(EcxGuest); 4597 } 4543 4598 4544 4599 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); … … 4610 4665 } 4611 4666 } 4612 if (c StdMax >= 2 && iVerbosity)4667 if (cGstMax >= 2 && iVerbosity) 4613 4668 { 4614 4669 /** @todo */ 4615 4670 } 4616 4617 /*4618 * Extended.4619 * Implemented after AMD specs.4620 */4621 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax & 0xffff;4622 4623 pHlp->pfnPrintf(pHlp,4624 "\n"4625 " RAW Extended CPUIDs\n"4626 " Function eax ebx ecx edx\n");4627 bool fSupportsInvariantTsc = false;4628 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt); i++)4629 {4630 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[i];4631 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);4632 4633 if ( i == 74634 && (Host.uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR))4635 {4636 fSupportsInvariantTsc = true;4637 }4638 pHlp->pfnPrintf(pHlp,4639 "Gst: %08x %08x %08x %08x %08x%s\n"4640 "Hst: %08x %08x %08x %08x\n",4641 0x80000000 | i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,4642 i <= cExtMax ? "" : "*",4643 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);4644 }4645 4646 /*4647 * Understandable output4648 */4649 if (iVerbosity)4650 {4651 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[0];4652 pHlp->pfnPrintf(pHlp,4653 "Ext Name: %.4s%.4s%.4s\n"4654 "Ext Supports: 0x80000000-%#010x\n",4655 &Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax);4656 }4657 4658 if (iVerbosity && cExtMax >= 1)4659 {4660 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[1];4661 uint32_t uEAX = Guest.uEax;4662 pHlp->pfnPrintf(pHlp,4663 "Family: %d \tExtended: %d \tEffective: %d\n"4664 "Model: %d \tExtended: %d \tEffective: %d\n"4665 "Stepping: %d\n"4666 "Brand ID: %#05x\n",4667 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),4668 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),4669 ASMGetCpuStepping(uEAX),4670 Guest.uEbx & 0xfff);4671 4672 if (iVerbosity == 1)4673 {4674 uint32_t uEDX = Guest.uEdx;4675 pHlp->pfnPrintf(pHlp, "Features EDX: ");4676 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");4677 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");4678 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");4679 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");4680 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");4681 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");4682 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");4683 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");4684 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");4685 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");4686 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");4687 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");4688 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");4689 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");4690 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");4691 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");4692 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");4693 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");4694 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");4695 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");4696 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");4697 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");4698 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");4699 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");4700 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");4701 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");4702 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");4703 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");4704 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");4705 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");4706 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");4707 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");4708 pHlp->pfnPrintf(pHlp, "\n");4709 4710 uint32_t uECX = Guest.uEcx;4711 pHlp->pfnPrintf(pHlp, "Features ECX: ");4712 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");4713 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");4714 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");4715 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");4716 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");4717 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");4718 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");4719 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");4720 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");4721 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");4722 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");4723 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");4724 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");4725 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");4726 for (unsigned iBit = 5; iBit < 32; iBit++)4727 if (uECX & RT_BIT(iBit))4728 pHlp->pfnPrintf(pHlp, " %d", iBit);4729 pHlp->pfnPrintf(pHlp, "\n");4730 }4731 else4732 {4733 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);4734 4735 uint32_t uEdxGst = Guest.uEdx;4736 uint32_t uEdxHst = Host.uEdx;4737 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");4738 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));4739 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));4740 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));4741 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));4742 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));4743 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));4744 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));4745 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));4746 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));4747 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));4748 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));4749 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));4750 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));4751 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));4752 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));4753 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));4754 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));4755 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));4756 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));4757 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));4758 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));4759 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));4760 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));4761 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));4762 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));4763 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));4764 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));4765 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));4766 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));4767 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));4768 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));4769 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));4770 4771 uint32_t uEcxGst = Guest.uEcx;4772 uint32_t uEcxHst = Host.uEcx;4773 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));4774 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));4775 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));4776 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));4777 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));4778 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));4779 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));4780 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));4781 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));4782 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));4783 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));4784 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));4785 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));4786 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));4787 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);4788 }4789 }4790 4791 if (iVerbosity && cExtMax >= 2)4792 {4793 char szString[4*4*3+1] = {0};4794 uint32_t *pu32 = (uint32_t *)szString;4795 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEax;4796 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEbx;4797 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEcx;4798 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEdx;4799 if (cExtMax >= 3)4800 {4801 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEax;4802 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEbx;4803 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEcx;4804 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEdx;4805 }4806 if (cExtMax >= 4)4807 {4808 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEax;4809 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEbx;4810 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEcx;4811 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEdx;4812 }4813 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);4814 }4815 4816 if (iVerbosity && cExtMax >= 5)4817 {4818 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEax;4819 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEbx;4820 uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEcx;4821 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEdx;4822 char sz1[32];4823 char sz2[32];4824 4825 pHlp->pfnPrintf(pHlp,4826 "TLB 2/4M Instr/Uni: %s %3d entries\n"4827 "TLB 2/4M Data: %s %3d entries\n",4828 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,4829 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);4830 pHlp->pfnPrintf(pHlp,4831 "TLB 4K Instr/Uni: %s %3d entries\n"4832 "TLB 4K Data: %s %3d entries\n",4833 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,4834 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);4835 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"4836 "L1 Instr Cache Lines Per Tag: %d\n"4837 "L1 Instr Cache Associativity: %s\n"4838 "L1 Instr Cache Size: %d KB\n",4839 (uEDX >> 0) & 0xff,4840 (uEDX >> 8) & 0xff,4841 getCacheAss((uEDX >> 16) & 0xff, sz1),4842 (uEDX >> 24) & 0xff);4843 pHlp->pfnPrintf(pHlp,4844 "L1 Data Cache Line Size: %d bytes\n"4845 "L1 Data Cache Lines Per Tag: %d\n"4846 "L1 Data Cache Associativity: %s\n"4847 "L1 Data Cache Size: %d KB\n",4848 (uECX >> 0) & 0xff,4849 (uECX >> 8) & 0xff,4850 getCacheAss((uECX >> 16) & 0xff, sz1),4851 (uECX >> 24) & 0xff);4852 }4853 4854 if (iVerbosity && cExtMax >= 6)4855 {4856 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEax;4857 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEbx;4858 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEdx;4859 4860 pHlp->pfnPrintf(pHlp,4861 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"4862 "L2 TLB 2/4M Data: %s %4d entries\n",4863 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,4864 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);4865 pHlp->pfnPrintf(pHlp,4866 "L2 TLB 4K Instr/Uni: %s %4d entries\n"4867 "L2 TLB 4K Data: %s %4d entries\n",4868 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,4869 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);4870 pHlp->pfnPrintf(pHlp,4871 "L2 Cache Line Size: %d bytes\n"4872 "L2 Cache Lines Per Tag: %d\n"4873 "L2 Cache Associativity: %s\n"4874 "L2 Cache Size: %d KB\n",4875 (uEDX >> 0) & 0xff,4876 (uEDX >> 8) & 0xf,4877 getL2CacheAss((uEDX >> 12) & 0xf),4878 (uEDX >> 16) & 0xffff);4879 }4880 4881 if (iVerbosity && cExtMax >= 7)4882 {4883 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[7].uEdx;4884 4885 pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n", fSupportsInvariantTsc);4886 pHlp->pfnPrintf(pHlp, "APM Features: ");4887 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");4888 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");4889 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");4890 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");4891 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");4892 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");4893 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");4894 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");4895 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");4896 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");4897 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");4898 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");4899 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");4900 for (unsigned iBit = 13; iBit < 32; iBit++)4901 if (uEDX & RT_BIT(iBit))4902 pHlp->pfnPrintf(pHlp, " %d", iBit);4903 pHlp->pfnPrintf(pHlp, "\n");4904 }4905 4906 if (iVerbosity && cExtMax >= 8)4907 {4908 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEax;4909 uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEcx;4910 4911 pHlp->pfnPrintf(pHlp,4912 "Physical Address Width: %d bits\n"4913 "Virtual Address Width: %d bits\n"4914 "Guest Physical Address Width: %d bits\n",4915 (uEAX >> 0) & 0xff,4916 (uEAX >> 8) & 0xff,4917 (uEAX >> 16) & 0xff);4918 pHlp->pfnPrintf(pHlp,4919 "Physical Core Count: %d\n",4920 (uECX >> 0) & 0xff);4921 }4922 4923 4671 4924 4672 /* … … 4928 4676 * aren't a subset of the host CPUID bits. 4929 4677 */ 4930 RT_ZERO(Host); 4931 if (cStdHstMax >= 1) 4932 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4933 bool fHostHvp = RT_BOOL(Host.uEcx & X86_CPUID_FEATURE_ECX_HVP); 4934 bool fGuestHvp = false; 4935 if (cStdMax >= 1) 4936 { 4937 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1]; 4938 fGuestHvp = RT_BOOL(Guest.uEcx & X86_CPUID_FEATURE_ECX_HVP); 4939 } 4940 4941 if ( fHostHvp 4942 || fGuestHvp) 4943 { 4944 uint32_t const uHyperLeaf = 0x40000000; 4678 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves"); 4679 4680 ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4681 cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0; 4682 cGstMax = pCurLeaf - paLeaves < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000) 4683 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0; 4684 cMax = RT_MAX(cHstMax, cGstMax); 4685 if (cMax >= UINT32_C(0x40000000)) 4686 { 4687 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves"); 4688 4689 /** @todo dump these in more detail. */ 4690 4691 pCurLeaf = pNextLeaf; 4692 } 4693 4694 4695 /* 4696 * Extended. Custom raw dump here due to ECX sub-leaves host handling. 4697 * Implemented after AMD specs. 4698 */ 4699 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves"); 4700 4701 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4702 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0; 4703 cGstMax = pCurLeaf - paLeaves < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000) 4704 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0; 4705 cMax = RT_MAX(cHstMax, cGstMax); 4706 if (cMax >= UINT32_C(0x80000000)) 4707 { 4708 4945 4709 pHlp->pfnPrintf(pHlp, 4946 "\n" 4947 " Hypervisor CPUIDs\n" 4948 " Function eax ebx ecx edx\n"); 4949 4950 PCCPUMCPUIDLEAF pHyperLeafGst = NULL; 4951 if (fGuestHvp) 4952 { 4953 pHyperLeafGst = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves, 4954 uHyperLeaf, 0 /* uSubLeaf */); 4955 } 4956 4957 RT_ZERO(Host); 4958 if (fHostHvp) 4959 ASMCpuIdExSlow(uHyperLeaf, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4960 4961 CPUMCPUIDLEAF GuestLeaf; 4962 uint32_t const cHyperGstMax = pHyperLeafGst ? pHyperLeafGst->uEax : 0; 4963 uint32_t const cHyperHstMax = Host.uEax; 4964 uint32_t const cHyperMax = RT_MAX(cHyperHstMax, cHyperGstMax); 4965 for (uint32_t i = uHyperLeaf; i <= cHyperMax; i++) 4966 { 4967 RT_ZERO(Host); 4968 RT_ZERO(GuestLeaf); 4969 if (i <= cHyperHstMax) 4970 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4971 CPUMR3CpuIdGetLeaf(pVM, &GuestLeaf, i, 0 /* uSubLeaf */); 4972 if (!fHostHvp) 4710 " Raw Extended CPUID Leaves\n" 4711 " Leaf/sub-leaf eax ebx ecx edx\n"); 4712 PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf; 4713 for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++) 4714 { 4715 uint32_t cMaxSubLeaves = 1; 4716 if (uLeaf == UINT32_C(0x8000001d)) 4717 cMaxSubLeaves = 16; 4718 4719 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++) 4973 4720 { 4974 pHlp->pfnPrintf(pHlp, 4975 "Gst: %08x %08x %08x %08x %08x\n", 4976 i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx); 4721 ASMCpuIdExSlow(uLeaf, uSubLeaf, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4722 if ( pCurLeaf - paLeaves < cLeaves 4723 && pCurLeaf->uLeaf == uLeaf 4724 && pCurLeaf->uSubLeaf == uSubLeaf) 4725 { 4726 pHlp->pfnPrintf(pHlp, 4727 "Gst: %08x/%04x %08x %08x %08x %08x\n" 4728 "Hst: %08x %08x %08x %08x\n", 4729 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx, 4730 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4731 pCurLeaf++; 4732 } 4733 else if ( uLeaf != 0xd 4734 || uSubLeaf <= 1 4735 || Host.uEbx != 0 ) 4736 pHlp->pfnPrintf(pHlp, 4737 "Hst: %08x/%04x %08x %08x %08x %08x\n", 4738 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 4739 4740 /* Done? */ 4741 if ( ( pCurLeaf - paLeaves >= cLeaves 4742 || pCurLeaf->uLeaf != uLeaf) 4743 && (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) ) 4744 break; 4745 } 4746 } 4747 pNextLeaf = pCurLeaf; 4748 4749 /* 4750 * Understandable output 4751 */ 4752 if (iVerbosity) 4753 pHlp->pfnPrintf(pHlp, 4754 "Ext Name: %.4s%.4s%.4s\n" 4755 "Ext Supports: 0x80000000-%#010x\n", 4756 &pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax); 4757 4758 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0); 4759 if (iVerbosity && pCurLeaf) 4760 { 4761 uint32_t uEAX = pCurLeaf->uEax; 4762 pHlp->pfnPrintf(pHlp, 4763 "Family: %d \tExtended: %d \tEffective: %d\n" 4764 "Model: %d \tExtended: %d \tEffective: %d\n" 4765 "Stepping: %d\n" 4766 "Brand ID: %#05x\n", 4767 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX), 4768 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel), 4769 ASMGetCpuStepping(uEAX), 4770 pCurLeaf->uEbx & 0xfff); 4771 4772 if (iVerbosity == 1) 4773 { 4774 uint32_t uEDX = pCurLeaf->uEdx; 4775 pHlp->pfnPrintf(pHlp, "Features EDX: "); 4776 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU"); 4777 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME"); 4778 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE"); 4779 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE"); 4780 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC"); 4781 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR"); 4782 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE"); 4783 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE"); 4784 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8"); 4785 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC"); 4786 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10"); 4787 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR"); 4788 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR"); 4789 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE"); 4790 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA"); 4791 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV"); 4792 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT"); 4793 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36"); 4794 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18"); 4795 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19"); 4796 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX"); 4797 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21"); 4798 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX"); 4799 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX"); 4800 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR"); 4801 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR"); 4802 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB"); 4803 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP"); 4804 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28"); 4805 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode"); 4806 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow"); 4807 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow"); 4808 pHlp->pfnPrintf(pHlp, "\n"); 4809 4810 uint32_t uECX = pCurLeaf->uEcx; 4811 pHlp->pfnPrintf(pHlp, "Features ECX: "); 4812 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF"); 4813 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL"); 4814 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM"); 4815 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC"); 4816 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L"); 4817 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM"); 4818 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A"); 4819 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE"); 4820 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF"); 4821 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW"); 4822 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS"); 4823 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5"); 4824 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT"); 4825 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT"); 4826 for (unsigned iBit = 5; iBit < 32; iBit++) 4827 if (uECX & RT_BIT(iBit)) 4828 pHlp->pfnPrintf(pHlp, " %d", iBit); 4829 pHlp->pfnPrintf(pHlp, "\n"); 4977 4830 } 4978 4831 else 4979 4832 { 4980 pHlp->pfnPrintf(pHlp, 4981 "Gst: %08x %08x %08x %08x %08x%s\n" 4982 "Hst: %08x %08x %08x %08x%s\n", 4983 i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx, 4984 i <= cHyperGstMax ? "" : "*", 4985 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx, i <= cHyperHstMax ? "" : "*"); 4833 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4834 4835 uint32_t uEdxGst = pCurLeaf->uEdx; 4836 uint32_t uEdxHst = Host.uEdx; 4837 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); 4838 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0))); 4839 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1))); 4840 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2))); 4841 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3))); 4842 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4))); 4843 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5))); 4844 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6))); 4845 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7))); 4846 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8))); 4847 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9))); 4848 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10))); 4849 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11))); 4850 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12))); 4851 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13))); 4852 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14))); 4853 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15))); 4854 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16))); 4855 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17))); 4856 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18))); 4857 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19))); 4858 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20))); 4859 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21))); 4860 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22))); 4861 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23))); 4862 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24))); 4863 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25))); 4864 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26))); 4865 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27))); 4866 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28))); 4867 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29))); 4868 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30))); 4869 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31))); 4870 4871 uint32_t uEcxGst = pCurLeaf->uEcx; 4872 uint32_t uEcxHst = Host.uEcx; 4873 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0))); 4874 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1))); 4875 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2))); 4876 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3))); 4877 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4))); 4878 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5))); 4879 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6))); 4880 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7))); 4881 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8))); 4882 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9))); 4883 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10))); 4884 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11))); 4885 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12))); 4886 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13))); 4887 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14); 4986 4888 } 4987 4889 } 4988 } 4890 4891 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL) 4892 { 4893 char szString[4*4*3+1] = {0}; 4894 uint32_t *pu32 = (uint32_t *)szString; 4895 *pu32++ = pCurLeaf->uEax; 4896 *pu32++ = pCurLeaf->uEbx; 4897 *pu32++ = pCurLeaf->uEcx; 4898 *pu32++ = pCurLeaf->uEdx; 4899 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0); 4900 if (pCurLeaf) 4901 { 4902 *pu32++ = pCurLeaf->uEax; 4903 *pu32++ = pCurLeaf->uEbx; 4904 *pu32++ = pCurLeaf->uEcx; 4905 *pu32++ = pCurLeaf->uEdx; 4906 } 4907 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0); 4908 if (pCurLeaf) 4909 { 4910 *pu32++ = pCurLeaf->uEax; 4911 *pu32++ = pCurLeaf->uEbx; 4912 *pu32++ = pCurLeaf->uEcx; 4913 *pu32++ = pCurLeaf->uEdx; 4914 } 4915 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString); 4916 } 4917 4918 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL) 4919 { 4920 uint32_t uEAX = pCurLeaf->uEax; 4921 uint32_t uEBX = pCurLeaf->uEbx; 4922 uint32_t uECX = pCurLeaf->uEcx; 4923 uint32_t uEDX = pCurLeaf->uEdx; 4924 char sz1[32]; 4925 char sz2[32]; 4926 4927 pHlp->pfnPrintf(pHlp, 4928 "TLB 2/4M Instr/Uni: %s %3d entries\n" 4929 "TLB 2/4M Data: %s %3d entries\n", 4930 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff, 4931 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff); 4932 pHlp->pfnPrintf(pHlp, 4933 "TLB 4K Instr/Uni: %s %3d entries\n" 4934 "TLB 4K Data: %s %3d entries\n", 4935 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff, 4936 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff); 4937 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n" 4938 "L1 Instr Cache Lines Per Tag: %d\n" 4939 "L1 Instr Cache Associativity: %s\n" 4940 "L1 Instr Cache Size: %d KB\n", 4941 (uEDX >> 0) & 0xff, 4942 (uEDX >> 8) & 0xff, 4943 getCacheAss((uEDX >> 16) & 0xff, sz1), 4944 (uEDX >> 24) & 0xff); 4945 pHlp->pfnPrintf(pHlp, 4946 "L1 Data Cache Line Size: %d bytes\n" 4947 "L1 Data Cache Lines Per Tag: %d\n" 4948 "L1 Data Cache Associativity: %s\n" 4949 "L1 Data Cache Size: %d KB\n", 4950 (uECX >> 0) & 0xff, 4951 (uECX >> 8) & 0xff, 4952 getCacheAss((uECX >> 16) & 0xff, sz1), 4953 (uECX >> 24) & 0xff); 4954 } 4955 4956 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL) 4957 { 4958 uint32_t uEAX = pCurLeaf->uEax; 4959 uint32_t uEBX = pCurLeaf->uEbx; 4960 uint32_t uEDX = pCurLeaf->uEdx; 4961 4962 pHlp->pfnPrintf(pHlp, 4963 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n" 4964 "L2 TLB 2/4M Data: %s %4d entries\n", 4965 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff, 4966 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff); 4967 pHlp->pfnPrintf(pHlp, 4968 "L2 TLB 4K Instr/Uni: %s %4d entries\n" 4969 "L2 TLB 4K Data: %s %4d entries\n", 4970 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff, 4971 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff); 4972 pHlp->pfnPrintf(pHlp, 4973 "L2 Cache Line Size: %d bytes\n" 4974 "L2 Cache Lines Per Tag: %d\n" 4975 "L2 Cache Associativity: %s\n" 4976 "L2 Cache Size: %d KB\n", 4977 (uEDX >> 0) & 0xff, 4978 (uEDX >> 8) & 0xf, 4979 getL2CacheAss((uEDX >> 12) & 0xf), 4980 (uEDX >> 16) & 0xffff); 4981 } 4982 4983 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL) 4984 { 4985 uint32_t uEDX = pCurLeaf->uEdx; 4986 4987 pHlp->pfnPrintf(pHlp, "APM Features: "); 4988 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS"); 4989 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID"); 4990 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID"); 4991 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP"); 4992 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM"); 4993 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC"); 4994 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC"); 4995 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE"); 4996 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant"); 4997 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB"); 4998 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO"); 4999 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI"); 5000 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA"); 5001 for (unsigned iBit = 13; iBit < 32; iBit++) 5002 if (uEDX & RT_BIT(iBit)) 5003 pHlp->pfnPrintf(pHlp, " %d", iBit); 5004 pHlp->pfnPrintf(pHlp, "\n"); 5005 5006 ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 5007 pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n", 5008 cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8))); 5009 5010 } 5011 5012 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL) 5013 { 5014 uint32_t uEAX = pCurLeaf->uEax; 5015 uint32_t uECX = pCurLeaf->uEcx; 5016 5017 pHlp->pfnPrintf(pHlp, 5018 "Physical Address Width: %d bits\n" 5019 "Virtual Address Width: %d bits\n" 5020 "Guest Physical Address Width: %d bits\n", 5021 (uEAX >> 0) & 0xff, 5022 (uEAX >> 8) & 0xff, 5023 (uEAX >> 16) & 0xff); 5024 pHlp->pfnPrintf(pHlp, 5025 "Physical Core Count: %d\n", 5026 (uECX >> 0) & 0xff); 5027 } 5028 5029 pCurLeaf = pNextLeaf; 5030 } 5031 5032 4989 5033 4990 5034 /* 4991 5035 * Centaur. 4992 5036 */ 4993 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdPatmCentaur[0].uEax & 0xffff; 4994 4995 pHlp->pfnPrintf(pHlp, 4996 "\n" 4997 " RAW Centaur CPUIDs\n" 4998 " Function eax ebx ecx edx\n"); 4999 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur); i++) 5000 { 5001 Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[i]; 5002 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 5003 5004 pHlp->pfnPrintf(pHlp, 5005 "Gst: %08x %08x %08x %08x %08x%s\n" 5006 "Hst: %08x %08x %08x %08x\n", 5007 0xc0000000 | i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx, 5008 i <= cCentaurMax ? "" : "*", 5009 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx); 5037 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves"); 5038 5039 ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 5040 cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff) 5041 ? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0; 5042 cGstMax = pCurLeaf - paLeaves < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000) 5043 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0; 5044 cMax = RT_MAX(cHstMax, cGstMax); 5045 if (cMax >= UINT32_C(0xc0000000)) 5046 { 5047 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves"); 5048 5049 /* 5050 * Understandable output 5051 */ 5052 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL) 5053 pHlp->pfnPrintf(pHlp, 5054 "Centaur Supports: 0xc0000000-%#010x\n", 5055 pCurLeaf->uEax); 5056 5057 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL) 5058 { 5059 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 5060 uint32_t uEdxGst = pCurLeaf->uEdx; 5061 uint32_t uEdxHst = Host.uEdx; 5062 5063 if (iVerbosity == 1) 5064 { 5065 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: "); 5066 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS"); 5067 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E"); 5068 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG"); 5069 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E"); 5070 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH"); 5071 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS"); 5072 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE"); 5073 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E"); 5074 /* possibly indicating MM/HE and MM/HE-E on older chips... */ 5075 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2"); 5076 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E"); 5077 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE"); 5078 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E"); 5079 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM"); 5080 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E"); 5081 for (unsigned iBit = 14; iBit < 32; iBit++) 5082 if (uEdxGst & RT_BIT(iBit)) 5083 pHlp->pfnPrintf(pHlp, " %d", iBit); 5084 pHlp->pfnPrintf(pHlp, "\n"); 5085 } 5086 else 5087 { 5088 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); 5089 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0))); 5090 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1))); 5091 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2))); 5092 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3))); 5093 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4))); 5094 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5))); 5095 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6))); 5096 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7))); 5097 /* possibly indicating MM/HE and MM/HE-E on older chips... */ 5098 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8))); 5099 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9))); 5100 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10))); 5101 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11))); 5102 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12))); 5103 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13))); 5104 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14))); 5105 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15))); 5106 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16))); 5107 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17))); 5108 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18))); 5109 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19))); 5110 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20))); 5111 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21))); 5112 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22))); 5113 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23))); 5114 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24))); 5115 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25))); 5116 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26))); 5117 for (unsigned iBit = 27; iBit < 32; iBit++) 5118 if ((uEdxGst | uEdxHst) & RT_BIT(iBit)) 5119 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit))); 5120 pHlp->pfnPrintf(pHlp, "\n"); 5121 } 5122 } 5123 5124 pCurLeaf = pNextLeaf; 5010 5125 } 5011 5126 5012 5127 /* 5013 * Understandable output 5014 */ 5015 if (iVerbosity) 5016 { 5017 Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[0]; 5018 pHlp->pfnPrintf(pHlp, 5019 "Centaur Supports: 0xc0000000-%#010x\n", 5020 Guest.uEax); 5021 } 5022 5023 if (iVerbosity && cCentaurMax >= 1) 5024 { 5025 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 5026 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdPatmCentaur[1].uEdx; 5027 uint32_t uEdxHst = Host.uEdx; 5028 5029 if (iVerbosity == 1) 5030 { 5031 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: "); 5032 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS"); 5033 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E"); 5034 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG"); 5035 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E"); 5036 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH"); 5037 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS"); 5038 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE"); 5039 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E"); 5040 /* possibly indicating MM/HE and MM/HE-E on older chips... */ 5041 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2"); 5042 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E"); 5043 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE"); 5044 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E"); 5045 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM"); 5046 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E"); 5047 for (unsigned iBit = 14; iBit < 32; iBit++) 5048 if (uEdxGst & RT_BIT(iBit)) 5049 pHlp->pfnPrintf(pHlp, " %d", iBit); 5050 pHlp->pfnPrintf(pHlp, "\n"); 5051 } 5052 else 5053 { 5054 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); 5055 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0))); 5056 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1))); 5057 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2))); 5058 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3))); 5059 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4))); 5060 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5))); 5061 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6))); 5062 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7))); 5063 /* possibly indicating MM/HE and MM/HE-E on older chips... */ 5064 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8))); 5065 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9))); 5066 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10))); 5067 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11))); 5068 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12))); 5069 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13))); 5070 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14))); 5071 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15))); 5072 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16))); 5073 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17))); 5074 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18))); 5075 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19))); 5076 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20))); 5077 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21))); 5078 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22))); 5079 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23))); 5080 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24))); 5081 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25))); 5082 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26))); 5083 for (unsigned iBit = 27; iBit < 32; iBit++) 5084 if ((uEdxGst | uEdxHst) & RT_BIT(iBit)) 5085 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit))); 5086 pHlp->pfnPrintf(pHlp, "\n"); 5087 } 5088 } 5128 * The remainder. 5129 */ 5130 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves"); 5089 5131 } 5090 5132
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