Index: /trunk/include/VBox/err.h =================================================================== --- /trunk/include/VBox/err.h (revision 54737) +++ /trunk/include/VBox/err.h (revision 54738) @@ -631,4 +631,6 @@ /** Return to ring-3 to write the MSR there. */ #define VINF_CPUM_R3_MSR_WRITE (1759) +/** Too may CPUID leaves. */ +#define VERR_TOO_MANY_CPUID_LEAVES (1760) /** @} */ Index: /trunk/include/VBox/vmm/cpum.h =================================================================== --- /trunk/include/VBox/vmm/cpum.h (revision 54737) +++ /trunk/include/VBox/vmm/cpum.h (revision 54738) @@ -305,35 +305,38 @@ /** @name CPUMCPUIDLEAF::fFlags * @{ */ -/** Indicates that ECX (the sub-leaf indicator) doesn't change when - * requesting the final leaf and all undefined leaves that follows it. - * Observed for 0x0000000b on Intel. */ -#define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0) +/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified + * and EDX containing the extended APIC ID. */ +#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0) +/** The leaf contains an APIC ID that needs changing to that of the current CPU. */ +#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1) +/** Mask of the valid flags. */ +#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0x3) /** @} */ /** - * Method used to deal with unknown CPUID leafs. + * Method used to deal with unknown CPUID leaves. * @remarks Used in patch code. */ -typedef enum CPUMUKNOWNCPUID +typedef enum CPUMUNKNOWNCPUID { /** Invalid zero value. */ - CPUMUKNOWNCPUID_INVALID = 0, + CPUMUNKNOWNCPUID_INVALID = 0, /** Use given default values (DefCpuId). */ - CPUMUKNOWNCPUID_DEFAULTS, + CPUMUNKNOWNCPUID_DEFAULTS, /** Return the last standard leaf. * Intel Sandy Bridge has been observed doing this. */ - CPUMUKNOWNCPUID_LAST_STD_LEAF, + CPUMUNKNOWNCPUID_LAST_STD_LEAF, /** Return the last standard leaf, with ecx observed. * Intel Sandy Bridge has been observed doing this. */ - CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX, + CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX, /** The register values are passed thru unmodified. */ - CPUMUKNOWNCPUID_PASSTHRU, + CPUMUNKNOWNCPUID_PASSTHRU, /** End of valid value. */ - CPUMUKNOWNCPUID_END, + CPUMUNKNOWNCPUID_END, /** Ensure 32-bit type. */ - CPUMUKNOWNCPUID_32BIT_HACK = 0x7fffffff -} CPUMUKNOWNCPUID; + CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff +} CPUMUNKNOWNCPUID; /** Pointer to unknown CPUID leaf method. */ -typedef CPUMUKNOWNCPUID *PCPUMUKNOWNCPUID; +typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID; @@ -923,5 +926,6 @@ VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu); VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue); -VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx); +VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, + uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx); VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu); VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue); @@ -1268,6 +1272,6 @@ VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch); VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves); -VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown); -VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod); +VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown); +VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod); VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX); VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor); @@ -1281,5 +1285,5 @@ VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUIDLEAF)) CPUMR3GetGuestCpuIdPatmArrayRCPtr(PVM pVM); VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUIDLEAF)) CPUMR3GetGuestCpuIdPatmArrayEndRCPtr(PVM pVM); -VMMR3_INT_DECL(CPUMUKNOWNCPUID) CPUMR3GetGuestCpuIdPatmUnknownLeafMethod(PVM pVM); +VMMR3_INT_DECL(CPUMUNKNOWNCPUID) CPUMR3GetGuestCpuIdPatmUnknownLeafMethod(PVM pVM); /* Legacy: */ VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM); Index: /trunk/include/VBox/vmm/cpum.mac =================================================================== --- /trunk/include/VBox/vmm/cpum.mac (revision 54737) +++ /trunk/include/VBox/vmm/cpum.mac (revision 54738) @@ -43,5 +43,5 @@ .fFlags resd 1 endstruc -%define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0) +%define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0) ;; @@ -56,10 +56,10 @@ -;; @name Method used to deal with unknown CPUID leafs. +;; @name Method used to deal with unknown CPUID leaves. ;; @{ -%define CPUMUKNOWNCPUID_DEFAULTS 1 -%define CPUMUKNOWNCPUID_LAST_STD_LEAF 2 -%define CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX 3 -%define CPUMUKNOWNCPUID_PASSTHRU 4 +%define CPUMUNKNOWNCPUID_DEFAULTS 1 +%define CPUMUNKNOWNCPUID_LAST_STD_LEAF 2 +%define CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX 3 +%define CPUMUNKNOWNCPUID_PASSTHRU 4 ;; @} Index: /trunk/include/iprt/x86.h =================================================================== --- /trunk/include/iprt/x86.h (revision 54737) +++ /trunk/include/iprt/x86.h (revision 54738) @@ -583,4 +583,7 @@ /** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */ #define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29) + +/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */ +#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0) /** @} */ @@ -654,5 +657,5 @@ #define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31) -/** Bit 1 - CMPL - Core multi-processing legacy mode. */ +/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */ #define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1) /** Bit 2 - SVM - AMD VM extensions. */ @@ -680,5 +683,15 @@ /** Bit 13 - WDT - AMD Watchdog timer support. */ #define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13) - +/** Bit 15 - LWP - Lightweight profiling support. */ +#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15) +/** Bit 16 - FMA4 - Four operand FMA instruction support. */ +#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16) +/** Bit 19 - NodeId - Indicates support for + * MSR_C001_100C[NodeId,NodesPerProcessr]. */ +#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19) +/** Bit 21 - TBM - Trailing bit manipulation instruction support. */ +#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21) +/** Bit 22 - TopologyExtensions - . */ +#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22) /** @} */ @@ -706,4 +719,12 @@ /** Bit 8 - TSCINVAR - TSC Invariant. */ #define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8) +/** Bit 9 - CPB - TSC Invariant. */ +#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9) +/** Bit 10 - EffFreqRO - MPERF/APERF. */ +#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10) +/** Bit 11 - PFI - Processor feedback interface (see EAX). */ +#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11) +/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */ +#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12) /** @} */