Index: /trunk/include/VBox/disopcode.h =================================================================== --- /trunk/include/VBox/disopcode.h (revision 53006) +++ /trunk/include/VBox/disopcode.h (revision 53007) @@ -41,591 +41,581 @@ * @{ */ - +enum OPCODES { /** @name Full Intel X86 opcode list * @{ */ -#define OP_INVALID 0 -#define OP_OPSIZE 1 -#define OP_ADDRSIZE 2 -#define OP_SEG 3 -#define OP_REPNE 4 -#define OP_REPE 5 -#define OP_REX 6 -#define OP_LOCK 7 -#define OP_LAST_PREFIX OP_LOCK /* disassembler assumes this is the last prefix byte value!!!! */ -#define OP_AND 8 -#define OP_OR 9 -#define OP_DAA 10 -#define OP_SUB 11 -#define OP_DAS 12 -#define OP_XOR 13 -#define OP_AAA 14 -#define OP_CMP 15 -#define OP_IMM_GRP1 16 -#define OP_AAS 17 -#define OP_INC 18 -#define OP_DEC 19 -#define OP_PUSHA 20 -#define OP_POPA 21 -#define OP_BOUND 22 -#define OP_ARPL 23 -#define OP_PUSH 24 -#define OP_POP 25 -#define OP_IMUL 26 -#define OP_INSB 27 -#define OP_INSWD 28 -#define OP_OUTSB 29 -#define OP_OUTSWD 30 -#define OP_JO 31 -#define OP_JNO 32 -#define OP_JC 33 -#define OP_JNC 34 -#define OP_JE 35 -#define OP_JNE 36 -#define OP_JBE 37 -#define OP_JNBE 38 -#define OP_JS 39 -#define OP_JNS 40 -#define OP_JP 41 -#define OP_JNP 42 -#define OP_JL 43 -#define OP_JNL 44 -#define OP_JLE 45 -#define OP_JNLE 46 -#define OP_ADD 47 -#define OP_TEST 48 -#define OP_XCHG 49 -#define OP_MOV 50 -#define OP_LEA 51 -#define OP_NOP 52 -#define OP_CBW 53 -#define OP_CWD 54 -#define OP_CALL 55 -#define OP_WAIT 56 -#define OP_PUSHF 57 -#define OP_POPF 58 -#define OP_SAHF 59 -#define OP_LAHF 60 -#define OP_MOVSB 61 -#define OP_MOVSWD 62 -#define OP_CMPSB 63 -#define OP_CMPWD 64 -#define OP_STOSB 65 -#define OP_STOSWD 66 -#define OP_LODSB 67 -#define OP_LODSWD 68 -#define OP_SCASB 69 -#define OP_SCASWD 70 -#define OP_SHIFT_GRP2 71 -#define OP_RETN 72 -#define OP_LES 73 -#define OP_LDS 74 -#define OP_ENTER 75 -#define OP_LEAVE 76 -#define OP_RETF 77 -#define OP_INT3 78 -#define OP_INT 79 -#define OP_INTO 80 -#define OP_IRET 81 -#define OP_AAM 82 -#define OP_AAD 83 -#define OP_XLAT 84 -#define OP_ESCF0 85 -#define OP_ESCF1 86 -#define OP_ESCF2 87 -#define OP_ESCF3 88 -#define OP_ESCF4 89 -#define OP_ESCF5 90 -#define OP_ESCF6 91 -#define OP_ESCF7 92 -#define OP_LOOPNE 93 -#define OP_LOOPE 94 -#define OP_LOOP 95 -#define OP_JECXZ 96 -#define OP_IN 97 -#define OP_OUT 98 -#define OP_JMP 99 -#define OP_2B_ESC 100 -#define OP_ADC 101 -#define OP_SBB 102 -#define OP_HLT 103 -#define OP_CMC 104 -#define OP_UNARY_GRP3 105 -#define OP_CLC 106 -#define OP_STC 107 -#define OP_CLI 108 -#define OP_STI 109 -#define OP_CLD 110 -#define OP_STD 111 -#define OP_INC_GRP4 112 -#define OP_IND_GRP5 113 -#define OP_GRP6 114 -#define OP_GRP7 115 -#define OP_LAR 116 -#define OP_LSL 117 -#define OP_SYSCALL 118 -#define OP_CLTS 119 -#define OP_SYSRET 120 -#define OP_INVD 121 -#define OP_WBINVD 122 -#define OP_ILLUD2 123 -#define OP_FEMMS 124 -#define OP_3DNOW 125 -#define OP_MOVUPS 126 -#define OP_MOVLPS 127 -#define OP_UNPCKLPS 128 -#define OP_MOVHPS 129 -#define OP_UNPCKHPS 130 -#define OP_PREFETCH_GRP16 131 -#define OP_MOV_CR 132 -#define OP_MOVAPS 133 -#define OP_CVTPI2PS 134 -#define OP_MOVNTPS 135 -#define OP_CVTTPS2PI 136 -#define OP_CVTPS2PI 137 -#define OP_UCOMISS 138 -#define OP_COMISS 139 -#define OP_WRMSR 140 -#define OP_RDTSC 141 -#define OP_RDMSR 142 -#define OP_RDPMC 143 -#define OP_SYSENTER 144 -#define OP_SYSEXIT 145 -#define OP_PAUSE 146 -#define OP_CMOVO 147 -#define OP_CMOVNO 148 -#define OP_CMOVC 149 -#define OP_CMOVNC 150 -#define OP_CMOVZ 151 -#define OP_CMOVNZ 152 -#define OP_CMOVBE 153 -#define OP_CMOVNBE 154 -#define OP_CMOVS 155 -#define OP_CMOVNS 156 -#define OP_CMOVP 157 -#define OP_CMOVNP 158 -#define OP_CMOVL 159 -#define OP_CMOVNL 160 -#define OP_CMOVLE 161 -#define OP_CMOVNLE 162 -#define OP_MOVMSKPS 163 -#define OP_SQRTPS 164 -#define OP_RSQRTPS 165 -#define OP_RCPPS 166 -#define OP_ANDPS 167 -#define OP_ANDNPS 168 -#define OP_ORPS 169 -#define OP_XORPS 170 -#define OP_ADDPS 171 -#define OP_MULPS 172 -#define OP_CVTPS2PD 173 -#define OP_CVTDQ2PS 174 -#define OP_SUBPS 175 -#define OP_MINPS 176 -#define OP_DIVPS 177 -#define OP_MAXPS 178 -#define OP_PUNPCKLBW 179 -#define OP_PUNPCKLWD 180 -#define OP_PUNPCKLDQ 181 -#define OP_PACKSSWB 182 -#define OP_PCMPGTB 183 -#define OP_PCMPGTW 184 -#define OP_PCMPGTD 185 -#define OP_PACKUSWB 186 -#define OP_PUNPCKHBW 187 -#define OP_PUNPCKHWD 188 -#define OP_PUNPCKHDQ 189 -#define OP_PACKSSDW 190 -#define OP_MOVD 191 -#define OP_MOVQ 192 -#define OP_PSHUFW 193 -#define OP_3B_ESC4 194 -#define OP_3B_ESC5 195 - -#define OP_PCMPEQB 196 -#define OP_PCMPEQW 197 -#define OP_PCMPEQD 198 -#define OP_SETO 199 -#define OP_SETNO 200 -#define OP_SETC 201 -#define OP_SETNC 202 -#define OP_SETE 203 -#define OP_SETNE 204 -#define OP_SETBE 205 -#define OP_SETNBE 206 -#define OP_SETS 207 -#define OP_SETNS 208 -#define OP_SETP 209 -#define OP_SETNP 210 -#define OP_SETL 211 -#define OP_SETNL 212 -#define OP_SETLE 213 -#define OP_SETNLE 214 -#define OP_CPUID 215 -#define OP_BT 216 -#define OP_SHLD 217 -#define OP_RSM 218 -#define OP_BTS 219 -#define OP_SHRD 220 -#define OP_GRP15 221 -#define OP_CMPXCHG 222 -#define OP_LSS 223 -#define OP_BTR 224 -#define OP_LFS 225 -#define OP_LGS 226 -#define OP_MOVZX 227 -#define OP_GRP10_INV 228 -#define OP_GRP8 229 -#define OP_BTC 230 -#define OP_BSF 231 -#define OP_BSR 232 -#define OP_MOVSX 233 -#define OP_XADD 234 -#define OP_CMPPS 235 -#define OP_MOVNTI 236 -#define OP_PINSRW 237 -#define OP_PEXTRW 238 -#define OP_SHUFPS 239 -#define OP_GRP9 240 -#define OP_BSWAP 241 -#define OP_PSRLW 242 -#define OP_PSRLD 243 -#define OP_PSRLQ 244 -#define OP_PADDQ 245 -#define OP_PMULLW 246 -#define OP_PMOVMSKB 247 -#define OP_PSUBUSB 248 -#define OP_PSUBUSW 249 -#define OP_PMINUB 250 -#define OP_PAND 251 -#define OP_PADDUSB 252 -#define OP_PADDUSW 253 -#define OP_PMAXUB 254 -#define OP_PANDN 255 -#define OP_PAVGN 256 -#define OP_PSRAW 257 -#define OP_PSRAD 258 -#define OP_PAVGW 259 -#define OP_PMULHUW 260 -#define OP_PMULHW 261 -#define OP_MOVNTQ 262 -#define OP_PSUBSB 263 -#define OP_PSUBSW 264 -#define OP_PMINSW 265 -#define OP_POR 266 -#define OP_PADDSB 267 -#define OP_PADDSW 268 -#define OP_PMAXSW 269 -#define OP_PXOR 270 -#define OP_PSLLW 271 -#define OP_PSLLD 272 -#define OP_PSSQ 273 -#define OP_PMULUDQ 274 -#define OP_PADDWD 275 -#define OP_PADBW 276 -#define OP_PMASKMOVQ 277 -#define OP_PSUBB 278 -#define OP_PSUBW 279 - -#define OP_PSUBD 281 -#define OP_PADDB 282 -#define OP_PADDW 283 -#define OP_PADDD 284 -#define OP_MOVUPD 285 -#define OP_MOVLPD 286 -#define OP_UNPCKLPD 287 -#define OP_UNPCKHPD 288 -#define OP_MOVHPD 289 - -#define OP_MOVAPD 291 -#define OP_CVTPI2PD 292 -#define OP_MOVNTPD 293 -#define OP_CVTTPD2PI 294 -#define OP_CVTPD2PI 295 -#define OP_UCOMISD 296 -#define OP_COMISD 297 -#define OP_MOVMSKPD 298 -#define OP_SQRTPD 299 -#define OP_ANDPD 301 -#define OP_ANDNPD 302 -#define OP_ORPD 303 -#define OP_XORPD 304 -#define OP_ADDPD 305 -#define OP_MULPD 306 -#define OP_CVTPD2PS 307 -#define OP_CVTPS2DQ 308 -#define OP_SUBPD 309 -#define OP_MINPD 310 -#define OP_DIVPD 311 -#define OP_MAXPD 312 - -#define OP_GRP12 313 -#define OP_GRP13 314 -#define OP_GRP14 315 -#define OP_EMMS 316 -#define OP_MMX_UD78 317 -#define OP_MMX_UD79 318 -#define OP_MMX_UD7A 319 -#define OP_MMX_UD7B 320 -#define OP_MMX_UD7C 321 -#define OP_MMX_UD7D 322 - - -#define OP_PUNPCKLQDQ 325 -#define OP_PUNPCKHQD 326 - -#define OP_MOVDQA 328 -#define OP_PSHUFD 329 - - - -#define OP_CMPPD 334 -#define OP_SHUFPD 337 - - -#define OP_CVTTPD2DQ 353 -#define OP_MOVNTDQ 354 - -#define OP_PSHUFB 355 -#define OP_PHADDW 356 -#define OP_PHADDD 357 -#define OP_PHADDSW 358 -#define OP_PMADDUBSW 359 -#define OP_PHSUBW 360 -#define OP_PHSUBD 361 -#define OP_PHSUBSW 362 -#define OP_PSIGNB 363 -#define OP_PSIGNW 364 -#define OP_PSIGND 365 -#define OP_PMULHRSW 366 -#define OP_PBLENDVB 367 -#define OP_BLENDVPS 368 -#define OP_BLENDVPD 369 -#define OP_PTEST 370 -#define OP_PABSB 371 -#define OP_PABSW 372 -#define OP_PABSD 373 - -#define OP_PMASKMOVDQU 376 -#define OP_MOVSD 377 -#define OP_CVTSI2SD 378 -#define OP_CVTTSD2SI 379 -#define OP_CVTSD2SI 380 -#define OP_SQRTSD 381 -#define OP_ADDSD 382 -#define OP_MULSD 383 -#define OP_CVTSD2SS 384 -#define OP_SUBSD 385 -#define OP_MINSD 386 -#define OP_DIVSD 387 -#define OP_MAXSD 388 -#define OP_PSHUFLW 389 -#define OP_CMPSD 390 -#define OP_MOVDQ2Q 391 -#define OP_CVTPD2DQ 392 -#define OP_MOVSS 393 -#define OP_CVTSI2SS 394 -#define OP_CVTTSS2SI 395 -#define OP_CVTSS2SI 396 -#define OP_SQRTSS 397 -#define OP_RSQRTSS 398 -#define OP_ADDSS 399 -#define OP_MULSS 401 -#define OP_CVTTPS2DQ 403 -#define OP_SUBSS 404 -#define OP_MINSS 405 -#define OP_DIVSS 406 -#define OP_MAXSS 407 -#define OP_MOVDQU 408 -#define OP_PSHUFHW 409 -#define OP_CMPSS 410 -#define OP_MOVQ2DQ 411 -#define OP_CVTDQ2PD 412 + OP_INVALID, + OP_OPSIZE, + OP_ADDRSIZE, + OP_SEG, + OP_REPNE, + OP_REPE, + OP_REX, + OP_LOCK, + OP_LAST_PREFIX = OP_LOCK, /* Last prefix for disassembler */ + OP_AND, + OP_OR, + OP_DAA, + OP_SUB, + OP_DAS, + OP_XOR, + OP_AAA, + OP_CMP, + OP_IMM_GRP1, + OP_AAS, + OP_INC, + OP_DEC, + OP_PUSHA, + OP_POPA, + OP_BOUND, + OP_ARPL, + OP_PUSH, + OP_POP, + OP_IMUL, + OP_INSB, + OP_INSWD, + OP_OUTSB, + OP_OUTSWD, + OP_JO, + OP_JNO, + OP_JC, + OP_JNC, + OP_JE, + OP_JNE, + OP_JBE, + OP_JNBE, + OP_JS, + OP_JNS, + OP_JP, + OP_JNP, + OP_JL, + OP_JNL, + OP_JLE, + OP_JNLE, + OP_ADD, + OP_TEST, + OP_XCHG, + OP_MOV, + OP_LEA, + OP_NOP, + OP_CBW, + OP_CWD, + OP_CALL, + OP_WAIT, + OP_PUSHF, + OP_POPF, + OP_SAHF, + OP_LAHF, + OP_MOVSB, + OP_MOVSWD, + OP_CMPSB, + OP_CMPWD, + OP_STOSB, + OP_STOSWD, + OP_LODSB, + OP_LODSWD, + OP_SCASB, + OP_SCASWD, + OP_SHIFT_GRP2, + OP_RETN, + OP_LES, + OP_LDS, + OP_ENTER, + OP_LEAVE, + OP_RETF, + OP_INT3, + OP_INT, + OP_INTO, + OP_IRET, + OP_AAM, + OP_AAD, + OP_XLAT, + OP_ESCF0, + OP_ESCF1, + OP_ESCF2, + OP_ESCF3, + OP_ESCF4, + OP_ESCF5, + OP_ESCF6, + OP_ESCF7, + OP_LOOPNE, + OP_LOOPE, + OP_LOOP, + OP_JECXZ, + OP_IN, + OP_OUT, + OP_JMP, + OP_2B_ESC, + OP_ADC, + OP_SBB, + OP_HLT, + OP_CMC, + OP_UNARY_GRP3, + OP_CLC, + OP_STC, + OP_CLI, + OP_STI, + OP_CLD, + OP_STD, + OP_INC_GRP4, + OP_IND_GRP5, + OP_GRP6, + OP_GRP7, + OP_LAR, + OP_LSL, + OP_SYSCALL, + OP_CLTS, + OP_SYSRET, + OP_INVD, + OP_WBINVD, + OP_ILLUD2, + OP_FEMMS, + OP_3DNOW, + OP_MOVUPS, + OP_MOVLPS, + OP_UNPCKLPS, + OP_MOVHPS, + OP_UNPCKHPS, + OP_PREFETCH_GRP16, + OP_MOV_CR, + OP_MOVAPS, + OP_CVTPI2PS, + OP_MOVNTPS, + OP_CVTTPS2PI, + OP_CVTPS2PI, + OP_UCOMISS, + OP_COMISS, + OP_WRMSR, + OP_RDTSC, + OP_RDMSR, + OP_RDPMC, + OP_SYSENTER, + OP_SYSEXIT, + OP_PAUSE, + OP_CMOVO, + OP_CMOVNO, + OP_CMOVC, + OP_CMOVNC, + OP_CMOVZ, + OP_CMOVNZ, + OP_CMOVBE, + OP_CMOVNBE, + OP_CMOVS, + OP_CMOVNS, + OP_CMOVP, + OP_CMOVNP, + OP_CMOVL, + OP_CMOVNL, + OP_CMOVLE, + OP_CMOVNLE, + OP_MOVMSKPS, + OP_SQRTPS, + OP_RSQRTPS, + OP_RCPPS, + OP_ANDPS, + OP_ANDNPS, + OP_ORPS, + OP_XORPS, + OP_ADDPS, + OP_MULPS, + OP_CVTPS2PD, + OP_CVTDQ2PS, + OP_SUBPS, + OP_MINPS, + OP_DIVPS, + OP_MAXPS, + OP_PUNPCKLBW, + OP_PUNPCKLWD, + OP_PUNPCKLDQ, + OP_PACKSSWB, + OP_PCMPGTB, + OP_PCMPGTW, + OP_PCMPGTD, + OP_PACKUSWB, + OP_PUNPCKHBW, + OP_PUNPCKHWD, + OP_PUNPCKHDQ, + OP_PACKSSDW, + OP_MOVD, + OP_MOVQ, + OP_PSHUFW, + OP_3B_ESC4, + OP_3B_ESC5, + OP_PCMPEQB, + OP_PCMPEQW, + OP_PCMPEQD, + OP_SETO, + OP_SETNO, + OP_SETC, + OP_SETNC, + OP_SETE, + OP_SETNE, + OP_SETBE, + OP_SETNBE, + OP_SETS, + OP_SETNS, + OP_SETP, + OP_SETNP, + OP_SETL, + OP_SETNL, + OP_SETLE, + OP_SETNLE, + OP_CPUID, + OP_BT, + OP_SHLD, + OP_RSM, + OP_BTS, + OP_SHRD, + OP_GRP15, + OP_CMPXCHG, + OP_LSS, + OP_BTR, + OP_LFS, + OP_LGS, + OP_MOVZX, + OP_GRP10_INV, + OP_GRP8, + OP_BTC, + OP_BSF, + OP_BSR, + OP_MOVSX, + OP_XADD, + OP_CMPPS, + OP_MOVNTI, + OP_PINSRW, + OP_PEXTRW, + OP_SHUFPS, + OP_GRP9, + OP_BSWAP, + OP_PSRLW, + OP_PSRLD, + OP_PSRLQ, + OP_PADDQ, + OP_PMULLW, + OP_PMOVMSKB, + OP_PSUBUSB, + OP_PSUBUSW, + OP_PMINUB, + OP_PAND, + OP_PADDUSB, + OP_PADDUSW, + OP_PMAXUB, + OP_PANDN, + OP_PAVGN, + OP_PSRAW, + OP_PSRAD, + OP_PAVGW, + OP_PMULHUW, + OP_PMULHW, + OP_MOVNTQ, + OP_PSUBSB, + OP_PSUBSW, + OP_PMINSW, + OP_POR, + OP_PADDSB, + OP_PADDSW, + OP_PMAXSW, + OP_PXOR, + OP_PSLLW, + OP_PSLLD, + OP_PSSQ, + OP_PMULUDQ, + OP_PADDWD, + OP_PADBW, + OP_PMASKMOVQ, + OP_PSUBB, + OP_PSUBW, + OP_PSUBD, + OP_PADDB, + OP_PADDW, + OP_PADDD, + OP_MOVUPD, + OP_MOVLPD, + OP_UNPCKLPD, + OP_UNPCKHPD, + OP_MOVHPD, + OP_MOVAPD, + OP_CVTPI2PD, + OP_MOVNTPD, + OP_CVTTPD2PI, + OP_CVTPD2PI, + OP_UCOMISD, + OP_COMISD, + OP_MOVMSKPD, + OP_SQRTPD, + OP_ANDPD, + OP_ANDNPD, + OP_ORPD, + OP_XORPD, + OP_ADDPD, + OP_MULPD, + OP_CVTPD2PS, + OP_CVTPS2DQ, + OP_SUBPD, + OP_MINPD, + OP_DIVPD, + OP_MAXPD, + OP_GRP12, + OP_GRP13, + OP_GRP14, + OP_EMMS, + OP_MMX_UD78, + OP_MMX_UD79, + OP_MMX_UD7A, + OP_MMX_UD7B, + OP_MMX_UD7C, + OP_MMX_UD7D, + OP_PUNPCKLQDQ, + OP_PUNPCKHQD, + OP_MOVDQA, + OP_PSHUFD, + OP_CMPPD, + OP_SHUFPD, + OP_CVTTPD2DQ, + OP_MOVNTDQ, + OP_PSHUFB, + OP_PHADDW, + OP_PHADDD, + OP_PHADDSW, + OP_PMADDUBSW, + OP_PHSUBW, + OP_PHSUBD, + OP_PHSUBSW, + OP_PSIGNB, + OP_PSIGNW, + OP_PSIGND, + OP_PMULHRSW, + OP_PBLENDVB, + OP_BLENDVPS, + OP_BLENDVPD, + OP_PTEST, + OP_PABSB, + OP_PABSW, + OP_PABSD, + OP_MOVBEGM, + OP_MOVBEMG, + OP_CRC32GDEB, + OP_CRC32GDEY, + OP_POPCNT, + OP_TZCNT, + OP_LZCNT, + OP_ADCX, + OP_ADOX, + OP_ANDN, + OP_BZHI, + OP_BEXTR, + OP_PMASKMOVDQU, + OP_MOVSD, + OP_CVTSI2SD, + OP_CVTTSD2SI, + OP_CVTSD2SI, + OP_SQRTSD, + OP_ADDSD, + OP_MULSD, + OP_CVTSD2SS, + OP_SUBSD, + OP_MINSD, + OP_DIVSD, + OP_MAXSD, + OP_PSHUFLW, + OP_CMPSD, + OP_MOVDQ2Q, + OP_CVTPD2DQ, + OP_MOVSS, + OP_CVTSI2SS, + OP_CVTTSS2SI, + OP_CVTSS2SI, + OP_SQRTSS, + OP_RSQRTSS, + OP_ADDSS, + OP_MULSS, + OP_CVTTPS2DQ, + OP_SUBSS, + OP_MINSS, + OP_DIVSS, + OP_MAXSS, + OP_MOVDQU, + OP_PSHUFHW, + OP_CMPSS, + OP_MOVQ2DQ, + OP_CVTDQ2PD, /** @} */ /** @name Floating point ops - * @{ - */ -#define OP_FADD 413 -#define OP_FMUL 414 -#define OP_FCOM 415 -#define OP_FCOMP 416 -#define OP_FSUB 417 -#define OP_FSUBR 418 -#define OP_FDIV 419 -#define OP_FDIVR 420 -#define OP_FLD 421 -#define OP_FST 422 -#define OP_FSTP 423 -#define OP_FLDENV 424 - -#define OP_FSTENV 426 -#define OP_FSTCW 427 -#define OP_FXCH 428 -#define OP_FNOP 429 -#define OP_FCHS 430 -#define OP_FABS 431 - -#define OP_FLD1 433 -#define OP_FLDL2T 434 -#define OP_FLDL2E 435 -#define OP_FLDPI 436 -#define OP_FLDLG2 437 -#define OP_FLDLN2 438 -#define OP_FLDZ 439 -#define OP_F2XM1 440 -#define OP_FYL2X 441 -#define OP_FPTAN 442 -#define OP_FPATAN 443 -#define OP_FXTRACT 444 -#define OP_FREM1 445 -#define OP_FDECSTP 446 -#define OP_FINCSTP 447 -#define OP_FPREM 448 -#define OP_FYL2XP1 449 -#define OP_FSQRT 450 -#define OP_FSINCOS 451 -#define OP_FRNDINT 452 -#define OP_FSCALE 453 -#define OP_FSIN 454 -#define OP_FCOS 455 -#define OP_FIADD 456 -#define OP_FIMUL 457 -#define OP_FISUB 460 -#define OP_FISUBR 461 -#define OP_FIDIV 462 -#define OP_FIDIVR 463 -#define OP_FCMOVB 464 -#define OP_FCMOVE 465 -#define OP_FCMOVBE 466 -#define OP_FCMOVU 467 -#define OP_FUCOMPP 468 -#define OP_FILD 469 -#define OP_FIST 470 -#define OP_FISTP 471 -#define OP_FCMOVNB 474 -#define OP_FCMOVNE 475 -#define OP_FCMOVNBE 476 -#define OP_FCMOVNU 477 -#define OP_FCLEX 478 -#define OP_FINIT 479 -#define OP_FUCOMI 480 -#define OP_FCOMI 481 -#define OP_FRSTOR 482 -#define OP_FSAVE 483 -#define OP_FNSTSW 484 -#define OP_FFREE 485 -#define OP_FUCOM 486 -#define OP_FUCOMP 487 -#define OP_FICOM 490 -#define OP_FICOMP 491 -#define OP_FADDP 496 -#define OP_FMULP 497 -#define OP_FCOMPP 498 -#define OP_FSUBRP 499 -#define OP_FSUBP 500 -#define OP_FDIVRP 501 -#define OP_FDIVP 502 -#define OP_FBLD 503 -#define OP_FBSTP 504 -#define OP_FCOMIP 506 -#define OP_FUCOMIP 507 + * @{ */ + OP_FADD, + OP_FMUL, + OP_FCOM, + OP_FCOMP, + OP_FSUB, + OP_FSUBR, + OP_FDIV, + OP_FDIVR, + OP_FLD, + OP_FST, + OP_FSTP, + OP_FLDENV, + OP_FSTENV, + OP_FSTCW, + OP_FXCH, + OP_FNOP, + OP_FCHS, + OP_FABS, + OP_FLD1, + OP_FLDL2T, + OP_FLDL2E, + OP_FLDPI, + OP_FLDLG2, + OP_FLDLN2, + OP_FLDZ, + OP_F2XM1, + OP_FYL2X, + OP_FPTAN, + OP_FPATAN, + OP_FXTRACT, + OP_FREM1, + OP_FDECSTP, + OP_FINCSTP, + OP_FPREM, + OP_FYL2XP1, + OP_FSQRT, + OP_FSINCOS, + OP_FRNDINT, + OP_FSCALE, + OP_FSIN, + OP_FCOS, + OP_FIADD, + OP_FIMUL, + OP_FISUB, + OP_FISUBR, + OP_FIDIV, + OP_FIDIVR, + OP_FCMOVB, + OP_FCMOVE, + OP_FCMOVBE, + OP_FCMOVU, + OP_FUCOMPP, + OP_FILD, + OP_FIST, + OP_FISTP, + OP_FCMOVNB, + OP_FCMOVNE, + OP_FCMOVNBE, + OP_FCMOVNU, + OP_FCLEX, + OP_FINIT, + OP_FUCOMI, + OP_FCOMI, + OP_FRSTOR, + OP_FSAVE, + OP_FNSTSW, + OP_FFREE, + OP_FUCOM, + OP_FUCOMP, + OP_FICOM, + OP_FICOMP, + OP_FADDP, + OP_FMULP, + OP_FCOMPP, + OP_FSUBRP, + OP_FSUBP, + OP_FDIVRP, + OP_FDIVP, + OP_FBLD, + OP_FBSTP, + OP_FCOMIP, + OP_FUCOMIP, /** @} */ /** @name 3DNow! - * @{ - */ -#define OP_PI2FW 508 -#define OP_PI2FD 509 -#define OP_PF2IW 510 -#define OP_PF2ID 511 -#define OP_PFPNACC 512 -#define OP_PFCMPGE 513 -#define OP_PFMIN 514 -#define OP_PFRCP 515 -#define OP_PFRSQRT 516 -#define OP_PFSUB 517 -#define OP_PFADD 518 -#define OP_PFCMPGT 519 -#define OP_PFMAX 520 -#define OP_PFRCPIT1 521 -#define OP_PFRSQRTIT1 522 -#define OP_PFSUBR 523 -#define OP_PFACC 524 -#define OP_PFCMPEQ 525 -#define OP_PFMUL 526 -#define OP_PFRCPIT2 527 -#define OP_PFMULHRW 528 -#define OP_PFSWAPD 529 -#define OP_PAVGUSB 530 -#define OP_PFNACC 531 -#define OP_ROL 532 -#define OP_ROR 533 -#define OP_RCL 534 -#define OP_RCR 535 -#define OP_SHL 536 -#define OP_SHR 537 -#define OP_SAR 538 -#define OP_NOT 539 -#define OP_NEG 540 -#define OP_MUL 541 -#define OP_DIV 542 -#define OP_IDIV 543 -#define OP_SLDT 544 -#define OP_STR 545 -#define OP_LLDT 546 -#define OP_LTR 547 -#define OP_VERR 548 -#define OP_VERW 549 -#define OP_SGDT 550 -#define OP_LGDT 551 -#define OP_SIDT 552 -#define OP_LIDT 553 -#define OP_SMSW 554 -#define OP_LMSW 555 -#define OP_INVLPG 556 -#define OP_CMPXCHG8B 557 -#define OP_PSLLQ 558 -#define OP_PSRLDQ 559 -#define OP_PSLLDQ 560 -#define OP_FXSAVE 561 -#define OP_FXRSTOR 562 -#define OP_LDMXCSR 563 -#define OP_STMXCSR 564 -#define OP_LFENCE 565 -#define OP_MFENCE 566 -#define OP_SFENCE 567 -#define OP_PREFETCH 568 -#define OP_MONITOR 569 -#define OP_MWAIT 570 -#define OP_CLFLUSH 571 - -#define OP_MOV_DR 600 -#define OP_MOV_TR 601 - -#define OP_SWAPGS 610 - + * @{ */ + OP_PI2FW, + OP_PI2FD, + OP_PF2IW, + OP_PF2ID, + OP_PFPNACC, + OP_PFCMPGE, + OP_PFMIN, + OP_PFRCP, + OP_PFRSQRT, + OP_PFSUB, + OP_PFADD, + OP_PFCMPGT, + OP_PFMAX, + OP_PFRCPIT1, + OP_PFRSQRTIT1, + OP_PFSUBR, + OP_PFACC, + OP_PFCMPEQ, + OP_PFMUL, + OP_PFRCPIT2, + OP_PFMULHRW, + OP_PFSWAPD, + OP_PAVGUSB, + OP_PFNACC, + OP_ROL, + OP_ROR, + OP_RCL, + OP_RCR, + OP_SHL, + OP_SHR, + OP_SAR, + OP_NOT, + OP_NEG, + OP_MUL, + OP_DIV, + OP_IDIV, + OP_SLDT, + OP_STR, + OP_LLDT, + OP_LTR, + OP_VERR, + OP_VERW, + OP_SGDT, + OP_LGDT, + OP_SIDT, + OP_LIDT, + OP_SMSW, + OP_LMSW, + OP_INVLPG, + OP_CMPXCHG8B, + OP_PSLLQ, + OP_PSRLDQ, + OP_PSLLDQ, + OP_FXSAVE, + OP_FXRSTOR, + OP_LDMXCSR, + OP_STMXCSR, + OP_LFENCE, + OP_MFENCE, + OP_SFENCE, + OP_PREFETCH, + OP_MONITOR, + OP_MWAIT, + OP_CLFLUSH, + OP_MOV_DR, + OP_MOV_TR, + OP_SWAPGS, /** @name VT-x instructions - * @{ */ -#define OP_VMREAD 650 -#define OP_VMWRITE 651 -#define OP_VMCALL 652 -#define OP_VMXON 653 -#define OP_VMXOFF 654 -#define OP_VMCLEAR 655 -#define OP_VMLAUNCH 656 -#define OP_VMRESUME 657 -#define OP_VMPTRLD 658 -#define OP_VMPTRST 659 -#define OP_INVEPT 660 -#define OP_INVVPID 661 +* @{ */ + OP_VMREAD, + OP_VMWRITE, + OP_VMCALL, + OP_VMXON, + OP_VMXOFF, + OP_VMCLEAR, + OP_VMLAUNCH, + OP_VMRESUME, + OP_VMPTRLD, + OP_VMPTRST, + OP_INVEPT, + OP_INVVPID, /** @} */ - /** @name 64 bits instruction * @{ */ -#define OP_MOVSXD 700 -/** @} */ - + + OP_MOVSXD /** @} */ - +}; +/** @} */ /** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1, @@ -636,102 +626,104 @@ /* NOTE: Register order is important for translations!! */ -#define OP_PARM_NONE 0 -#define OP_PARM_REG_EAX 1 -#define OP_PARM_REG_GEN32_START OP_PARM_REG_EAX -#define OP_PARM_REG_ECX 2 -#define OP_PARM_REG_EDX 3 -#define OP_PARM_REG_EBX 4 -#define OP_PARM_REG_ESP 5 -#define OP_PARM_REG_EBP 6 -#define OP_PARM_REG_ESI 7 -#define OP_PARM_REG_EDI 8 -#define OP_PARM_REG_GEN32_END OP_PARM_REG_EDI - -#define OP_PARM_REG_ES 9 -#define OP_PARM_REG_SEG_START OP_PARM_REG_ES -#define OP_PARM_REG_CS 10 -#define OP_PARM_REG_SS 11 -#define OP_PARM_REG_DS 12 -#define OP_PARM_REG_FS 13 -#define OP_PARM_REG_GS 14 -#define OP_PARM_REG_SEG_END OP_PARM_REG_GS - -#define OP_PARM_REG_AX 15 -#define OP_PARM_REG_GEN16_START OP_PARM_REG_AX -#define OP_PARM_REG_CX 16 -#define OP_PARM_REG_DX 17 -#define OP_PARM_REG_BX 18 -#define OP_PARM_REG_SP 19 -#define OP_PARM_REG_BP 20 -#define OP_PARM_REG_SI 21 -#define OP_PARM_REG_DI 22 -#define OP_PARM_REG_GEN16_END OP_PARM_REG_DI - -#define OP_PARM_REG_AL 23 -#define OP_PARM_REG_GEN8_START OP_PARM_REG_AL -#define OP_PARM_REG_CL 24 -#define OP_PARM_REG_DL 25 -#define OP_PARM_REG_BL 26 -#define OP_PARM_REG_AH 27 -#define OP_PARM_REG_CH 28 -#define OP_PARM_REG_DH 29 -#define OP_PARM_REG_BH 30 -#define OP_PARM_REG_GEN8_END OP_PARM_REG_BH - -#define OP_PARM_REGFP_0 31 -#define OP_PARM_REG_FP_START OP_PARM_REGFP_0 -#define OP_PARM_REGFP_1 32 -#define OP_PARM_REGFP_2 33 -#define OP_PARM_REGFP_3 34 -#define OP_PARM_REGFP_4 35 -#define OP_PARM_REGFP_5 36 -#define OP_PARM_REGFP_6 37 -#define OP_PARM_REGFP_7 38 -#define OP_PARM_REG_FP_END OP_PARM_REGFP_7 - -#define OP_PARM_NTA 39 -#define OP_PARM_T0 40 -#define OP_PARM_T1 41 -#define OP_PARM_T2 42 - -#define OP_PARM_1 43 - -#define OP_PARM_REX 50 -#define OP_PARM_REX_START OP_PARM_REX -#define OP_PARM_REX_B 51 -#define OP_PARM_REX_X 52 -#define OP_PARM_REX_XB 53 -#define OP_PARM_REX_R 54 -#define OP_PARM_REX_RB 55 -#define OP_PARM_REX_RX 56 -#define OP_PARM_REX_RXB 57 -#define OP_PARM_REX_W 58 -#define OP_PARM_REX_WB 59 -#define OP_PARM_REX_WX 60 -#define OP_PARM_REX_WXB 61 -#define OP_PARM_REX_WR 62 -#define OP_PARM_REX_WRB 63 -#define OP_PARM_REX_WRX 64 -#define OP_PARM_REX_WRXB 65 - -#define OP_PARM_REG_RAX 100 -#define OP_PARM_REG_GEN64_START OP_PARM_REG_RAX -#define OP_PARM_REG_RCX 101 -#define OP_PARM_REG_RDX 102 -#define OP_PARM_REG_RBX 103 -#define OP_PARM_REG_RSP 104 -#define OP_PARM_REG_RBP 105 -#define OP_PARM_REG_RSI 106 -#define OP_PARM_REG_RDI 107 -#define OP_PARM_REG_R8 108 -#define OP_PARM_REG_R9 109 -#define OP_PARM_REG_R10 110 -#define OP_PARM_REG_R11 111 -#define OP_PARM_REG_R12 112 -#define OP_PARM_REG_R13 113 -#define OP_PARM_REG_R14 114 -#define OP_PARM_REG_R15 115 -#define OP_PARM_REG_GEN64_END OP_PARM_REG_R15 - +enum OP_PARM +{ + OP_PARM_NONE, + + OP_PARM_REG_EAX, + OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX, + OP_PARM_REG_ECX, + OP_PARM_REG_EDX, + OP_PARM_REG_EBX, + OP_PARM_REG_ESP, + OP_PARM_REG_EBP, + OP_PARM_REG_ESI, + OP_PARM_REG_EDI, + OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI, + + OP_PARM_REG_ES, + OP_PARM_REG_SEG_START = OP_PARM_REG_ES, + OP_PARM_REG_CS, + OP_PARM_REG_SS, + OP_PARM_REG_DS, + OP_PARM_REG_FS, + OP_PARM_REG_GS, + OP_PARM_REG_SEG_END = OP_PARM_REG_GS, + + OP_PARM_REG_AX, + OP_PARM_REG_GEN16_START = OP_PARM_REG_AX, + OP_PARM_REG_CX, + OP_PARM_REG_DX, + OP_PARM_REG_BX, + OP_PARM_REG_SP, + OP_PARM_REG_BP, + OP_PARM_REG_SI, + OP_PARM_REG_DI, + OP_PARM_REG_GEN16_END = OP_PARM_REG_DI, + + OP_PARM_REG_AL, + OP_PARM_REG_GEN8_START = OP_PARM_REG_AL, + OP_PARM_REG_CL, + OP_PARM_REG_DL, + OP_PARM_REG_BL, + OP_PARM_REG_AH, + OP_PARM_REG_CH, + OP_PARM_REG_DH, + OP_PARM_REG_BH, + OP_PARM_REG_GEN8_END = OP_PARM_REG_BH, + + OP_PARM_REGFP_0, + OP_PARM_REG_FP_START = OP_PARM_REGFP_0, + OP_PARM_REGFP_1, + OP_PARM_REGFP_2, + OP_PARM_REGFP_3, + OP_PARM_REGFP_4, + OP_PARM_REGFP_5, + OP_PARM_REGFP_6, + OP_PARM_REGFP_7, + OP_PARM_REG_FP_END = OP_PARM_REGFP_7, + + OP_PARM_NTA, + OP_PARM_T0, + OP_PARM_T1, + OP_PARM_T2, + OP_PARM_1, + + OP_PARM_REX, + OP_PARM_REX_START = OP_PARM_REX, + OP_PARM_REX_B, + OP_PARM_REX_X, + OP_PARM_REX_XB, + OP_PARM_REX_R, + OP_PARM_REX_RB, + OP_PARM_REX_RX, + OP_PARM_REX_RXB, + OP_PARM_REX_W, + OP_PARM_REX_WB, + OP_PARM_REX_WX, + OP_PARM_REX_WXB, + OP_PARM_REX_WR, + OP_PARM_REX_WRB, + OP_PARM_REX_WRX, + OP_PARM_REX_WRXB, + + OP_PARM_REG_RAX, + OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX, + OP_PARM_REG_RCX, + OP_PARM_REG_RDX, + OP_PARM_REG_RBX, + OP_PARM_REG_RSP, + OP_PARM_REG_RBP, + OP_PARM_REG_RSI, + OP_PARM_REG_RDI, + OP_PARM_REG_R8, + OP_PARM_REG_R9, + OP_PARM_REG_R10, + OP_PARM_REG_R11, + OP_PARM_REG_R12, + OP_PARM_REG_R13, + OP_PARM_REG_R14, + OP_PARM_REG_R15, + OP_PARM_REG_GEN64_END = OP_PARM_REG_R15 +}; #define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0) @@ -779,4 +771,5 @@ #define OP_PARM_w 0xF #define OP_PARM_z 0x10 +#define OP_PARM_y 0x11 @@ -789,4 +782,5 @@ #define OP_PARM_Ev (OP_PARM_E+OP_PARM_v) #define OP_PARM_Ew (OP_PARM_E+OP_PARM_w) +#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y) #define OP_PARM_Fv (OP_PARM_F+OP_PARM_v) #define OP_PARM_Gb (OP_PARM_G+OP_PARM_b) @@ -794,4 +788,5 @@ #define OP_PARM_Gv (OP_PARM_G+OP_PARM_v) #define OP_PARM_Gw (OP_PARM_G+OP_PARM_w) +#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y) #define OP_PARM_Ib (OP_PARM_I+OP_PARM_b) #define OP_PARM_Id (OP_PARM_I+OP_PARM_d) @@ -810,4 +805,5 @@ #define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq) #define OP_PARM_Ms (OP_PARM_M+OP_PARM_s) +#define OP_PARM_My (OP_PARM_M+OP_PARM_y) #define OP_PARM_Ob (OP_PARM_O+OP_PARM_b) #define OP_PARM_Ov (OP_PARM_O+OP_PARM_v) Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 53006) +++ /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 53007) @@ -813,5 +813,5 @@ subtype = (pDis->uAddrMode == DISCPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d; else - if (subtype == OP_PARM_v || subtype == OP_PARM_NONE) + if (subtype == OP_PARM_v || subtype == OP_PARM_NONE || subtype == OP_PARM_y) { switch (pDis->uOpMode) @@ -824,5 +824,6 @@ break; case DISCPUMODE_16BIT: - subtype = OP_PARM_w; + if (subtype != OP_PARM_y) + subtype = OP_PARM_w; break; default: @@ -1915,5 +1916,11 @@ /* Cancel prefix changes. */ pDis->fPrefix &= ~DISPREFIX_OPSIZE; - pDis->uOpMode = pDis->uCpuMode; + + if (pDis->uCpuMode == DISCPUMODE_64BIT) + { + pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); + } + else + pDis->uOpMode = pDis->uCpuMode; } break; @@ -1981,5 +1988,11 @@ /* Cancel prefix changes. */ pDis->fPrefix &= ~DISPREFIX_OPSIZE; - pDis->uOpMode = pDis->uCpuMode; + if (pDis->uCpuMode == DISCPUMODE_64BIT) + { + pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); + } + else + pDis->uOpMode = pDis->uCpuMode; + } } @@ -2001,4 +2014,19 @@ } break; + + case OP_REPE: /* 0xF3 */ + if (g_apThreeByteMapX86_F30F38[pDis->bOpCode >> 4]) + { + pOpcode = g_apThreeByteMapX86_F30F38[pDis->bOpCode >> 4]; + pOpcode = &pOpcode[pDis->bOpCode & 0xf]; + + if (pOpcode->uOpcode != OP_INVALID) + { + /* Table entry is valid, so use the extension table. */ + + /* Cancel prefix changes. */ + pDis->fPrefix &= ~DISPREFIX_REP; + } + } } @@ -2031,5 +2059,11 @@ /* Cancel prefix changes. */ pDis->fPrefix &= ~DISPREFIX_OPSIZE; - pDis->uOpMode = pDis->uCpuMode; + if (pDis->uCpuMode == DISCPUMODE_64BIT) + { + pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); + } + else + pDis->uOpMode = pDis->uCpuMode; + } } Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 53006) +++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 53007) @@ -603,4 +603,5 @@ { \ case OP_PARM_v: \ + case OP_PARM_y: \ switch (pDis->uOpMode) \ { \ @@ -617,5 +618,5 @@ case OP_PARM_dq: \ if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \ - PUT_SZ("qword "); \ + PUT_SZ("dqword "); \ break; \ case OP_PARM_p: break; /* see PUT_FAR */ \ Index: /trunk/src/VBox/Disassembler/DisasmInternal.h =================================================================== --- /trunk/src/VBox/Disassembler/DisasmInternal.h (revision 53006) +++ /trunk/src/VBox/Disassembler/DisasmInternal.h (revision 53007) @@ -30,47 +30,50 @@ /** @name Index into g_apfnCalcSize and g_apfnFullDisasm. * @{ */ -#define IDX_ParseNop 0 -#define IDX_ParseModRM 1 -#define IDX_UseModRM 2 -#define IDX_ParseImmByte 3 -#define IDX_ParseImmBRel 4 -#define IDX_ParseImmUshort 5 -#define IDX_ParseImmV 6 -#define IDX_ParseImmVRel 7 -#define IDX_ParseImmAddr 8 -#define IDX_ParseFixedReg 9 -#define IDX_ParseImmUlong 10 -#define IDX_ParseImmQword 11 -#define IDX_ParseTwoByteEsc 12 -#define IDX_ParseImmGrpl 13 -#define IDX_ParseShiftGrp2 14 -#define IDX_ParseGrp3 15 -#define IDX_ParseGrp4 16 -#define IDX_ParseGrp5 17 -#define IDX_Parse3DNow 18 -#define IDX_ParseGrp6 19 -#define IDX_ParseGrp7 20 -#define IDX_ParseGrp8 21 -#define IDX_ParseGrp9 22 -#define IDX_ParseGrp10 23 -#define IDX_ParseGrp12 24 -#define IDX_ParseGrp13 25 -#define IDX_ParseGrp14 26 -#define IDX_ParseGrp15 27 -#define IDX_ParseGrp16 28 -#define IDX_ParseModFence 29 -#define IDX_ParseYv 30 -#define IDX_ParseYb 31 -#define IDX_ParseXv 32 -#define IDX_ParseXb 33 -#define IDX_ParseEscFP 34 -#define IDX_ParseNopPause 35 -#define IDX_ParseImmByteSX 36 -#define IDX_ParseImmZ 37 -#define IDX_ParseThreeByteEsc4 38 -#define IDX_ParseThreeByteEsc5 39 -#define IDX_ParseImmAddrF 40 -#define IDX_ParseInvOpModRM 41 -#define IDX_ParseMax (IDX_ParseInvOpModRM+1) +enum IDX_Parse +{ + IDX_ParseNop = 0, + IDX_ParseModRM, + IDX_UseModRM, + IDX_ParseImmByte, + IDX_ParseImmBRel, + IDX_ParseImmUshort, + IDX_ParseImmV, + IDX_ParseImmVRel, + IDX_ParseImmAddr, + IDX_ParseFixedReg, + IDX_ParseImmUlong, + IDX_ParseImmQword, + IDX_ParseTwoByteEsc, + IDX_ParseImmGrpl, + IDX_ParseShiftGrp2, + IDX_ParseGrp3, + IDX_ParseGrp4, + IDX_ParseGrp5, + IDX_Parse3DNow, + IDX_ParseGrp6, + IDX_ParseGrp7, + IDX_ParseGrp8, + IDX_ParseGrp9, + IDX_ParseGrp10, + IDX_ParseGrp12, + IDX_ParseGrp13, + IDX_ParseGrp14, + IDX_ParseGrp15, + IDX_ParseGrp16, + IDX_ParseModFence, + IDX_ParseYv, + IDX_ParseYb, + IDX_ParseXv, + IDX_ParseXb, + IDX_ParseEscFP, + IDX_ParseNopPause, + IDX_ParseImmByteSX, + IDX_ParseImmZ, + IDX_ParseThreeByteEsc4, + IDX_ParseThreeByteEsc5, + IDX_ParseImmAddrF, + IDX_ParseInvOpModRM, + IDX_ParseMax +}; /** @} */ @@ -101,4 +104,7 @@ /** Three byte opcode map with prefix 0xF2 (0xF 0x38) */ extern PCDISOPCODE const g_apThreeByteMapX86_F20F38[16]; + +/** Three byte opcode map with prefix 0xF3 (0xF 0x38) */ +extern PCDISOPCODE const g_apThreeByteMapX86_F30F38[16]; /** Three byte opcode map with prefix 0x66 (0xF 0x3A) */ Index: /trunk/src/VBox/Disassembler/DisasmTables.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmTables.cpp (revision 53006) +++ /trunk/src/VBox/Disassembler/DisasmTables.cpp (revision 53007) @@ -529,6 +529,6 @@ OP("pcmpeqd %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, DISOPTYPE_HARMLESS), OP("emms", 0, 0, 0, OP_EMMS, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), - OP("MMX UD 0x78", 0, 0, 0, OP_MMX_UD78,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), /** @todo 0x0f 0x78 VMREAD */ - OP("MMX UD 0x79", 0, 0, 0, OP_MMX_UD79,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), /** @todo 0x0f 0x79 VMWRITE */ + OP("vmread %Ey,%Gy", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMREAD, OP_PARM_Ey, OP_PARM_Gy, OP_PARM_NONE, DISOPTYPE_HARMLESS|DISOPTYPE_FORCED_64_OP_SIZE), + OP("vmwrite %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMWRITE, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS|DISOPTYPE_FORCED_64_OP_SIZE), OP("MMX UD 0x7A", 0, 0, 0, OP_MMX_UD7A,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), OP("MMX UD 0x7B", 0, 0, 0, OP_MMX_UD7B,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), @@ -792,6 +792,6 @@ OP("pcmpeqd %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Vdq, OP_PARM_Vdq, OP_PARM_NONE, DISOPTYPE_HARMLESS), INVALID_OPCODE, - OP("vmread %Ed,%Gd", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMREAD, OP_PARM_Ed, OP_PARM_Gd, OP_PARM_NONE, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED), - OP("vmwrite %Gd,%Ed", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMWRITE, OP_PARM_Gd, OP_PARM_Ed, OP_PARM_NONE, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED), + INVALID_OPCODE, + INVALID_OPCODE, INVALID_OPCODE, INVALID_OPCODE, @@ -1172,5 +1172,20 @@ /* b */ - INVALID_OPCODE_BLOCK + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + OP("popcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_POPCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + OP("tzcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_TZCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), + OP("lzcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_LZCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, /* c */ @@ -1276,4 +1291,26 @@ }; +/** Three byte opcode map (0x0F 0x38 0xFx) */ +const DISOPCODE g_aThreeByteMapX86_0F38_F[16] = +{ + /* F */ + OP("movbe %Gy,%My", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEGM, OP_PARM_Gy, OP_PARM_My, OP_PARM_NONE, DISOPTYPE_HARMLESS), + OP("movbe %My,%Gy", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEMG, OP_PARM_My, OP_PARM_Gy, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, +}; + /** These tables are mostly sparse, so use another level of indirection to save space. */ PCDISOPCODE const g_apThreeByteMapX86_0F38[16] = @@ -1310,5 +1347,5 @@ NULL, /* f */ - NULL, + &g_aThreeByteMapX86_0F38_F[0], }; @@ -1381,4 +1418,25 @@ }; +const DISOPCODE g_aThreeByteMapX86_660F38_F[16] = +{ + /* 8 */ + OP("movbe %Gw,%Mw", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEGM, OP_PARM_Gw, OP_PARM_Mw, OP_PARM_NONE, DISOPTYPE_HARMLESS), + OP("movbe %Mw,%Gw", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEMG, OP_PARM_Mw, OP_PARM_Gw, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + OP("adcx %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADCX, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, +}; + /** Three byte opcode map with prefix 0x66 (0xF 0x38) */ PCDISOPCODE const g_apThreeByteMapX86_660F38[16] = @@ -1415,5 +1473,51 @@ NULL, /* f */ - NULL, + &g_aThreeByteMapX86_660F38_F[0], +}; + +const DISOPCODE g_aThreeByteMapX86_F20F38_F[16] = +{ + /* According to Intel opcodes map in Intel® 64 and IA-32 Architectures Software Developer’s Manual dated September 2014 + it should be %Gd (always dword regardless of operand-size attribute), but from the description of the command + it is clear that REX.W prefix can change this size to 64 bit, therefore it is set to %Gy. Seems to be a mistake. */ + OP("crc32 %Gy,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEB, OP_PARM_Gy, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), + OP("crc32 %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEY, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, +}; + +const DISOPCODE g_aThreeByteMapX86_66F20F38_F[16] = +{ + /* According to Intel opcodes map in Intel® 64 and IA-32 Architectures Software Developer’s Manual dated September 2014 + it should be %Gd (always dword regardless of operand-size attribute), but from the description of the command + it is clear that REX.W prefix can change this size to 64 bit, therefore it is set to %Gy. Seems to be a mistake. */ + OP("crc32 %Gy,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEB, OP_PARM_Gy, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), + OP("crc32 %Gy,%Ew", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEY, OP_PARM_Gy, OP_PARM_Ew, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, }; @@ -1453,5 +1557,62 @@ NULL, /* f */ - NULL, + &g_aThreeByteMapX86_F20F38_F[0], +}; + +const DISOPCODE g_aThreeByteMapX86_F30F38_F[16] = +{ + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + OP("adox %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADOX, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, + INVALID_OPCODE, +}; + +/** Three byte opcode map with prefix 0xF3 (0xF 0x38) */ +PCDISOPCODE const g_apThreeByteMapX86_F30F38[16] = +{ + /* 0 */ + NULL, + /* 1 */ + NULL, + /* 2 */ + NULL, + /* 3 */ + NULL, + /* 4 */ + NULL, + /* 5 */ + NULL, + /* 6 */ + NULL, + /* 7 */ + NULL, + /* 8 */ + NULL, + /* 9 */ + NULL, + /* a */ + NULL, + /* b */ + NULL, + /* c */ + NULL, + /* d */ + NULL, + /* e */ + NULL, + /* f */ + &g_aThreeByteMapX86_F30F38_F[0], }; Index: /trunk/src/VBox/Disassembler/testcase/tstDisasm-1A.asm =================================================================== --- /trunk/src/VBox/Disassembler/testcase/tstDisasm-1A.asm (revision 53006) +++ /trunk/src/VBox/Disassembler/testcase/tstDisasm-1A.asm (revision 53007) @@ -51,7 +51,7 @@ DB 0xF0, 0x0F, 0x20, 0xC0 smsw word [edx+16] - ; invept eax, qword [ecx] + ; invept eax, dqword [ecx] DB 0x66, 0x0F, 0x38, 0x80, 0x1 - ; invept eax, qword [ecx] + ; invept eax, dqword [ecx] DB 0x66, 0x0F, 0x38, 0x81, 0x1 mov eax, dword [ecx] @@ -148,4 +148,47 @@ paddd mm1, mm3 paddd xmm1, xmm3 + +%if __YASM_VERSION_ID__ >= 001030000h ; Old yasm doesn't support the instructions below + adcx eax, ebx + adcx eax, [edi] + + adox eax, ebx + adox eax, [edi] + adox eax, [edi + 1000h] + + tzcnt ax, bx + tzcnt eax, ebx + tzcnt ax, [edi] + tzcnt eax, [edi] + tzcnt eax, [edi + 1000h] +%endif + + movbe eax, [edi] + movbe ebx, [edi + 1000h] + movbe ax, [edi] + movbe [edi], eax + + crc32 eax, bl + ;crc32 eax, bx + crc32 eax, ebx + crc32 eax, byte [edi] + ;crc32 eax, word [edi] + crc32 eax, dword [edi] + + popcnt ax, bx + popcnt eax, ebx + popcnt ax, [edi] + popcnt eax, [edi] + popcnt eax, [edi + 1000h] + + lzcnt ax, bx + lzcnt eax, ebx + lzcnt ax, [edi] + lzcnt eax, [edi] + lzcnt eax, [edi + 1000h] + + vmread eax, ebx + vmwrite eax, ebx + ENDPROC TestProc32 @@ -164,11 +207,11 @@ mov rbx, [0xfffe0080] divsd xmm1, xmm0 - ; invept rdi, qword [rsi] + ; invept rdi, dqword [rsi] DB 0x66, 0x0F, 0x38, 0x80, 0x3E - ; invept rcx, qword [rdx] + ; invept rcx, dqword [rdx] DB 0x66, 0x0F, 0x38, 0x80, 0xA - ;invvpid rdi, qword [rsi] + ;invvpid rdi, dqword [rsi] DB 0x66, 0x0F, 0x38, 0x81, 0x3E - ; invvpid rcx, qword [rdx] + ; invvpid rcx, dqword [rdx] DB 0x66, 0x0F, 0x38, 0x81, 0xA mov rdi, [rsi] @@ -234,4 +277,65 @@ movsd xmm6, xmm1 + movbe eax, [rdi] + movbe ax, [rdi] + movbe rax, [rdi] + + crc32 eax, bl + ;crc32 eax, bx + crc32 eax, ebx + crc32 eax, byte [edi] + ;crc32 eax, word [edi] + crc32 eax, dword [edi] + + crc32 rax, bl + crc32 rax, byte [rdi] + crc32 rax, qword [rdi] + +%if __YASM_VERSION_ID__ >= 001030000h ; Old yasm doesn't support the instructions below + + adcx eax, ebx + adcx rax, rbx + adcx r8, r11 + adcx r8d, edx + + adox eax, ebx + adox eax, [edi] + adox eax, [edi + 1000h] + + adox rax, rbx + adox rax, [rdi] + adox rax, [rdi + 1000h] + adox rax, [edi + 1000h] + + tzcnt ax, bx + tzcnt eax, ebx + tzcnt rax, rbx + tzcnt ax, [edi] + tzcnt eax, [edi] + tzcnt eax, [edi + 1000h] +%endif + + popcnt ax, bx + popcnt eax, ebx + popcnt rax, rbx + popcnt ax, [edi] + popcnt eax, [edi] + popcnt eax, [edi + 1000h] + popcnt rax, [rdi + 1000h] + + lzcnt ax, bx + lzcnt eax, ebx + lzcnt rax, rbx + lzcnt ax, [edi] + lzcnt eax, [edi] + lzcnt eax, [edi + 1000h] + lzcnt eax, [rdi] + lzcnt ax, [rdi] + lzcnt rax, [rdi] + lzcnt r8d, [rdi] + + vmread rax, rbx + vmwrite rax, rbx + ret ENDPROC TestProc64