Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 52549)
+++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 52550)
@@ -3964,4 +3964,5 @@
                     "         RAW Extended CPUIDs\n"
                     "     Function  eax      ebx      ecx      edx\n");
+    bool fSupportsInvariantTsc = false;
     for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
     {
@@ -3969,4 +3970,9 @@
         ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
 
+        if (   i == 7
+            && (Host.edx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR))
+        {
+            fSupportsInvariantTsc = true;
+        }
         pHlp->pfnPrintf(pHlp,
                         "Gst: %08x  %08x %08x %08x %08x%s\n"
@@ -4215,5 +4221,5 @@
     {
         uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
-
+        pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support:      %RTbool\n", fSupportsInvariantTsc);
         pHlp->pfnPrintf(pHlp, "APM Features:                   ");
         if (uEDX & RT_BIT(0))   pHlp->pfnPrintf(pHlp, " TS");
@@ -4224,6 +4230,10 @@
         if (uEDX & RT_BIT(5))   pHlp->pfnPrintf(pHlp, " STC");
         for (unsigned iBit = 6; iBit < 32; iBit++)
-            if (uEDX & RT_BIT(iBit))
+        {
+            if (uEDX & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
+                pHlp->pfnPrintf(pHlp, " TSCINVARIANT");
+            else if (uEDX & RT_BIT(iBit))
                 pHlp->pfnPrintf(pHlp, " %d", iBit);
+        }
         pHlp->pfnPrintf(pHlp, "\n");
     }