Index: /trunk/include/VBox/vmm/cpum.h
===================================================================
--- /trunk/include/VBox/vmm/cpum.h	(revision 49848)
+++ /trunk/include/VBox/vmm/cpum.h	(revision 49849)
@@ -289,7 +289,9 @@
 DECLINLINE(bool)    CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
 {
+    /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
+       than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set.  */
     return (   (pCtx->cr4 & X86_CR4_PAE)
             && CPUMIsGuestPagingEnabledEx(pCtx)
-            && !(pCtx->msrEFER & MSR_K6_EFER_LME));
+            && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
 }
 
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 49848)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 49849)
@@ -2798,7 +2798,9 @@
 VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
 {
+    /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
+       than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set.  */
     return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
         && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
-        && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
+        && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
 }