Index: /trunk/include/iprt/x86.h
===================================================================
--- /trunk/include/iprt/x86.h	(revision 48283)
+++ /trunk/include/iprt/x86.h	(revision 48284)
@@ -3269,4 +3269,17 @@
 #pragma pack(1)
 /**
+ * 16-bit IDTR.
+ */
+typedef struct X86IDTR16
+{
+    /** Offset. */
+    uint16_t    offSel;
+    /** Selector. */
+    uint16_t    uSel;
+} X86IDTR16, *PX86IDTR16;
+#pragma pack()
+
+#pragma pack(1)
+/**
  * 32-bit IDTR/GDTR.
  */
Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 48283)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 48284)
@@ -6801,5 +6801,5 @@
 
             /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
-            const size_t cbIdtEntry = 4;
+            const size_t cbIdtEntry = sizeof(X86IDTR16);
             if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pMixedCtx->idtr.cbIdt)
             {
@@ -6830,9 +6830,7 @@
 
             /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
-            uint16_t offIdtEntry    = 0;
-            RTSEL    selIdtEntry    = 0;
+            X86IDTR16 IdtEntry;
             RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
-            rc  = PGMPhysSimpleReadGCPhys(pVM, &offIdtEntry, GCPhysIdtEntry,     sizeof(offIdtEntry));
-            rc |= PGMPhysSimpleReadGCPhys(pVM, &selIdtEntry, GCPhysIdtEntry + 2, sizeof(selIdtEntry));
+            rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
             AssertRCReturn(rc, rc);
 
@@ -6847,7 +6845,7 @@
             {
                 pMixedCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
-                pMixedCtx->rip         = offIdtEntry;
-                pMixedCtx->cs.Sel      = selIdtEntry;
-                pMixedCtx->cs.u64Base  = selIdtEntry << cbIdtEntry;
+                pMixedCtx->rip         = IdtEntry.offSel;
+                pMixedCtx->cs.Sel      = IdtEntry.uSel;
+                pMixedCtx->cs.u64Base  = IdtEntry.uSel << cbIdtEntry;
                 if (   uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
                     && uVector   == X86_XCPT_PF)
Index: /trunk/src/VBox/VMM/include/HMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/HMInternal.h	(revision 48283)
+++ /trunk/src/VBox/VMM/include/HMInternal.h	(revision 48284)
@@ -555,4 +555,5 @@
         /** Current VMX_VMCS32_CTRL_ENTRY. */
         uint32_t                    u32EntryCtls;
+
         /** Physical address of the virtual APIC page for TPR caching. */
         RTHCPHYS                    HCPhysVirtApic;
@@ -610,4 +611,5 @@
         /** Last use TSC offset value. (cached) */
         uint64_t                    u64TSCOffset;
+
         /** VMCS cache. */
         VMCSCACHE                   VMCSCache;
@@ -616,12 +618,12 @@
         struct
         {
-            X86DESCATTR                 AttrCS;
-            X86DESCATTR                 AttrDS;
-            X86DESCATTR                 AttrES;
-            X86DESCATTR                 AttrFS;
-            X86DESCATTR                 AttrGS;
-            X86DESCATTR                 AttrSS;
-            X86EFLAGS                   Eflags;
-            uint32_t                    fRealOnV86Active;
+            X86DESCATTR             AttrCS;
+            X86DESCATTR             AttrDS;
+            X86DESCATTR             AttrES;
+            X86DESCATTR             AttrFS;
+            X86DESCATTR             AttrGS;
+            X86DESCATTR             AttrSS;
+            X86EFLAGS               Eflags;
+            uint32_t                fRealOnV86Active;
         } RealMode;