Index: /trunk/include/VBox/vmm/hm_vmx.h =================================================================== --- /trunk/include/VBox/vmm/hm_vmx.h (revision 48215) +++ /trunk/include/VBox/vmm/hm_vmx.h (revision 48216) @@ -861,4 +861,29 @@ /** @} */ +/** @name VMX MSRs. + * @{ + */ +typedef struct VMXMSRS +{ + uint64_t u64FeatureCtrl; + uint64_t u64BasicInfo; + VMX_CAPABILITY VmxPinCtls; + VMX_CAPABILITY VmxProcCtls; + VMX_CAPABILITY VmxProcCtls2; + VMX_CAPABILITY VmxExit; + VMX_CAPABILITY VmxEntry; + uint64_t u64Misc; + uint64_t u64Cr0Fixed0; + uint64_t u64Cr0Fixed1; + uint64_t u64Cr4Fixed0; + uint64_t u64Cr4Fixed1; + uint64_t u64VmcsEnum; + uint64_t u64Vmfunc; + uint64_t u64EptVpidCaps; +} VMXMSRS; +/** Pointer to a VMXMSRS struct. */ +typedef VMXMSRS *PVMXMSRS; +/** @} */ + /** @name VMX EFLAGS reserved bits. * @{ Index: /trunk/src/VBox/VMM/VMMR0/HMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMR0.cpp (revision 48215) +++ /trunk/src/VBox/VMM/VMMR0/HMR0.cpp (revision 48216) @@ -121,22 +121,6 @@ /** VMX MSR values */ - struct - { - uint64_t u64FeatureCtrl; - uint64_t u64BasicInfo; - VMX_CAPABILITY VmxPinCtls; - VMX_CAPABILITY VmxProcCtls; - VMX_CAPABILITY VmxProcCtls2; - VMX_CAPABILITY VmxExit; - VMX_CAPABILITY VmxEntry; - uint64_t u64Misc; - uint64_t u64Cr0Fixed0; - uint64_t u64Cr0Fixed1; - uint64_t u64Cr4Fixed0; - uint64_t u64Cr4Fixed1; - uint64_t u64VmcsEnum; - uint64_t u64Vmfunc; - uint64_t u64EptVpidCaps; - } msr; + VMXMSRS Msrs; + /* Last instruction error */ uint32_t ulLastInstrError; @@ -372,5 +356,5 @@ { /** @todo move this into a separate function. */ - g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); + g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); /* @@ -403,23 +387,23 @@ { /* Reread in case we've changed it. */ - g_HvmR0.vmx.msr.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); - - if ( (g_HvmR0.vmx.msr.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK)) - == (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK)) + g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); + + if ( (g_HvmR0.vmx.Msrs.u64FeatureCtrl & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK)) + == (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK)) { /* * Read all relevant MSRs. */ - g_HvmR0.vmx.msr.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO); - g_HvmR0.vmx.msr.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS); - g_HvmR0.vmx.msr.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS); - g_HvmR0.vmx.msr.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS); - g_HvmR0.vmx.msr.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS); - g_HvmR0.vmx.msr.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC); - g_HvmR0.vmx.msr.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0); - g_HvmR0.vmx.msr.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1); - g_HvmR0.vmx.msr.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0); - g_HvmR0.vmx.msr.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1); - g_HvmR0.vmx.msr.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM); + g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO); + g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS); + g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS); + g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS); + g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS); + g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC); + g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0); + g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1); + g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0); + g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1); + g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM); g_HvmR0.vmx.u64HostCr4 = ASMGetCR4(); g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER); @@ -427,12 +411,12 @@ g_HvmR0.uMaxAsid = 0x10000; /* exclusive */ - if (g_HvmR0.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) + if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) { - g_HvmR0.vmx.msr.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2); - if (g_HvmR0.vmx.msr.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID)) - g_HvmR0.vmx.msr.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP); - - if (g_HvmR0.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) - g_HvmR0.vmx.msr.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC); + g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2); + if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID)) + g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP); + + if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) + g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC); } @@ -455,5 +439,5 @@ /* Set revision dword at the beginning of the structure. */ - *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.u64BasicInfo); + *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo); /* Make sure we don't get rescheduled to another cpu during this probe. */ @@ -537,8 +521,8 @@ * Timer Does Not Count Down at the Rate Specified" erratum. */ - if (g_HvmR0.vmx.msr.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER) + if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER) { g_HvmR0.vmx.fUsePreemptTimer = true; - g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.u64Misc); + g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc); if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum()) g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */ @@ -840,5 +824,5 @@ /* MSR is not yet locked; we can change it ourselves here. */ ASMWrMsr(MSR_IA32_FEATURE_CONTROL, - g_HvmR0.vmx.msr.u64FeatureCtrl | MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK); + g_HvmR0.vmx.Msrs.u64FeatureCtrl | MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK); fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); } @@ -1249,21 +1233,7 @@ pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer; pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift; - pVM->hm.s.vmx.msr.u64FeatureCtrl = g_HvmR0.vmx.msr.u64FeatureCtrl; pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4; pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer; - pVM->hm.s.vmx.msr.u64BasicInfo = g_HvmR0.vmx.msr.u64BasicInfo; - pVM->hm.s.vmx.msr.VmxPinCtls = g_HvmR0.vmx.msr.VmxPinCtls; - pVM->hm.s.vmx.msr.VmxProcCtls = g_HvmR0.vmx.msr.VmxProcCtls; - pVM->hm.s.vmx.msr.VmxProcCtls2 = g_HvmR0.vmx.msr.VmxProcCtls2; - pVM->hm.s.vmx.msr.VmxExit = g_HvmR0.vmx.msr.VmxExit; - pVM->hm.s.vmx.msr.VmxEntry = g_HvmR0.vmx.msr.VmxEntry; - pVM->hm.s.vmx.msr.u64Misc = g_HvmR0.vmx.msr.u64Misc; - pVM->hm.s.vmx.msr.u64Cr0Fixed0 = g_HvmR0.vmx.msr.u64Cr0Fixed0; - pVM->hm.s.vmx.msr.u64Cr0Fixed1 = g_HvmR0.vmx.msr.u64Cr0Fixed1; - pVM->hm.s.vmx.msr.u64Cr4Fixed0 = g_HvmR0.vmx.msr.u64Cr4Fixed0; - pVM->hm.s.vmx.msr.u64Cr4Fixed1 = g_HvmR0.vmx.msr.u64Cr4Fixed1; - pVM->hm.s.vmx.msr.u64VmcsEnum = g_HvmR0.vmx.msr.u64VmcsEnum; - pVM->hm.s.vmx.msr.u64Vmfunc = g_HvmR0.vmx.msr.u64Vmfunc; - pVM->hm.s.vmx.msr.u64EptVpidCaps = g_HvmR0.vmx.msr.u64EptVpidCaps; + pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs; pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr; pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev; Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 48215) +++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 48216) @@ -729,5 +729,5 @@ { /* Write the VMCS revision dword to the VMXON region. */ - *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo); + *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo); } @@ -839,5 +839,5 @@ #endif - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap); @@ -907,5 +907,5 @@ /* Allocate the APIC-access page for trapping APIC accesses from the guest. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) { rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, @@ -924,5 +924,5 @@ /* Allocate the VM control structure (VMCS). */ - AssertReturn(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo) <= PAGE_SIZE, VERR_INTERNAL_ERROR); + AssertReturn(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE, VERR_INTERNAL_ERROR); rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs); if (RT_FAILURE(rc)) @@ -930,5 +930,5 @@ /* Allocate the Virtual-APIC page for transparent TPR accesses. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) { rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic, @@ -939,5 +939,5 @@ /* Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for transparent accesses of specific MSRs. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) { rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, @@ -1031,5 +1031,5 @@ { /* We require ALL_CONTEXT flush-type to be available on the CPU. See hmR0VmxSetupTaggedTlb(). */ - Assert(pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS); + Assert(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS); hmR0VmxFlushEpt(pVM, NULL /* pVCpu */, VMX_FLUSH_EPT_ALL_CONTEXTS); pCpu->fFlushAsidBeforeUse = false; @@ -1226,5 +1226,5 @@ if (pVM->hm.s.vmx.fVpid) { - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, GCVirt); @@ -1383,5 +1383,5 @@ * as supported by the CPU. */ - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) @@ -1554,5 +1554,5 @@ { /* Flush individual guest entries using VPID or as little as possible with EPT as supported by the CPU. */ - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) @@ -1618,9 +1618,9 @@ if (pVM->hm.s.fNestedPaging) { - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT) - { - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT) + { + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT) pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT; - else if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS) + else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS) pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS; else @@ -1632,7 +1632,7 @@ /* Make sure the write-back cacheable memory type for EPT is supported. */ - if (!(pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)) + if (!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)) { - LogRel(("hmR0VmxSetupTaggedTlb: Unsupported EPTP memory type %#x.\n", pVM->hm.s.vmx.msr.u64EptVpidCaps)); + LogRel(("hmR0VmxSetupTaggedTlb: Unsupported EPTP memory type %#x.\n", pVM->hm.s.vmx.Msrs.u64EptVpidCaps)); pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -1652,16 +1652,16 @@ if (pVM->hm.s.vmx.fVpid) { - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID) - { - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID) + { + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT) pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT; - else if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS) + else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS) pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS; else { /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */ - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) LogRel(("hmR0VmxSetupTaggedTlb: Only INDIV_ADDR supported. Ignoring VPID.\n")); - if (pVM->hm.s.vmx.msr.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS) + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS) LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n")); pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED; @@ -1705,6 +1705,6 @@ AssertPtr(pVCpu); - uint32_t val = pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */ - uint32_t zap = pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */ + uint32_t val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */ + uint32_t zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */ val |= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT /* External interrupts causes a VM-exits. */ @@ -1715,5 +1715,5 @@ if (pVM->hm.s.vmx.fUsePreemptTimer) { - Assert(pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER); + Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER); val |= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER; } @@ -1722,5 +1722,5 @@ { LogRel(("hmR0VmxSetupPinCtls: invalid pin-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n", - pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0, val, zap)); + pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0, val, zap)); pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -1749,6 +1749,6 @@ int rc = VERR_INTERNAL_ERROR_5; - uint32_t val = pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */ - uint32_t zap = pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ + uint32_t val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */ + uint32_t zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ val |= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT /* HLT causes a VM-exit. */ @@ -1761,6 +1761,6 @@ /* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */ - if ( !(pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) - || (pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)) + if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) + || (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)) { LogRel(("hmR0VmxSetupProcCtls: unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!")); @@ -1779,5 +1779,5 @@ /* Use TPR shadowing if supported by the CPU. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) { Assert(pVCpu->hm.s.vmx.HCPhysVirtApic); @@ -1799,5 +1799,5 @@ /* Use MSR-bitmaps if supported by the CPU. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) { val |= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS; @@ -1824,5 +1824,5 @@ /* Use the secondary processor-based VM-execution controls if supported by the CPU. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL; @@ -1830,5 +1830,5 @@ { LogRel(("hmR0VmxSetupProcCtls: invalid processor-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n", - pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0, val, zap)); + pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0, val, zap)); pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -1846,8 +1846,8 @@ if (RT_LIKELY(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)) { - val = pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */ - zap = pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ - - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT) + val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */ + zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ + + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT) val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT; /* WBINVD causes a VM-exit. */ @@ -1861,5 +1861,5 @@ * See Intel spec. 25.4 "Changes to instruction behaviour in VMX non-root operation". */ - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID) val |= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID; } @@ -1874,5 +1874,5 @@ /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be * done dynamically. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) { Assert(pVM->hm.s.vmx.HCPhysApicAccess); @@ -1883,8 +1883,8 @@ } - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) { val |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP; /* Enable RDTSCP support. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) hmR0VmxSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE); } @@ -1893,5 +1893,5 @@ { LogRel(("hmR0VmxSetupProcCtls: invalid secondary processor-based VM-execution controls combo! " - "cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0, val, zap)); + "cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0, val, zap)); return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; } @@ -2131,5 +2131,5 @@ /* Set revision dword at the beginning of the VMCS structure. */ - *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo); + *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo); /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */ @@ -2552,7 +2552,7 @@ /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */ - if (RT_UNLIKELY(cHostMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc))) - { - LogRel(("cHostMsrs=%u Cpu=%u\n", cHostMsrs, (unsigned)MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc))); + if (RT_UNLIKELY(cHostMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc))) + { + LogRel(("cHostMsrs=%u Cpu=%u\n", cHostMsrs, (unsigned)MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc))); pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -2616,6 +2616,6 @@ { PVM pVM = pVCpu->CTX_SUFF(pVM); - uint32_t val = pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */ - uint32_t zap = pVM->hm.s.vmx.msr.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ + uint32_t val = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */ + uint32_t zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */ @@ -2641,5 +2641,5 @@ { LogRel(("hmR0VmxLoadGuestEntryCtls: invalid VM-entry controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n", - pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0, val, zap)); + pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0, val, zap)); pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -2675,6 +2675,6 @@ { PVM pVM = pVCpu->CTX_SUFF(pVM); - uint32_t val = pVM->hm.s.vmx.msr.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */ - uint32_t zap = pVM->hm.s.vmx.msr.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ + uint32_t val = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */ + uint32_t zap = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */ /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */ @@ -2706,5 +2706,5 @@ * VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR. */ - if (pVM->hm.s.vmx.msr.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER) + if (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER) val |= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER; @@ -2712,5 +2712,5 @@ { LogRel(("hmR0VmxSetupProcCtls: invalid VM-exit controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n", - pVM->hm.s.vmx.msr.VmxExit.n.disallowed0, val, zap)); + pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0, val, zap)); pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT; return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO; @@ -3088,6 +3088,6 @@ /* Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW). */ - uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.msr.u64Cr0Fixed0 & pVM->hm.s.vmx.msr.u64Cr0Fixed1); - uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.msr.u64Cr0Fixed0 | pVM->hm.s.vmx.msr.u64Cr0Fixed1); + uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); + uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */ uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG); @@ -3316,6 +3316,6 @@ /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */ - uint64_t uSetCR4 = (pVM->hm.s.vmx.msr.u64Cr4Fixed0 & pVM->hm.s.vmx.msr.u64Cr4Fixed1); - uint64_t uZapCR4 = (pVM->hm.s.vmx.msr.u64Cr4Fixed0 | pVM->hm.s.vmx.msr.u64Cr4Fixed1); + uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); + uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); u32GuestCR4 |= uSetCR4; u32GuestCR4 &= uZapCR4; @@ -3379,5 +3379,5 @@ { /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */ - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG) { pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG; @@ -3978,5 +3978,5 @@ /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */ - if (cGuestMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc)) + if (cGuestMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc)) { LogRel(("CPU autoload/store MSR count in VMCS exceeded cGuestMsrs=%u.\n", cGuestMsrs)); @@ -6343,5 +6343,5 @@ DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu) { - if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)) + if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)) { if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)) @@ -7913,6 +7913,6 @@ * CR0. */ - uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.msr.u64Cr0Fixed0 & pVM->hm.s.vmx.msr.u64Cr0Fixed1); - uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.msr.u64Cr0Fixed0 | pVM->hm.s.vmx.msr.u64Cr0Fixed1); + uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); + uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). See Intel spec. 26.3.1 "Checks on guest Guest Control Registers, Debug Registers and MSRs." */ @@ -7934,6 +7934,6 @@ * CR4. */ - uint64_t uSetCR4 = (pVM->hm.s.vmx.msr.u64Cr4Fixed0 & pVM->hm.s.vmx.msr.u64Cr4Fixed1); - uint64_t uZapCR4 = (pVM->hm.s.vmx.msr.u64Cr4Fixed0 | pVM->hm.s.vmx.msr.u64Cr4Fixed1); + uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); + uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32Val); AssertRCBreak(rc); @@ -8354,5 +8354,5 @@ AssertRCBreak(rc); HMVMX_CHECK_BREAK( !u32ActivityState - || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.u64Misc)), + || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)), VMX_IGS_ACTIVITY_STATE_INVALID); HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl) @@ -9512,5 +9512,5 @@ #if 0 /* Not quite ready, seem iSegReg assertion trigger once... Do we perhaps need to always read that in longjmp / preempt scenario? */ AssertReturn(pMixedCtx->dx == uIOPort, VERR_HMVMX_IPE_2); - if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo)) + if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)) { rc2 = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient); Index: /trunk/src/VBox/VMM/VMMR3/HM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/HM.cpp (revision 48215) +++ /trunk/src/VBox/VMM/VMMR3/HM.cpp (revision 48216) @@ -896,5 +896,5 @@ { LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError)); - LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl)); + LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl)); switch (pVM->hm.s.lLastError) { @@ -969,5 +969,5 @@ Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported)); - AssertLogRelReturn(pVM->hm.s.vmx.msr.u64FeatureCtrl != 0, VERR_HM_IPE_4); + AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4); uint64_t val; @@ -977,17 +977,17 @@ LogRel(("HM: Using VT-x implementation 2.0!\n")); LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4)); - LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl)); - LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.msr.u64BasicInfo)); - LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo))); - LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo))); - LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None")); - LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo))); - LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo))); - LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo))); + LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl)); + LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo)); + LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo))); + LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo))); + LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None")); + LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo))); + LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))); + LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))); LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops)); - LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxPinCtls.u)); - val = pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1; - zap = pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0; + LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u)); + val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; + zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT); @@ -995,7 +995,7 @@ HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER); - LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls.u)); - val = pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1; - zap = pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0; + LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u)); + val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; + zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING); @@ -1019,9 +1019,9 @@ HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL); - if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) - { - LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls2.u)); - val = pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1; - zap = pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0; + if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) + { + LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u)); + val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; + zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT); @@ -1038,7 +1038,7 @@ } - LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxEntry.u)); - val = pVM->hm.s.vmx.msr.VmxEntry.n.allowed1; - zap = pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0; + LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u)); + val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; + zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST); @@ -1049,7 +1049,7 @@ HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR); - LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxExit.u)); - val = pVM->hm.s.vmx.msr.VmxExit.n.allowed1; - zap = pVM->hm.s.vmx.msr.VmxExit.n.disallowed0; + LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u)); + val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; + zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG); HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE); @@ -1062,7 +1062,7 @@ HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER); - if (pVM->hm.s.vmx.msr.u64EptVpidCaps) - { - val = pVM->hm.s.vmx.msr.u64EptVpidCaps; + if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps) + { + val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps; LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val)); HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY); @@ -1093,5 +1093,5 @@ } - val = pVM->hm.s.vmx.msr.u64Misc; + val = pVM->hm.s.vmx.Msrs.u64Misc; LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val)); if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift) @@ -1113,16 +1113,16 @@ /* Paranoia */ - AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc) >= 512); - - LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed0)); - LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed1)); - LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed0)); - LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed1)); - - val = pVM->hm.s.vmx.msr.u64VmcsEnum; + AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512); + + LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0)); + LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1)); + LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0)); + LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1)); + + val = pVM->hm.s.vmx.Msrs.u64VmcsEnum; LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val)); LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val))); - val = pVM->hm.s.vmx.msr.u64Vmfunc; + val = pVM->hm.s.vmx.Msrs.u64Vmfunc; if (val) { @@ -1139,8 +1139,8 @@ } - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT) pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging; - if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID) + if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID) pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; @@ -1150,5 +1150,5 @@ * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel... */ - if ( !(pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) + if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP)) { @@ -1160,5 +1160,5 @@ if ( pVM->hm.s.vmx.fAllowUnrestricted && pVM->hm.s.fNestedPaging - && (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)) + && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)) { pVM->hm.s.vmx.fUnrestrictedGuest = true; @@ -2563,5 +2563,5 @@ /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */ - mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr0Fixed0; + mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0; /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */ mask &= ~X86_CR0_NE; @@ -2581,10 +2581,10 @@ /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */ - mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr0Fixed1; + mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1; if ((pCtx->cr0 & mask) != 0) return false; /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */ - mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr4Fixed0; + mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0; mask &= ~X86_CR4_VMXE; if ((pCtx->cr4 & mask) != mask) @@ -2592,5 +2592,5 @@ /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */ - mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr4Fixed1; + mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1; if ((pCtx->cr4 & mask) != 0) return false; @@ -2944,6 +2944,6 @@ if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM) { - LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.allowed1)); - LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0)); + LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1)); + LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0)); } } Index: /trunk/src/VBox/VMM/include/HMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/HMInternal.h (revision 48215) +++ /trunk/src/VBox/VMM/include/HMInternal.h (revision 48216) @@ -360,22 +360,5 @@ /** VMX MSR values */ - struct - { - uint64_t u64FeatureCtrl; - uint64_t u64BasicInfo; - VMX_CAPABILITY VmxPinCtls; - VMX_CAPABILITY VmxProcCtls; - VMX_CAPABILITY VmxProcCtls2; - VMX_CAPABILITY VmxExit; - VMX_CAPABILITY VmxEntry; - uint64_t u64Misc; - uint64_t u64Cr0Fixed0; - uint64_t u64Cr0Fixed1; - uint64_t u64Cr4Fixed0; - uint64_t u64Cr4Fixed1; - uint64_t u64VmcsEnum; - uint64_t u64Vmfunc; - uint64_t u64EptVpidCaps; - } msr; + VMXMSRS Msrs; /** Flush types for invept & invvpid; they depend on capabilities. */ Index: /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp =================================================================== --- /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp (revision 48215) +++ /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp (revision 48216) @@ -406,5 +406,5 @@ CHECK_MEMBER_ALIGNMENT(HM, uMaxAsid, 8); CHECK_MEMBER_ALIGNMENT(HM, vmx.u64HostCr4, 8); - CHECK_MEMBER_ALIGNMENT(HM, vmx.msr.u64FeatureCtrl, 8); + CHECK_MEMBER_ALIGNMENT(HM, vmx.Msrs.u64FeatureCtrl, 8); CHECK_MEMBER_ALIGNMENT(HM, StatTprPatchSuccess, 8); CHECK_MEMBER_ALIGNMENT(HMCPU, StatEntry, 8);