Index: /trunk/include/VBox/vmm/hm_vmx.h
===================================================================
--- /trunk/include/VBox/vmm/hm_vmx.h	(revision 48214)
+++ /trunk/include/VBox/vmm/hm_vmx.h	(revision 48215)
@@ -831,16 +831,14 @@
 typedef struct
 {
-    uint32_t    u32IndexMSR;
+    uint32_t    u32Msr;
     uint32_t    u32Reserved;
     uint64_t    u64Value;
-} VMXMSR;
+} VMXAUTOMSR;
 #pragma pack()
 /** Pointer to an MSR load/store element. */
-typedef VMXMSR *PVMXMSR;
+typedef VMXAUTOMSR *PVMXAUTOMSR;
 /** Pointer to a const MSR load/store element. */
-typedef const VMXMSR *PCVMXMSR;
-
-/** @} */
-
+typedef const VMXAUTOMSR *PCVMXAUTOMSR;
+/** @} */
 
 /** @name VMX-capability qword
Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 48214)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 48215)
@@ -2476,7 +2476,7 @@
     int rc = VINF_SUCCESS;
 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    PVMXMSR  pHostMsr           = (PVMXMSR)pVCpu->hm.s.vmx.pvHostMsr;
-    uint32_t cHostMsrs          = 0;
-    uint32_t u32HostExtFeatures = pVM->hm.s.cpuid.u32AMDFeatureEDX;
+    PVMXAUTOMSR  pHostMsr       = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
+    uint32_t     cHostMsrs      = 0;
+    uint32_t     u32HostExtFeatures = pVM->hm.s.cpuid.u32AMDFeatureEDX;
 
     if (u32HostExtFeatures & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
@@ -2506,5 +2506,5 @@
             if ((u64HostEfer & MSR_K6_EFER_SCE) != (u64GuestEfer & MSR_K6_EFER_SCE))
             {
-                pHostMsr->u32IndexMSR = MSR_K6_EFER;
+                pHostMsr->u32Msr      = MSR_K6_EFER;
                 pHostMsr->u32Reserved = 0;
                 pHostMsr->u64Value    = u64HostEfer;
@@ -2514,5 +2514,5 @@
 #  endif
 # else  /* HC_ARCH_BITS != 64 */
-        pHostMsr->u32IndexMSR = MSR_K6_EFER;
+        pHostMsr->u32Msr      = MSR_K6_EFER;
         pHostMsr->u32Reserved = 0;
 # if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
@@ -2532,17 +2532,17 @@
     if (HMVMX_IS_64BIT_HOST_MODE())
     {
-        pHostMsr->u32IndexMSR  = MSR_K6_STAR;
+        pHostMsr->u32Msr       = MSR_K6_STAR;
         pHostMsr->u32Reserved  = 0;
         pHostMsr->u64Value     = ASMRdMsr(MSR_K6_STAR);              /* legacy syscall eip, cs & ss */
         pHostMsr++; cHostMsrs++;
-        pHostMsr->u32IndexMSR  = MSR_K8_LSTAR;
+        pHostMsr->u32Msr       = MSR_K8_LSTAR;
         pHostMsr->u32Reserved  = 0;
         pHostMsr->u64Value     = ASMRdMsr(MSR_K8_LSTAR);             /* 64-bit mode syscall rip */
         pHostMsr++; cHostMsrs++;
-        pHostMsr->u32IndexMSR  = MSR_K8_SF_MASK;
+        pHostMsr->u32Msr       = MSR_K8_SF_MASK;
         pHostMsr->u32Reserved  = 0;
         pHostMsr->u64Value     = ASMRdMsr(MSR_K8_SF_MASK);           /* syscall flag mask */
         pHostMsr++; cHostMsrs++;
-        pHostMsr->u32IndexMSR = MSR_K8_KERNEL_GS_BASE;
+        pHostMsr->u32Msr      = MSR_K8_KERNEL_GS_BASE;
         pHostMsr->u32Reserved = 0;
         pHostMsr->u64Value    = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);     /* swapgs exchange value */
@@ -3935,7 +3935,7 @@
     {
 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-        PVM pVM             = pVCpu->CTX_SUFF(pVM);
-        PVMXMSR  pGuestMsr  = (PVMXMSR)pVCpu->hm.s.vmx.pvGuestMsr;
-        uint32_t cGuestMsrs = 0;
+        PVM         pVM        = pVCpu->CTX_SUFF(pVM);
+        PVMXAUTOMSR pGuestMsr  = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
+        uint32_t    cGuestMsrs = 0;
 
         /* See Intel spec. 4.1.4 "Enumeration of Paging Features by CPUID". */
@@ -3945,17 +3945,17 @@
         if (fSupportsLongMode)
         {
-            pGuestMsr->u32IndexMSR = MSR_K8_LSTAR;
+            pGuestMsr->u32Msr      = MSR_K8_LSTAR;
             pGuestMsr->u32Reserved = 0;
             pGuestMsr->u64Value    = pMixedCtx->msrLSTAR;           /* 64 bits mode syscall rip */
             pGuestMsr++; cGuestMsrs++;
-            pGuestMsr->u32IndexMSR = MSR_K6_STAR;
+            pGuestMsr->u32Msr      = MSR_K6_STAR;
             pGuestMsr->u32Reserved = 0;
             pGuestMsr->u64Value    = pMixedCtx->msrSTAR;            /* legacy syscall eip, cs & ss */
             pGuestMsr++; cGuestMsrs++;
-            pGuestMsr->u32IndexMSR = MSR_K8_SF_MASK;
+            pGuestMsr->u32Msr      = MSR_K8_SF_MASK;
             pGuestMsr->u32Reserved = 0;
             pGuestMsr->u64Value    = pMixedCtx->msrSFMASK;          /* syscall flag mask */
             pGuestMsr++; cGuestMsrs++;
-            pGuestMsr->u32IndexMSR = MSR_K8_KERNEL_GS_BASE;
+            pGuestMsr->u32Msr      = MSR_K8_KERNEL_GS_BASE;
             pGuestMsr->u32Reserved = 0;
             pGuestMsr->u64Value    = pMixedCtx->msrKERNELGSBASE;    /* swapgs exchange value */
@@ -3970,5 +3970,5 @@
             && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP))
         {
-            pGuestMsr->u32IndexMSR = MSR_K8_TSC_AUX;
+            pGuestMsr->u32Msr      = MSR_K8_TSC_AUX;
             pGuestMsr->u32Reserved = 0;
             rc = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pGuestMsr->u64Value);
@@ -5402,7 +5402,7 @@
     for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cGuestMsrs; i++)
     {
-        PVMXMSR pMsr = (PVMXMSR)pVCpu->hm.s.vmx.pvGuestMsr;
+        PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
         pMsr += i;
-        switch (pMsr->u32IndexMSR)
+        switch (pMsr->u32Msr)
         {
             case MSR_K8_LSTAR:          pMixedCtx->msrLSTAR  = pMsr->u64Value;                   break;