Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46868)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46869)
@@ -195,4 +195,6 @@
     /** Whether the TSC offset mode needs to be updated. */
     bool            fUpdateTscOffsetting;
+    /** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
+    bool            fRestoreTscAuxMsr;
 } SVMTRANSIENT, *PSVMTRANSIENT;
 /** @}  */
@@ -2620,4 +2622,5 @@
      * This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
      */
+    pSvmTransient->fRestoreTscAuxMsr = false;
     if (    (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
         && !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
@@ -2627,5 +2630,9 @@
         int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
         AssertRC(rc2);
-        ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
+        if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
+        {
+            ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
+            pSvmTransient->fRestoreTscAuxMsr = true;
+        }
     }
 }
@@ -2684,10 +2691,9 @@
     pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;        /* Mark the VMCB-state cache as unmodified by VMM. */
 
+    if (pSvmTransient->fRestoreTscAuxMsr)
+        ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
+
     if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
     {
-        /* Restore host's TSC_AUX if required. */
-        if (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
-            ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
-
         /** @todo Find a way to fix hardcoding a guestimate.  */
         TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);