Index: /trunk/include/VBox/vmm/hm_svm.h
===================================================================
--- /trunk/include/VBox/vmm/hm_svm.h	(revision 46841)
+++ /trunk/include/VBox/vmm/hm_svm.h	(revision 46842)
@@ -57,6 +57,4 @@
 /** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
 #define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST             RT_BIT(7)
-/** Where did we get this from? */
-#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE           RT_BIT(9)
 /** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
 #define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER              RT_BIT(10)
@@ -64,4 +62,6 @@
  *  intercept filter cycle count threshold. */
 #define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD    RT_BIT(12)
+/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
+#define AMD_CPUID_SVM_FEATURE_EDX_AVIC                      RT_BIT(13)
 /** @} */
 
Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46841)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46842)
@@ -2178,5 +2178,5 @@
     SVMEVENT Event;
     Event.u = 0;
-    if (pVCpu->hm.s.Event.fPending)                            /* First, inject any pending HM events. */
+    if (pVCpu->hm.s.Event.fPending)                                /* First, inject any pending HM events. */
     {
         Event.u = pVCpu->hm.s.Event.u64IntrInfo;
Index: /trunk/src/VBox/VMM/VMMR3/HM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 46841)
+++ /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 46842)
@@ -1398,7 +1398,7 @@
         HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
         HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
-        HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
         HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
         HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
+        HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
 #undef HMSVM_REPORT_FEATURE
     };