Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46783)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46784)
@@ -631,5 +631,4 @@
         /* Set up unconditional intercepts and conditions. */
         pVmcb->ctrl.u32InterceptCtrl1 =   SVM_CTRL1_INTERCEPT_INTR          /* External interrupt causes a VM-exit. */
-                                        | SVM_CTRL1_INTERCEPT_VINTR         /* Interrupt-window VM-exit. */
                                         | SVM_CTRL1_INTERCEPT_NMI           /* Non-Maskable Interrupts causes a VM-exit. */
                                         | SVM_CTRL1_INTERCEPT_SMI           /* System Management Interrupt cause a VM-exit. */
@@ -1994,6 +1993,7 @@
 
     SVMEVENT Event;
-    Event.u         = 0;
-    Event.n.u1Valid = 1;
+    Event.u          = 0;
+    Event.n.u1Valid  = 1;
+    Event.n.u8Vector = uVector;
 
     /* Refer AMD spec. 15.20 "Event Injection" for the format. */
@@ -2689,4 +2689,6 @@
     pSvmTransient->fVectoringPF = false;                        /* Vectoring page-fault needs to be determined later. */
     hmR0SvmSaveGuestState(pVCpu, pMixedCtx);                    /* Save the guest state from the VMCB to the guest-CPU context. */
+
+    Log4(("Vintr Intercept=%RTbool\n", !!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR)));
 
     if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
@@ -3724,5 +3726,8 @@
 
         rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
-        AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
+        if (RT_LIKELY(rc == VINF_SUCCESS))
+            pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        else
+            AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
 
         if (pCtx->ecx == MSR_K6_EFER)
@@ -3734,5 +3739,8 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
         rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
-        AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
+        if (RT_LIKELY(rc == VINF_SUCCESS))
+            pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        else
+            AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
     }