Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 46712)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 46713)
@@ -3315,7 +3315,4 @@
 {
     /* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
-    Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0);
-    Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS);
-
     /* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg()
      * only updates the VMCS bits with the unusable bit and doesn't change the guest-context value. */
@@ -5588,5 +5585,5 @@
     else
         Assert(VMMR0IsLogFlushDisabled(pVCpu));
-    Log4Func(("\n"));
+    Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu));
 
     int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
@@ -7938,5 +7935,7 @@
             && pMixedCtx->ecx <= MSR_IA32_X2APIC_END)
         {
-            Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_APIC_STATE);
+            /* We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
+             * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
+               EMInterpretWrmsr() changes it. */
             pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
         }