Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46670)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 46671)
@@ -4242,5 +4242,5 @@
        DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
     PVM pVM = pVCpu->CTX_SUFF(pVM);
-    rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), pCtx->dr[6]);
+    int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
     if (rc == VINF_EM_RAW_GUEST_TRAP)
     {
@@ -4263,4 +4263,5 @@
         Event.n.u8Vector = X86_XCPT_DB;
         hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
+
         rc = VINF_SUCCESS;
     }