Index: /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp	(revision 45533)
+++ /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp	(revision 45534)
@@ -129,5 +129,5 @@
 {
     AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
-    AssertMsg(pVCpu->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n"));
+    AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_PF, ("Not page-fault trap!\n"));
     return pVCpu->trpm.s.uActiveCR2;
 }
@@ -149,5 +149,4 @@
     return pVCpu->trpm.s.cbInstr;
 }
-
 
 
@@ -264,8 +263,8 @@
     switch (pVCpu->trpm.s.uActiveVector)
     {
-        case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e:
+        case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP: case X86_XCPT_PF:
             AssertMsg(uErrorCode != ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
             break;
-        case 0x11: case 0x08:
+        case X86_XCPT_AC: case X86_XCPT_DF:
             AssertMsg(uErrorCode == 0,            ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
             break;
Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45533)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45534)
@@ -5874,4 +5874,7 @@
     const bool fBlockSti   = (uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
 
+    Assert(!fBlockSti || (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_RFLAGS));
+    Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF);          /* Cannot set block-by-STI when interrupts are disabled. */
+
     int rc = VINF_SUCCESS;
     if (pVCpu->hm.s.Event.fPending)     /* First, inject any pending HM events. */
@@ -5957,5 +5960,5 @@
 
     /*
-     * There's no need to clear the entry-interruption information field here if we're not injecting anything.
+     * There's no need to clear the VM entry-interruption information field here if we're not injecting anything.
      * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
      */
@@ -6273,7 +6276,7 @@
 
     /* Validate. */
-    Assert(VMX_EXIT_INTERRUPTION_INFO_VALID(u32IntrInfo));              /* Bit 31 (Valid bit) must be set by caller. */
-    Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(u32IntrInfo));       /* Bit 12 MBZ. */
-    Assert(!(u32IntrInfo & 0x7ffff000));                                /* Bits 30:12 MBZ. */
+    Assert(VMX_EXIT_INTERRUPTION_INFO_VALID(u32IntrInfo));          /* Bit 31 (Valid bit) must be set by caller. */
+    Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(u32IntrInfo));   /* Bit 12 MBZ. */
+    Assert(!(u32IntrInfo & 0x7ffff000));                            /* Bits 30:12 MBZ. */
 
     /* Inject. */