Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 45502) +++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 45503) @@ -1236,5 +1236,5 @@ if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { - for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) + for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]); } @@ -1322,5 +1322,5 @@ } - pVCpu->hm.s.TlbShootdown.cPages= 0; + pVCpu->hm.s.TlbShootdown.cPages = 0; VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN); } @@ -1402,5 +1402,5 @@ if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { - for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) + for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]); } @@ -4652,5 +4652,5 @@ pVCpu->hm.s.Event.u64IntrInfo = u32IntrInfo; pVCpu->hm.s.Event.u32ErrCode = u32ErrCode; - pVCpu->hm.s.Event.u32InstrLen = cbInstr; + pVCpu->hm.s.Event.cbInstr = cbInstr; } @@ -5816,5 +5816,5 @@ { Log(("Injecting pending event\n")); - int rc = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32InstrLen, + int rc = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.cbInstr, pVCpu->hm.s.Event.u32ErrCode); AssertRCReturn(rc, rc); Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 45502) +++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 45503) @@ -1181,5 +1181,5 @@ /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */ STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown); - for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) + for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pvVMCB->ctrl.TLBCtrl.n.u32ASID); } Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 45502) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 45503) @@ -2610,5 +2610,4 @@ VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN); pVCpu->hm.s.TlbShootdown.cPages = 0; - return; } @@ -2697,5 +2696,5 @@ if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { - for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) + for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]); } @@ -2775,5 +2774,5 @@ } } - pVCpu->hm.s.TlbShootdown.cPages= 0; + pVCpu->hm.s.TlbShootdown.cPages = 0; VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN); @@ -2860,5 +2859,5 @@ if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { - for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) + for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]); } Index: /trunk/src/VBox/VMM/include/HMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/HMInternal.h (revision 45502) +++ /trunk/src/VBox/VMM/include/HMInternal.h (revision 45503) @@ -582,5 +582,5 @@ uint32_t u32Alignment; - /* Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */ + /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */ uint64_t u64HostTscAux; @@ -655,12 +655,12 @@ R0PTRTYPE(void *) pvHostMsr; - /* Number of automatically loaded/restored guest MSRs during the world switch. */ + /** Number of automatically loaded/restored guest MSRs during the world switch. */ uint32_t cGuestMsrs; uint32_t uAlignment; #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ - /* The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */ + /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */ uint64_t u64MsrApicBase; - /* Last use TSC offset value. (cached) */ + /** Last use TSC offset value. (cached) */ uint64_t u64TSCOffset; /** VMCS cache. */ @@ -731,5 +731,6 @@ uint32_t fPending; uint32_t u32ErrCode; - uint32_t u32InstrLen; + uint32_t cbInstr; + uint32_t u32Padding; /**< Explicit alignment padding. */ uint64_t u64IntrInfo; } Event; @@ -749,6 +750,6 @@ struct { - /* Pending IO operation type. */ - HMPENDINGIO enmType; + /** Pending IO operation type. */ + HMPENDINGIO enmType; uint32_t uPadding; RTGCPTR GCPtrRip; @@ -758,7 +759,7 @@ struct { - unsigned uPort; - unsigned uAndVal; - unsigned cbSize; + uint32_t uPort; + uint32_t uAndVal; + uint32_t cbSize; } Port; uint64_t aRaw[2]; @@ -781,5 +782,6 @@ { RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES]; - unsigned cPages; + uint32_t cPages; + uint32_t u32Padding; /**< Explicit alignment padding. */ } TlbShootdown; @@ -788,10 +790,8 @@ DISCPUSTATE DisState; - uint32_t padding2[1]; - STAMPROFILEADV StatEntry; STAMPROFILEADV StatExit1; STAMPROFILEADV StatExit2; -#ifdef VBOX_WITH_OLD_VTX_CODE /* temporary for tracking down darwin issues. */ +#ifdef VBOX_WITH_OLD_VTX_CODE /* "temporary" for tracking down darwin issues. */ STAMPROFILEADV StatExit2Sub1; STAMPROFILEADV StatExit2Sub2; Index: /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp =================================================================== --- /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp (revision 45502) +++ /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp (revision 45503) @@ -403,4 +403,5 @@ CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.HCPhysVmcs, sizeof(RTHCPHYS)); CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.u32PinCtls, 8); + CHECK_MEMBER_ALIGNMENT(HMCPU, DisState, 8); CHECK_MEMBER_ALIGNMENT(HMCPU, Event.u64IntrInfo, 8);