Index: /trunk/include/VBox/vmm/cpum.h =================================================================== --- /trunk/include/VBox/vmm/cpum.h (revision 45484) +++ /trunk/include/VBox/vmm/cpum.h (revision 45485) @@ -491,25 +491,7 @@ -/** - * Get the current privilege level of the guest. - * - * @returns CPL - * @param pVCpu The current virtual CPU. - * @param pRegFrame Pointer to the register frame. - */ VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); - #ifdef VBOX_WITH_RAW_RING1 -/** - * Transforms the guest CPU state to raw-ring mode. - * - * This function will change the any of the cs and ss register with DPL=0 to DPL=1. - * - * @returns VBox status. (recompiler failure) - * @param pVCpu Pointer to the VMCPU. - * @param pCtxCore The context core (for trap usage). - * @see @ref pg_raw - */ -VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore); +VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore); #endif Index: /trunk/include/VBox/vmm/em.h =================================================================== --- /trunk/include/VBox/vmm/em.h (revision 45484) +++ /trunk/include/VBox/vmm/em.h (revision 45485) @@ -122,5 +122,5 @@ * @param pVM The VM to operate on. */ -#define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser) +#define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser) /** @@ -131,5 +131,5 @@ * @param pVM The VM to operate on. */ -#define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor) +#define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor) #ifdef VBOX_WITH_RAW_RING1 @@ -141,7 +141,7 @@ * @param pVM The VM to operate on. */ -#define EMIsRawRing1Enabled(pVM) ((pVM)->fRawRing1Enabled) +# define EMIsRawRing1Enabled(pVM) ((pVM)->fRawRing1Enabled) #else -#define EMIsRawRing1Enabled(pVM) false +# define EMIsRawRing1Enabled(pVM) false #endif @@ -153,5 +153,5 @@ * @param pVM The VM to operate on. */ -#define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser) +#define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser) /** Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 45485) @@ -2666,9 +2666,8 @@ if (pVCpu->cpum.s.fRawEntered) { - if ( EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) - && uCpl == 2) + if ( uCpl == 2 + && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM))) uCpl = 1; - else - if (uCpl == 1) + else if (uCpl == 1) uCpl = 0; } Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 45485) @@ -57,6 +57,7 @@ #ifdef VBOX_WITH_RAW_RING1 -#define EM_EMULATE_SMSW -#endif +# define EM_EMULATE_SMSW +#endif + /******************************************************************************* @@ -3674,6 +3675,6 @@ || pRegFrame->eflags.Bits.u2IOPL > cpl ) +#endif { -#endif if ( cpl != 0 || pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */ @@ -3683,7 +3684,5 @@ return VERR_EM_INTERPRETER; } -#ifdef VBOX_WITH_RAW_RING1 } -#endif } else Index: /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 45485) @@ -23,4 +23,5 @@ #include #include +#include #include #include @@ -33,4 +34,6 @@ #include #include + +#include "SELMInline.h" @@ -838,4 +841,5 @@ } + #ifdef VBOX_WITH_RAW_RING1 /** @@ -853,4 +857,5 @@ } #endif + #ifdef VBOX_WITH_RAW_MODE_NOT_R0 Index: /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp (revision 45485) @@ -625,14 +625,11 @@ if (!fConforming && dpl < cpl) { -#ifdef IN_RC /* Only in GC mode we still see tracing of our ring modifications */ - if ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 +#ifdef IN_RC /* Only in RC we still see tracing of our ring modifications. */ + if ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM) pTrapStack[--idx] = pRegFrame->ss.Sel & ~1; /* Mask away traces of raw ring 0 execution (ring 1). */ -# ifdef VBOX_WITH_RAW_RING1 - else - if ( EMIsRawRing1Enabled(pVM) - && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2) + else if ( EMIsRawRing1Enabled(pVM) + && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2) pTrapStack[--idx] = (pRegFrame->ss.Sel & ~2) | 1; /* Mask away traces of raw ring 1 execution (ring 2). */ -# endif else #endif /* IN_RC */ @@ -645,14 +642,12 @@ /* Note: Not really necessary as we grab include those bits in the trap/irq handler trampoline */ pTrapStack[--idx] = eflags.u32; -#ifdef IN_RC /* Only in GC mode we still see tracing of our ring modifications */ - if ( (pRegFrame->cs.Sel & X86_SEL_RPL) == 1 + +#ifdef IN_RC /* Only in RC mode we still see tracing of our ring modifications */ + if ( (pRegFrame->cs.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM) pTrapStack[--idx] = pRegFrame->cs.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */ -# ifdef VBOX_WITH_RAW_RING1 - else - if ( EMIsRawRing1Enabled(pVM) - && (pRegFrame->cs.Sel & X86_SEL_RPL) == 2) + else if ( EMIsRawRing1Enabled(pVM) + && (pRegFrame->cs.Sel & X86_SEL_RPL) == 2) pTrapStack[--idx] = (pRegFrame->cs.Sel & ~2) | 1; /* Mask away traces of raw ring 1 execution (ring 2). */ -# endif else #endif /* IN_RC */ Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 45485) @@ -4193,5 +4193,5 @@ * Are we in Ring-0? */ - if ( pCtxCore->ss.Sel + if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0 && !pCtxCore->eflags.Bits.u1VM) @@ -4206,5 +4206,5 @@ */ pCtxCore->ss.Sel |= 1; - if ( pCtxCore->cs.Sel + if ( pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0) pCtxCore->cs.Sel |= 1; @@ -4236,5 +4236,5 @@ */ AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n")); - AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0, + AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0, ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL)); Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP)); @@ -4245,5 +4245,4 @@ return VINF_SUCCESS; } - Index: /trunk/src/VBox/VMM/VMMR3/CSAM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 45485) @@ -849,8 +849,6 @@ /* removing breaks win2k guests? */ case OP_IRET: -#ifdef VBOX_WITH_RAW_RING1 if (EMIsRawRing1Enabled(pVM)) break; -#endif /* no break */ Index: /trunk/src/VBox/VMM/VMMR3/EM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/EM.cpp (revision 45485) @@ -1320,8 +1320,7 @@ return EMSTATE_REM; -# ifdef VBOX_WITH_RAW_RING1 - /* Only ring 0 and 1 supervisor code. */ if (EMIsRawRing1Enabled(pVM)) { + /* Only ring 0 and 1 supervisor code. */ if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */ { @@ -1330,8 +1329,6 @@ } } - else -# endif /* Only ring 0 supervisor code. */ - if ((uSS & X86_SEL_RPL) != 0) + else if ((uSS & X86_SEL_RPL) != 0) { Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL)); Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 45485) @@ -1362,9 +1362,6 @@ Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ); # endif -# ifdef VBOX_WITH_RAW_RING1 - Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) == 3 || (pCtx->ss.Sel & X86_SEL_RPL) == 0 || (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1)); -# else - Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) == 3 || (pCtx->ss.Sel & X86_SEL_RPL) == 0); -# endif + Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) == 3 || (pCtx->ss.Sel & X86_SEL_RPL) == 0 + || (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1)); AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF) || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip), @@ -1446,4 +1443,5 @@ + /* * Execute the code. @@ -1551,5 +1549,5 @@ || VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) { - Assert(pCtx->eflags.Bits.u1VM || (EMIsRawRing1Enabled(pVM) ? ((pCtx->ss.Sel & X86_SEL_RPL) != 2) : ((pCtx->ss.Sel & X86_SEL_RPL) != 1))); + Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2 : 1)); STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a); Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 45485) @@ -1535,5 +1535,5 @@ break; -#ifdef VBOX_WITH_SAFE_STR /* @todo remove DISOPTYPE_PRIVILEGED_NOTRAP from disasm table */ +#ifdef VBOX_WITH_SAFE_STR /** @todo remove DISOPTYPE_PRIVILEGED_NOTRAP from disasm table */ case OP_STR: break; @@ -1651,5 +1651,5 @@ return VINF_SUCCESS; -#ifdef VBOX_WITH_SAFE_STR /* @todo remove DISOPTYPE_PRIVILEGED_NOTRAP from disasm table */ +#ifdef VBOX_WITH_SAFE_STR /** @todo remove DISOPTYPE_PRIVILEGED_NOTRAP from disasm table */ case OP_STR: break; Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 45485) @@ -439,11 +439,7 @@ callInfo.pCurInstrGC = pCurInstrGC; -#ifdef VBOX_WITH_RAW_RING1 if (EMIsRawRing1Enabled(pVM)) - { size = patmPatchGenCode(pVM, pPatch, pPB, &PATMIretRing1Record, 0, false, &callInfo); - } else -#endif size = patmPatchGenCode(pVM, pPatch, pPB, &PATMIretRecord, 0, false, &callInfo); @@ -1083,8 +1079,8 @@ int rc = VINF_SUCCESS; -#ifdef VBOX_WITH_RAW_RING1 - if (!EMIsRawRing1Enabled(pVM)) /* direct passthru of interrupts is not allowed in the ring-1 support case as we can't deal with the ring-1/2 ambiguity in the patm asm code and we don't need it either as TRPMForwardTrap takes care of the details. */ - { -#endif + if (!EMIsRawRing1Enabled(pVM)) /* direct passthru of interrupts is not allowed in the ring-1 support case as we can't + deal with the ring-1/2 ambiguity in the patm asm code and we don't need it either as + TRPMForwardTrap takes care of the details. */ + { uint32_t size; PATCHGEN_PROLOG(pVM, pPatch); @@ -1099,7 +1095,5 @@ PATCHGEN_EPILOG(pPatch, size); -#ifdef VBOX_WITH_RAW_RING1 - } -#endif + } // Interrupt gates set IF to 0 Index: /trunk/src/VBox/VMM/VMMR3/SELM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/SELM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/SELM.cpp (revision 45485) @@ -63,4 +63,5 @@ #include #include +#include #include #include @@ -80,4 +81,5 @@ #include +#include "SELMInline.h" @@ -957,5 +959,5 @@ #ifdef VBOX_WITH_SAFE_STR - /** Use the guest's TR selector to plug the str virtualization hole. */ + /* Use the guest's TR selector to plug the str virtualization hole. */ if (CPUMGetGuestTR(pVCpu, NULL) != 0) { @@ -1029,4 +1031,5 @@ { Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt)); + #ifdef SELM_TRACK_GUEST_GDT_CHANGES /* @@ -1044,7 +1047,9 @@ "Guest GDT write access handler"); # ifdef VBOX_WITH_RAW_RING1 - /* Some guest OSes (QNX) share code and the GDT on the same page; PGMR3HandlerVirtualRegister doesn't support more than one handler, so we kick out the - * PATM handler as this one is more important. - * @todo fix this properly in PGMR3HandlerVirtualRegister + /** @todo !HACK ALERT! + * Some guest OSes (QNX) share code and the GDT on the same page; + * PGMR3HandlerVirtualRegister doesn't support more than one handler, + * so we kick out the PATM handler as this one is more important. + * Fix this properly in PGMR3HandlerVirtualRegister? */ if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT) @@ -1062,5 +1067,6 @@ if (RT_FAILURE(rc)) return rc; -#endif +#endif /* SELM_TRACK_GUEST_GDT_CHANGES */ + /* Update saved Guest GDTR. */ pVM->selm.s.GuestGdtr = GDTR; @@ -1243,5 +1249,5 @@ /** @todo investigate how intel handle various operations on half present cross page entries. */ off = GCPtrLdt & (sizeof(X86DESC) - 1); -//// AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt)); + AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt)); /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */ @@ -1473,6 +1479,7 @@ STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a); return rcStrict; -#endif -} +#endif /* VBOX_WITH_RAW_MODE */ +} + #ifdef SELM_TRACK_GUEST_GDT_CHANGES @@ -1568,4 +1575,5 @@ } #endif + /** @@ -1719,10 +1727,10 @@ #ifdef VBOX_WITH_RAW_RING1 /* Update our TSS structure for the guest's ring 2 stack */ - selmSetRing2Stack(pVM, (Tss.ss1 & ~1) | 2, Tss.esp1); - - if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) | 1)) - || pVM->selm.s.Tss.esp2 != Tss.esp1) + if (EMIsRawRing1Enabled(pVM)) { - Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) | 1, pVM->selm.s.Tss.esp2)); + if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) | 1)) + || pVM->selm.s.Tss.esp2 != Tss.esp1) + Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) | 1, pVM->selm.s.Tss.esp2)); + selmSetRing2Stack(pVM, (Tss.ss1 & ~1) | 2, Tss.esp1); } #endif @@ -1770,7 +1778,9 @@ { # ifdef VBOX_WITH_RAW_RING1 - /* Some guest OSes (QNX) share code and the TSS on the same page; PGMR3HandlerVirtualRegister doesn't support more than one handler, so we kick out the - * PATM handler as this one is more important. - * @todo fix this properly in PGMR3HandlerVirtualRegister + /** @todo !HACK ALERT! + * Some guest OSes (QNX) share code and the TSS on the same page; + * PGMR3HandlerVirtualRegister doesn't support more than one + * handler, so we kick out the PATM handler as this one is more + * important. Fix this properly in PGMR3HandlerVirtualRegister? */ if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT) @@ -1794,5 +1804,6 @@ # endif } -#endif +#endif /* SELM_TRACK_GUEST_TSS_CHANGES */ + /* Update saved Guest TSS info. */ pVM->selm.s.GCPtrGuestTss = GCPtrTss; @@ -2095,7 +2106,8 @@ } + # ifdef VBOX_WITH_SAFE_STR /** - * Validates the RawR0 TR shadow GDT entry + * Validates the RawR0 TR shadow GDT entry. * * @returns true if it matches. @@ -2135,5 +2147,5 @@ return true; } -# endif +# endif /* VBOX_WITH_SAFE_STR */ #endif /* VBOX_WITH_RAW_MODE */ Index: /trunk/src/VBox/VMM/VMMR3/TRPM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/TRPM.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMR3/TRPM.cpp (revision 45485) @@ -1331,8 +1331,5 @@ if ( EMIsRawRing0Enabled(pVM) -#ifdef VBOX_WITH_RAW_RING1 - && !EMIsRawRing1Enabled(pVM) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */ -#endif - ) + && !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */ { /* Index: /trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp (revision 45485) @@ -115,4 +115,7 @@ * @param pVCpu The current virtual CPU. * @param pRegFrame Pointer to the register frame. + * + * @todo r=bird: This is very similar to CPUMGetGuestCPL and I cannot quite + * see why this variant of the code is necessary. */ VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) @@ -142,9 +145,8 @@ if (pVCpu->cpum.s.fRawEntered) { - if ( EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) - && uCpl == 2) + if ( uCpl == 2 + && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) ) uCpl = 1; - else - if (uCpl == 1) + else if (uCpl == 1) uCpl = 0; } @@ -162,4 +164,5 @@ } + #ifdef VBOX_WITH_RAW_RING1 /** @@ -168,8 +171,11 @@ * This function will change the any of the cs and ss register with DPL=0 to DPL=1. * - * @returns VBox status. (recompiler failure) + * Used by emInterpretIret() after the new state has been loaded. + * * @param pVCpu Pointer to the VMCPU. * @param pCtxCore The context core (for trap usage). * @see @ref pg_raw + * @remarks Will be probably obsoleted by #5653 (it will leave and reenter raw + * mode instead, I think). */ VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore) @@ -213,2 +219,3 @@ } #endif /* VBOX_WITH_RAW_RING1 */ + Index: /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp (revision 45485) @@ -155,9 +155,6 @@ /* Very important check -> otherwise we have a security leak. */ -#ifdef VBOX_WITH_RAW_RING1 - AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) <= (unsigned) (EMIsRawRing1Enabled(pVM) ? 2 : 1), VERR_ACCESS_DENIED); -#else - AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED); -#endif + AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) <= (EMIsRawRing1Enabled(pVM) ? 2U : 1U), + VERR_ACCESS_DENIED); Assert(PATMIsPatchGCAddr(pVM, pRegFrame->eip)); @@ -459,9 +456,7 @@ int rc; -#ifdef VBOX_WITH_RAW_RING1 - AssertReturn(!pRegFrame->eflags.Bits.u1VM && ((pRegFrame->ss.Sel & X86_SEL_RPL) == 1 || (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2)), VERR_ACCESS_DENIED); -#else - AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED); -#endif + AssertReturn(!pRegFrame->eflags.Bits.u1VM + && ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 + || (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2)), VERR_ACCESS_DENIED); /* Int 3 in PATM generated code? (most common case) */ Index: /trunk/src/VBox/VMM/VMMRC/SELMRC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/SELMRC.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMRC/SELMRC.cpp (revision 45485) @@ -35,4 +35,6 @@ #include +#include "SELMInline.h" + /******************************************************************************* @@ -43,4 +45,5 @@ static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" }; #endif + #ifdef SELM_TRACK_GUEST_GDT_CHANGES @@ -308,4 +311,5 @@ #endif /* SELM_TRACK_GUEST_GDT_CHANGES */ + #ifdef SELM_TRACK_GUEST_LDT_CHANGES /** @@ -332,4 +336,5 @@ } #endif + #ifdef SELM_TRACK_GUEST_TSS_CHANGES @@ -407,11 +412,10 @@ } #ifdef VBOX_WITH_RAW_RING1 - else - if ( EMIsRawRing1Enabled(pVM) - && PAGE_ADDRESS(&pGuestTss->esp1) == PAGE_ADDRESS(&pGuestTss->padding_ss1) - && PAGE_ADDRESS(&pGuestTss->esp1) == PAGE_ADDRESS((uint8_t *)pGuestTss + offRange) - && ( pGuestTss->esp1 != pVM->selm.s.Tss.esp2 - || pGuestTss->ss1 != ((pVM->selm.s.Tss.ss2 & ~2) | 1)) /* undo raw-r1 */ - ) + else if ( EMIsRawRing1Enabled(pVM) + && PAGE_ADDRESS(&pGuestTss->esp1) == PAGE_ADDRESS(&pGuestTss->padding_ss1) + && PAGE_ADDRESS(&pGuestTss->esp1) == PAGE_ADDRESS((uint8_t *)pGuestTss + offRange) + && ( pGuestTss->esp1 != pVM->selm.s.Tss.esp2 + || pGuestTss->ss1 != ((pVM->selm.s.Tss.ss2 & ~2) | 1)) /* undo raw-r1 */ + ) { Log(("selmRCGuestTSSWriteHandler: R1 stack: %RTsel:%RGv -> %RTsel:%RGv\n", @@ -513,4 +517,5 @@ #endif /* SELM_TRACK_GUEST_TSS_CHANGES */ + #ifdef SELM_TRACK_SHADOW_GDT_CHANGES /** @@ -534,4 +539,5 @@ #endif + #ifdef SELM_TRACK_SHADOW_LDT_CHANGES /** @@ -556,4 +562,5 @@ #endif + #ifdef SELM_TRACK_SHADOW_TSS_CHANGES /** Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 45484) +++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 45485) @@ -304,5 +304,5 @@ PVM pVM = TRPMCPU_2_VM(pTrpmCpu); PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); - //LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu))); + LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(1); @@ -445,11 +445,7 @@ * PATM is using INT3s, let them have a go first. */ -#ifdef VBOX_WITH_RAW_RING1 - if ( ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 - || (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2)) -#else - if ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 -#endif - && !pRegFrame->eflags.Bits.u1VM) + if ( ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1 + || (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2) ) + && !pRegFrame->eflags.Bits.u1VM) { rc = PATMRCHandleInt3PatchTrap(pVM, pRegFrame); @@ -528,9 +524,5 @@ PGMRZDynMapStartAutoSet(pVCpu); -#ifdef VBOX_WITH_RAW_RING1 - if (CPUMGetGuestCPL(pVCpu) <= (unsigned)(EMIsRawRing1Enabled(pVM) ? 1 : 0)) -#else - if (CPUMGetGuestCPL(pVCpu) == 0) -#endif + if (CPUMGetGuestCPL(pVCpu) <= (EMIsRawRing1Enabled(pVM) ? 1U : 0U)) { /* Index: /trunk/src/VBox/VMM/include/SELMInline.h =================================================================== --- /trunk/src/VBox/VMM/include/SELMInline.h (revision 45485) +++ /trunk/src/VBox/VMM/include/SELMInline.h (revision 45485) @@ -0,0 +1,314 @@ +/* $Id$ */ +/** @file + * SELM - Internal header file. + */ + +/* + * Copyright (C) 2006-2012 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + +#ifndef ___SELMInline_h +#define ___SELMInline_h + +#ifdef VBOX_WITH_RAW_MODE_NOT_R0 + +/** + * Checks if a shadow descriptor table entry is good for the given segment + * register. + * + * @returns @c true if good, @c false if not. + * @param pSReg The segment register. + * @param pShwDesc The shadow descriptor table entry. + * @param iSReg The segment register index (X86_SREG_XXX). + * @param uCpl The CPL. + */ +DECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl) +{ + /* + * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals. + */ + + if (!pShwDesc->Gen.u1Present) + { + Log(("selmIsShwDescGoodForSReg: Not present\n")); + return false; + } + + if (!pShwDesc->Gen.u1DescType) + { + Log(("selmIsShwDescGoodForSReg: System descriptor\n")); + return false; + } + + if (iSReg == X86_SREG_SS) + { + if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE) + { + Log(("selmIsShwDescGoodForSReg: Stack must be writable\n")); + return false; + } + if (uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available) + { + Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)); + return false; + } + } + else + { + if (iSReg == X86_SREG_CS) + { + if (!(pShwDesc->Gen.u4Type & X86_SEL_TYPE_CODE)) + { + Log(("selmIsShwDescGoodForSReg: CS needs code segment\n")); + return false; + } + } + else if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE) + { + Log(("selmIsShwDescGoodForSReg: iSReg=%u execute only\n", iSReg)); + return false; + } + + if ( (pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) + != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) + && ( ( (pSReg->Sel & X86_SEL_RPL) > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available + && (pSReg->Sel & X86_SEL_RPL) != pShwDesc->Gen.u1Available ) + || uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available ) ) + { + Log(("selmIsShwDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u\n", iSReg, + pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available, uCpl, pSReg->Sel & X86_SEL_RPL)); + return false; + } + } + + return true; +} + + +/** + * Checks if a guest descriptor table entry is good for the given segment + * register. + * + * @returns @c true if good, @c false if not. + * @param pVCpu The current virtual CPU. + * @param pSReg The segment register. + * @param pGstDesc The guest descriptor table entry. + * @param iSReg The segment register index (X86_SREG_XXX). + * @param uCpl The CPL. + */ +DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl) +{ + /* + * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals. + */ + + if (!pGstDesc->Gen.u1Present) + { + Log(("selmIsGstDescGoodForSReg: Not present\n")); + return false; + } + + if (!pGstDesc->Gen.u1DescType) + { + Log(("selmIsGstDescGoodForSReg: System descriptor\n")); + return false; + } + + if (iSReg == X86_SREG_SS) + { + if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE) + { + Log(("selmIsGstDescGoodForSReg: Stack must be writable\n")); + return false; + } + if (uCpl > pGstDesc->Gen.u2Dpl) + { + Log(("selmIsGstDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pGstDesc->Gen.u2Dpl)); + return false; + } + } + else + { + if (iSReg == X86_SREG_CS) + { + if (!(pGstDesc->Gen.u4Type & X86_SEL_TYPE_CODE)) + { + Log(("selmIsGstDescGoodForSReg: CS needs code segment\n")); + return false; + } + } + else if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE) + { + Log(("selmIsGstDescGoodForSReg: iSReg=%u execute only\n", iSReg)); + return false; + } + + if ( (pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) + != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) + && ( ( (pSReg->Sel & X86_SEL_RPL) > pGstDesc->Gen.u2Dpl + && ( (pSReg->Sel & X86_SEL_RPL) != 1 + || !CPUMIsGuestInRawMode(pVCpu) ) ) + || uCpl > (unsigned)pGstDesc->Gen.u2Dpl + ) + ) + { + Log(("selmIsGstDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u InRawMode=%u\n", iSReg, + pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu))); + return false; + } + } + + return true; +} + + +/** + * Converts a guest GDT or LDT entry to a shadow table entry. + * + * @param pVM The VM handle. + * @param pDesc Guest entry on input, shadow entry on return. + */ +DECL_FORCE_INLINE(void) selmGuestToShadowDesc(PVM pVM, PX86DESC pDesc) +{ + /* + * Code and data selectors are generally 1:1, with the + * 'little' adjustment we do for DPL 0 selectors. + */ + if (pDesc->Gen.u1DescType) + { + /* + * Hack for A-bit against Trap E on read-only GDT. + */ + /** @todo Fix this by loading ds and cs before turning off WP. */ + pDesc->Gen.u4Type |= X86_SEL_TYPE_ACCESSED; + + /* + * All DPL 0 code and data segments are squeezed into DPL 1. + * + * We're skipping conforming segments here because those + * cannot give us any trouble. + */ + if ( pDesc->Gen.u2Dpl == 0 + && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) + != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) ) + { + pDesc->Gen.u2Dpl = 1; + pDesc->Gen.u1Available = 1; + } +# ifdef VBOX_WITH_RAW_RING1 + else if ( pDesc->Gen.u2Dpl == 1 + && EMIsRawRing1Enabled(pVM) + && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) + != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) ) + { + pDesc->Gen.u2Dpl = 2; + pDesc->Gen.u1Available = 1; + } +# endif + else + pDesc->Gen.u1Available = 0; + } + else + { + /* + * System type selectors are marked not present. + * Recompiler or special handling is required for these. + */ + /** @todo what about interrupt gates and rawr0? */ + pDesc->Gen.u1Present = 0; + } +} + + +/** + * Checks if a segment register is stale given the shadow descriptor table + * entry. + * + * @returns @c true if stale, @c false if not. + * @param pSReg The segment register. + * @param pShwDesc The shadow descriptor entry. + * @param iSReg The segment register number (X86_SREG_XXX). + */ +DECLINLINE(bool) selmIsSRegStale32(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg) +{ + if ( pSReg->Attr.n.u1Present != pShwDesc->Gen.u1Present + || pSReg->Attr.n.u4Type != pShwDesc->Gen.u4Type + || pSReg->Attr.n.u1DescType != pShwDesc->Gen.u1DescType + || pSReg->Attr.n.u1DefBig != pShwDesc->Gen.u1DefBig + || pSReg->Attr.n.u1Granularity != pShwDesc->Gen.u1Granularity + || pSReg->Attr.n.u2Dpl != pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available) + { + Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc))); + return true; + } + + if (pSReg->u64Base != X86DESC_BASE(pShwDesc)) + { + Log(("selmIsSRegStale32: base changed (%#llx -> %#llx)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc))); + return true; + } + + if (pSReg->u32Limit != X86DESC_LIMIT_G(pShwDesc)) + { + Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc))); + return true; + } + + return false; +} + + +/** + * Loads the hidden bits of a selector register from a shadow descriptor table + * entry. + * + * @param pSReg The segment register in question. + * @param pShwDesc The shadow descriptor table entry. + */ +DECLINLINE(void) selmLoadHiddenSRegFromShadowDesc(PCPUMSELREG pSReg, PCX86DESC pShwDesc) +{ + pSReg->Attr.u = X86DESC_GET_HID_ATTR(pShwDesc); + pSReg->Attr.n.u2Dpl -= pSReg->Attr.n.u1Available; + Assert(pSReg->Attr.n.u4Type & X86_SEL_TYPE_ACCESSED); + pSReg->u32Limit = X86DESC_LIMIT_G(pShwDesc); + pSReg->u64Base = X86DESC_BASE(pShwDesc); + pSReg->ValidSel = pSReg->Sel; + if (pSReg->Attr.n.u1Available) + pSReg->ValidSel &= ~(RTSEL)1; + pSReg->fFlags = CPUMSELREG_FLAGS_VALID; +} + + +/** + * Loads the hidden bits of a selector register from a guest descriptor table + * entry. + * + * @param pVCpu The current virtual CPU. + * @param pSReg The segment register in question. + * @param pGstDesc The guest descriptor table entry. + */ +DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc) +{ + pSReg->Attr.u = X86DESC_GET_HID_ATTR(pGstDesc); + pSReg->Attr.n.u4Type |= X86_SEL_TYPE_ACCESSED; + pSReg->u32Limit = X86DESC_LIMIT_G(pGstDesc); + pSReg->u64Base = X86DESC_BASE(pGstDesc); + pSReg->ValidSel = pSReg->Sel; + if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu)) + pSReg->ValidSel &= ~(RTSEL)1; + pSReg->fFlags = CPUMSELREG_FLAGS_VALID; +} + +#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */ + +/** @} */ + +#endif Index: /trunk/src/VBox/VMM/include/SELMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/SELMInternal.h (revision 45484) +++ /trunk/src/VBox/VMM/include/SELMInternal.h (revision 45485) @@ -25,5 +25,4 @@ #include #include -#include @@ -229,297 +228,4 @@ RT_C_DECLS_END - -#ifdef VBOX_WITH_RAW_MODE_NOT_R0 - -/** - * Checks if a shadow descriptor table entry is good for the given segment - * register. - * - * @returns @c true if good, @c false if not. - * @param pSReg The segment register. - * @param pShwDesc The shadow descriptor table entry. - * @param iSReg The segment register index (X86_SREG_XXX). - * @param uCpl The CPL. - */ -DECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl) -{ - /* - * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals. - */ - - if (!pShwDesc->Gen.u1Present) - { - Log(("selmIsShwDescGoodForSReg: Not present\n")); - return false; - } - - if (!pShwDesc->Gen.u1DescType) - { - Log(("selmIsShwDescGoodForSReg: System descriptor\n")); - return false; - } - - if (iSReg == X86_SREG_SS) - { - if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE) - { - Log(("selmIsShwDescGoodForSReg: Stack must be writable\n")); - return false; - } - if (uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available) - { - Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)); - return false; - } - } - else - { - if (iSReg == X86_SREG_CS) - { - if (!(pShwDesc->Gen.u4Type & X86_SEL_TYPE_CODE)) - { - Log(("selmIsShwDescGoodForSReg: CS needs code segment\n")); - return false; - } - } - else if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE) - { - Log(("selmIsShwDescGoodForSReg: iSReg=%u execute only\n", iSReg)); - return false; - } - - if ( (pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) - != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) - && ( ( (pSReg->Sel & X86_SEL_RPL) > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available - && (pSReg->Sel & X86_SEL_RPL) != pShwDesc->Gen.u1Available ) - || uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available ) ) - { - Log(("selmIsShwDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u\n", iSReg, - pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available, uCpl, pSReg->Sel & X86_SEL_RPL)); - return false; - } - } - - return true; -} - - -/** - * Checks if a guest descriptor table entry is good for the given segment - * register. - * - * @returns @c true if good, @c false if not. - * @param pVCpu The current virtual CPU. - * @param pSReg The segment register. - * @param pGstDesc The guest descriptor table entry. - * @param iSReg The segment register index (X86_SREG_XXX). - * @param uCpl The CPL. - */ -DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl) -{ - /* - * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals. - */ - - if (!pGstDesc->Gen.u1Present) - { - Log(("selmIsGstDescGoodForSReg: Not present\n")); - return false; - } - - if (!pGstDesc->Gen.u1DescType) - { - Log(("selmIsGstDescGoodForSReg: System descriptor\n")); - return false; - } - - if (iSReg == X86_SREG_SS) - { - if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE) - { - Log(("selmIsGstDescGoodForSReg: Stack must be writable\n")); - return false; - } - if (uCpl > pGstDesc->Gen.u2Dpl) - { - Log(("selmIsGstDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pGstDesc->Gen.u2Dpl)); - return false; - } - } - else - { - if (iSReg == X86_SREG_CS) - { - if (!(pGstDesc->Gen.u4Type & X86_SEL_TYPE_CODE)) - { - Log(("selmIsGstDescGoodForSReg: CS needs code segment\n")); - return false; - } - } - else if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE) - { - Log(("selmIsGstDescGoodForSReg: iSReg=%u execute only\n", iSReg)); - return false; - } - - if ( (pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) - != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) - && ( ( (pSReg->Sel & X86_SEL_RPL) > pGstDesc->Gen.u2Dpl - && ( (pSReg->Sel & X86_SEL_RPL) != 1 - || !CPUMIsGuestInRawMode(pVCpu) ) ) - || uCpl > (unsigned)pGstDesc->Gen.u2Dpl - ) - ) - { - Log(("selmIsGstDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u InRawMode=%u\n", iSReg, - pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu))); - return false; - } - } - - return true; -} - - -/** - * Converts a guest GDT or LDT entry to a shadow table entry. - * - * @param pVM The VM handle. - * @param pDesc Guest entry on input, shadow entry on return. - */ -DECL_FORCE_INLINE(void) selmGuestToShadowDesc(PVM pVM, PX86DESC pDesc) -{ - /* - * Code and data selectors are generally 1:1, with the - * 'little' adjustment we do for DPL 0 selectors. - */ - if (pDesc->Gen.u1DescType) - { - /* - * Hack for A-bit against Trap E on read-only GDT. - */ - /** @todo Fix this by loading ds and cs before turning off WP. */ - pDesc->Gen.u4Type |= X86_SEL_TYPE_ACCESSED; - - /* - * All DPL 0 code and data segments are squeezed into DPL 1. - * - * We're skipping conforming segments here because those - * cannot give us any trouble. - */ - if ( pDesc->Gen.u2Dpl == 0 - && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) - != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) ) - { - pDesc->Gen.u2Dpl = 1; - pDesc->Gen.u1Available = 1; - } -# ifdef VBOX_WITH_RAW_RING1 - else - if ( pDesc->Gen.u2Dpl == 1 -// && EMIsRawRing1Enabled(pVM) - && (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) - != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) ) - { - pDesc->Gen.u2Dpl = 2; - pDesc->Gen.u1Available = 1; - } -# endif - else - pDesc->Gen.u1Available = 0; - } - else - { - /* - * System type selectors are marked not present. - * Recompiler or special handling is required for these. - */ - /** @todo what about interrupt gates and rawr0? */ - pDesc->Gen.u1Present = 0; - } -} - - -/** - * Checks if a segment register is stale given the shadow descriptor table - * entry. - * - * @returns @c true if stale, @c false if not. - * @param pSReg The segment register. - * @param pShwDesc The shadow descriptor entry. - * @param iSReg The segment register number (X86_SREG_XXX). - */ -DECLINLINE(bool) selmIsSRegStale32(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg) -{ - if ( pSReg->Attr.n.u1Present != pShwDesc->Gen.u1Present - || pSReg->Attr.n.u4Type != pShwDesc->Gen.u4Type - || pSReg->Attr.n.u1DescType != pShwDesc->Gen.u1DescType - || pSReg->Attr.n.u1DefBig != pShwDesc->Gen.u1DefBig - || pSReg->Attr.n.u1Granularity != pShwDesc->Gen.u1Granularity - || pSReg->Attr.n.u2Dpl != pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available) - { - Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc))); - return true; - } - - if (pSReg->u64Base != X86DESC_BASE(pShwDesc)) - { - Log(("selmIsSRegStale32: base changed (%#llx -> %#llx)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc))); - return true; - } - - if (pSReg->u32Limit != X86DESC_LIMIT_G(pShwDesc)) - { - Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc))); - return true; - } - - return false; -} - - -/** - * Loads the hidden bits of a selector register from a shadow descriptor table - * entry. - * - * @param pSReg The segment register in question. - * @param pShwDesc The shadow descriptor table entry. - */ -DECLINLINE(void) selmLoadHiddenSRegFromShadowDesc(PCPUMSELREG pSReg, PCX86DESC pShwDesc) -{ - pSReg->Attr.u = X86DESC_GET_HID_ATTR(pShwDesc); - pSReg->Attr.n.u2Dpl -= pSReg->Attr.n.u1Available; - Assert(pSReg->Attr.n.u4Type & X86_SEL_TYPE_ACCESSED); - pSReg->u32Limit = X86DESC_LIMIT_G(pShwDesc); - pSReg->u64Base = X86DESC_BASE(pShwDesc); - pSReg->ValidSel = pSReg->Sel; - if (pSReg->Attr.n.u1Available) - pSReg->ValidSel &= ~(RTSEL)1; - pSReg->fFlags = CPUMSELREG_FLAGS_VALID; -} - - -/** - * Loads the hidden bits of a selector register from a guest descriptor table - * entry. - * - * @param pVCpu The current virtual CPU. - * @param pSReg The segment register in question. - * @param pGstDesc The guest descriptor table entry. - */ -DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc) -{ - pSReg->Attr.u = X86DESC_GET_HID_ATTR(pGstDesc); - pSReg->Attr.n.u4Type |= X86_SEL_TYPE_ACCESSED; - pSReg->u32Limit = X86DESC_LIMIT_G(pGstDesc); - pSReg->u64Base = X86DESC_BASE(pGstDesc); - pSReg->ValidSel = pSReg->Sel; - if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu)) - pSReg->ValidSel &= ~(RTSEL)1; - pSReg->fFlags = CPUMSELREG_FLAGS_VALID; -} - -#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */ - /** @} */ Index: /trunk/src/recompiler/VBoxRecompiler.c =================================================================== --- /trunk/src/recompiler/VBoxRecompiler.c (revision 45484) +++ /trunk/src/recompiler/VBoxRecompiler.c (revision 45485) @@ -1633,9 +1633,8 @@ } -# ifdef VBOX_WITH_RAW_RING1 - /* Only ring 0 and 1 supervisor code. */ if (EMIsRawRing1Enabled(env->pVM)) { - if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */ + /* Only ring 0 and 1 supervisor code. */ + if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */ { Log2(("raw r0 mode refused: CPL %d\n", (fFlags >> HF_CPL_SHIFT) & 3)); @@ -1643,8 +1642,6 @@ } } - else -# endif - // Only R0 - if (((fFlags >> HF_CPL_SHIFT) & 3) != 0) + /* Only R0. */ + else if (((fFlags >> HF_CPL_SHIFT) & 3) != 0) { STAM_COUNTER_INC(&gStatRefuseRing1or2); Index: /trunk/src/recompiler/target-i386/op_helper.c =================================================================== --- /trunk/src/recompiler/target-i386/op_helper.c (revision 45484) +++ /trunk/src/recompiler/target-i386/op_helper.c (revision 45485) @@ -232,6 +232,6 @@ #ifdef VBOX /* Trying to load a selector with CPL=1? */ - /* @todo this is a hack to correct the incorrect checking order for pending interrupts in the patm iret replacement code (corrected in the ring-1 version) */ - /* @todo in theory the iret could fault and we'd still need this. */ + /** @todo this is a hack to correct the incorrect checking order for pending interrupts in the patm iret replacement code (corrected in the ring-1 version) */ + /** @todo in theory the iret could fault and we'd still need this. */ if ((env->hflags & HF_CPL_MASK) == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0) && !EMIsRawRing1Enabled(env->pVM)) { @@ -2561,6 +2561,8 @@ (RTGCPTR)env->eip, (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit, env->tr.flags, (RTSEL)(selector & 0xffff))); +# if 0 /** @todo r=bird: This looks very fishy, need good reason to re-enable it. */ ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT); +# endif #endif selector &= 0xffff; @@ -3186,5 +3188,4 @@ if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0)) { -# ifdef VBOX_WITH_RAW_RING1 if ( !EMIsRawRing1Enabled(env->pVM) || env->segs[R_CS].selector == (new_cs & 0xfffc)) @@ -3198,17 +3199,10 @@ Log(("Genuine switch to ring-1 (iret)\n")); } -# else - Log(("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc)); - new_cs = new_cs & 0xfffc; -# endif - } -# ifdef VBOX_WITH_RAW_RING1 - else - if ((new_cs & 0x3) == 2 && (env->state & CPU_RAW_RING0) && EMIsRawRing1Enabled(env->pVM)) + } + else if ((new_cs & 0x3) == 2 && (env->state & CPU_RAW_RING0) && EMIsRawRing1Enabled(env->pVM)) { Log(("RPL 2 -> new_cs %04X -> %04X\n", new_cs, (new_cs & 0xfffc) | 1)); new_cs = (new_cs & 0xfffc) | 1; } -# endif #endif } else {